KR20090071771A - Method for manufacturing isolation layer of semiconductor device - Google Patents

Abstract

A method for fabricating element isolation layer of semiconductor device is provided to implement the shallow trench having the different depth on the low voltage device part and high voltage device part by forming the first and the second shallow trench isolation layer which is gap filled in the trench of the semiconductor substrate. After successively laminating and patterning a pad insulating layer(102) and hard mask layers(104,106) on the top of semiconductor substrate(100), the mask pattern is formed. A part of the semiconductor substrate exposed by the mask pattern is etched to the first depth and the trench is formed within the high voltage device part and the low voltage device part. The trench of the high voltage device part is etched to the second depth by progressing the etching process using a photoresist pattern(112) masking the low voltage device part and making the high voltage device part open. Each trench formed in the semiconductor substrate is gap-filled and the element isolation layer is formed. After successively laminating the pad insulating layer and two or more hard mask layer on the top of the semiconductor substrate, the mask pattern is formed by patterning.

Description

METHODS FOR MANUFACTURING ISOLATION LAYER OF SEMICONDUCTOR DEVICE}

The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a device isolation film of a semiconductor device suitable for manufacturing a cell trench trench isolation film of different depths for a semiconductor device in which a high voltage device and a low voltage device is integrated. will be.

As the manufacturing technology of semiconductor devices is developed, the degree of integration of semiconductor devices has also increased, leading to the miniaturization of semiconductor devices. In the technology of miniaturization of semiconductor devices, in order to integrate devices, reduction technology of device isolation layers that separate devices is emerging as one of important items.

To cope with this, instead of LOCOS (LOCal Oxidation of Silicon) technology, which selectively grows a thick oxide film on a semiconductor substrate to form a device isolation film, a shallow trench device isolation film (STI: Shallow) can be used. Trench Isolation is widely used.

In a typical method of manufacturing a trench trench isolation film, a silicon oxide film (SiO ₂ ) is formed on a semiconductor substrate as a pad insulating film, and a silicon nitride film (SiN) is formed on the upper surface of the pad insulating film as a hard mask. .

Next, a photoresist pattern defining a shallow trench region is formed on the upper surface of the hard mask, and the hard mask and the pad insulating film are dry-etched, and then the semiconductor substrate is etched to a predetermined depth, for example, 3000 to 5000 mm, to form the trench trench. To form.

Subsequently, the trench trench isolation layer is manufactured in the semiconductor substrate by gap-filling the insulating film in the shallow trench and planarizing it by a chemical mechanical polishing (CMP) process to remove the remaining hard mask and the pad insulating film.

On the other hand, in semiconductor devices such as LDI (LCD Driver IC), low voltage transistors (e.g., 1.8V, 2.5V, 3.3V transistors) and high voltage transistors (e.g., 13.5V, 18V transistors) ) Is integrated into one wafer at the same time.

1 is a vertical cross-sectional view showing a device isolation layer structure of a high voltage and a low voltage semiconductor device according to the prior art.

Referring to FIG. 1, a pad insulating layer 12 and a hard mask 14 are stacked on a semiconductor substrate, and a shallow trench etched to a predetermined depth is formed in the semiconductor substrate 10 between the patterns. When the surface is planarized after gap filling, the shallow trench device isolation layer 16 is formed.

Here, in the low voltage element region A and the high voltage element region B, since the device isolation process is performed at the same time, the depth d of the shallow trench element isolation film is the same, but the width w of each region is the same. Are different from each other.

In the device isolation film manufacturing method according to the related arts described above, since the trench trenches of the high voltage device region and the low voltage device region are simultaneously formed, the trench depths of the respective regions are equal to each other.

However, in order to improve the device isolation characteristics of the high voltage device region and to reduce the design size, the photoresist pattern needs to be formed thick because the depth of the high voltage cell trench must be deeper than that of the low voltage cell trench. Forming a thick resist pattern causes a problem that it is difficult to reduce the trench width of the low voltage device region to a predetermined size or less.

Furthermore, since the trench depth ratio of the low voltage device region is the same as that of the high voltage device region, the trench aspect ratio of the low voltage device region is increased, resulting in poor gap fill characteristics of the low voltage trench, while void filling of the high voltage trench is not completed. Problem occurs.

Accordingly, the present invention reduces the trench width of the low-voltage device region by reducing the trench depth of the low-voltage device region by lowering the trench depth of the low-voltage device region, thereby improving the gap fill characteristics of the region, and at the same time, the high voltage. Provided is a device isolation film manufacturing method of a semiconductor device capable of increasing gap depth to facilitate gap fill.

According to one aspect of the present invention, there is provided a method of manufacturing a device isolation film of a semiconductor device having a high voltage device and a low voltage device, wherein a pad insulating film and a hard mask film are sequentially stacked on a semiconductor substrate and then patterned to form a mask pattern. Etching a portion of the semiconductor substrate exposed by the mask pattern to a first depth to form trenches in the high voltage device region and the low voltage device region, respectively, masking the low voltage device region, and forming the high voltage device region. Etching the trenches of the high voltage device region to a second depth by performing an etching process using an open photoresist pattern; and forming a device isolation layer by gap filling each trench formed in the semiconductor substrate. Provided is a device isolation film manufacturing method.

According to another aspect of the present invention, there is provided a method of manufacturing a device isolation film of a semiconductor device having a high voltage device and a low voltage device, wherein a pad insulating film and at least two hard mask films are sequentially stacked on a semiconductor substrate and then patterned to form a mask pattern. Forming a trench in a high voltage device region and a low voltage device region by etching a portion of the semiconductor substrate exposed by the mask pattern to a first depth, masking the low voltage device region, and masking the high voltage Etching the trench of the high voltage device region to a second depth by performing an etching process using a photoresist pattern to open the device region; removing an upper hard mask layer of the two hard mask layers; Gap isolation between trenches formed in the substrate to form an isolation layer Step provides a device isolation method for manufacturing a semiconductor device including a to.

According to another aspect, the present invention provides a method of manufacturing a device isolation film of a semiconductor device having a high voltage device and a low voltage device, the method comprising: sequentially depositing a pad insulating film and at least one hard mask film on an upper surface of a semiconductor substrate; Patterning the hard mask film and the pad insulating film formed in the device region to form a first mask pattern; and etching the semiconductor substrate of the low voltage device region exposed by the first mask pattern to a first depth to form a trench Forming a second mask pattern by patterning a hard mask film and a pad insulating film formed on the high voltage device region, and forming the semiconductor substrate of the high voltage device region exposed by the second mask pattern at the first depth; Forming a trench by etching to a second depth different from that of the semiconductor substrate; It provides a device isolation film manufacturing method of a semiconductor device comprising the step of forming a device isolation film by gap-filling each formed trench.

According to the present invention, the substrate of the low voltage device region is etched to a first depth using at least one hard mask and a pad insulating film having etch selectivity to form a first cell trench, and the substrate of the high voltage device region to a second depth. By etching to form the second narrow trench, a shallow trench having different depths may be implemented in the low voltage device region and the high voltage device region.

Accordingly, the present invention reduces the trench width of the low voltage device region by reducing the trench width of the low voltage device region by forming the trench depth of the high voltage device region deeper than the low voltage device region, thereby improving the gap fill characteristics of the region. The gap fill of the high voltage trench can be facilitated to prevent void generation.

SUMMARY OF THE INVENTION The present invention provides a low-voltage device region in which a pad insulating film and at least one hard mask film are sequentially stacked and patterned on a semiconductor substrate, and the substrate exposed by the pattern is shallowly etched to a first depth to form trenches. After masking and opening the high voltage device region, the trench of the high voltage device region is deeply etched to a second depth, and a gap isolation device isolation film is formed in the trench of the substrate. By reducing the width and reducing the aspect ratio of the low voltage trench, it is possible to improve the gap fill characteristics of the corresponding region and to facilitate the gap fill of the high voltage trench.

Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.

2A to 2E are flowcharts sequentially illustrating a process of fabricating a device separator of a high voltage and a low voltage semiconductor device according to an exemplary embodiment of the present invention.

Referring to FIG. 2A, as a pad insulating film 102 on a semiconductor substrate 100 such as silicon, a silicon oxide film (SiO ₂ ) is subjected to a thermal oxidation process, a chemical vapor deposition (CVD) process, or the like. Form. Here, the thickness of the pad insulating film 102 can be formed, for example in the range of about 500-2000 mm thickness.

Next, a silicon nitride film (SiN) is formed on the upper surface of the pad insulating film 102 as the first hard mask film 104. The first hard mask film 104 is subjected to a chemical vapor deposition (CVD) process or the like. It can be used, and the thickness can be formed in about 500 kV-2000 kPa range.

Subsequently, as the second hard mask film 106 having an etch selectivity on the upper surface of the first hard mask film 104, a silicon oxide film (SiO ₂ ) is formed in a range of approximately 500 kPa to 2000 kPa. The film 106 is thermally decomposed TEOS by low pressure chemical vapor deposition (LP-CVD) to deposit a silicon oxide film.

Referring to FIG. 2B, a process such as spin coating is performed to apply a photoresist to the upper surface of the second hard mask layer 106, and an exposure process using a mask defining an element isolation layer region is performed to expose the photoresist. Then, by developing it with a developer, a photoresist pattern 108 defining an element isolation region is formed on the second hard mask film 106.

Next, a dry etching process is performed to form a mask pattern by etching the second hard mask layer 106, the first hard mask layer 104, and the pad insulating layer 102 exposed by the photoresist pattern 108. The first narrow trench 110 having the first depth is formed by removing a portion of the semiconductor substrate 100 exposed by the mask pattern. A first portion formed by removing a portion of the semiconductor substrate 100 is formed. The depth is, for example, formed in the range of approximately 3000 Pa to 6000 Pa. At this time, the first shallow trench 110 is a trench formed in the low voltage device region A. FIG.

Here, the dry etching process may proceed to an etching process using an etching apparatus having a plasma source of a magnetically enhanced reactive ion (MERI) type, for example.

Referring again to FIG. 2C, a process such as ashing is performed to remove the photoresist pattern remaining on the second hard mask layer (), and a process such as spin coating is applied to apply the photoresist to the entire surface of the structure. The photoresist pattern 112 is formed by performing an exposure process using a mask that separates the low voltage device region A and the high voltage device region B, exposing the photoresist, and developing the photoresist with a developer. Here, the photoresist pattern 112 masks the substrate portion of the low voltage element region A having the first depth and opens the substrate portion of the high voltage element region B having the second depth. Have

Next, an etching process is performed to etch the trenches of the high voltage device region B opened by the photoresist pattern 112 to a second depth to form the second shallow trench 114 in the high voltage device region B. FIG. do. Here, the second narrow trench 114 of the high voltage element region B may be formed to a depth of about 7000 kPa to about 15000 kPa.

Therefore, the second shallow trench 114 formed in the high voltage device region B has a depth difference of about 4000 kPa to 9000 kPa compared to the first shallow trench 110 formed in the low voltage device region A. FIG. Here, the difference between the depth and the depth of the trench may be changed depending on the design of the semiconductor device.

Subsequently, a process such as ashing is performed to remove the photoresist pattern remaining on the high voltage small region as an example, as shown in FIG. 2D.

That is, according to the preferred embodiment of the present invention, the first narrow trench 110 having the first depth is formed in the low voltage device region A, and the high voltage device region B has a predetermined depth than the first depth. A second narrow trench 114 is formed having a second depth relatively deeper by value.

Referring again to FIG. 2E, a gap fill insulating film is deposited on the entire surface of the semiconductor substrate 100 on which the first and second shallow trenches 110 and 114 are formed by a process such as chemical vapor deposition (CVD) to completely gap fill the trench. do.

For example, chemical vapor deposition processes include LPCVD to deposit TEOS (Tetra Ethyl Ortho Silicate) at low pressure, APCVD to deposit TEOS and ozone at atmospheric pressure, sub-atmospheric pressure. SACVD for depositing TEOS and ozone, or High Density Plasma CVD (HDP-CVD) may be used.

Next, a planarization process such as chemical mechanical polishing (CMP) or the like is performed to planarize the gap fill insulating film until the surface of the second hard mask film 106 is exposed, thereby reducing the low voltage device region A and the high voltage device region B. First and second narrow trench device isolation layers 116 and 118 are formed in each trench.

Although not shown in the drawings, a process of etching and removing the second hard mask film 106, the first hard mask film 104, and the pad insulating film 102 remaining on the semiconductor substrate 100 may be removed. You will proceed.

Therefore, according to an embodiment of the present invention, a pattern for trenches is formed by using two hard masks and an etch selectivity pad pad insulating layer, and the low voltage device region exposed by the pattern has a first depth in the substrate of the high voltage device region. The first cell trench is etched to form a second cell trench, and the second cell trench is etched again to have a second depth, so that each cell has a different depth in the low voltage element region and the high voltage element region. Low trenches can be realized.

3A to 3C are flowcharts sequentially illustrating a process of fabricating a device separator of a high voltage and a low voltage semiconductor device according to another exemplary embodiment of the present invention.

Referring to these drawings, the manufacturing process according to another embodiment of the present invention selectively removes only the second hard mask film before proceeding the gap fill process of the trench in one embodiment as follows. Here, the process of forming the second hard mask film is the same as in the embodiment shown in FIG. 2.

Referring to FIG. 3A, the pad insulating film 102, the first hard mask film 104, and the second hard mask film 106 are sequentially stacked on the semiconductor substrate 100, and the second hard mask film 106 is stacked. The first hard mask film 104 and the pad insulating film 102 are dry-etched to form a mask pattern, and the semiconductor substrate exposed by the mask pattern is etched to a first depth, for example, approximately 3000 to 6000 microseconds, so as to form a first pattern. Form the trench 110.

Next, the low voltage element region A is masked, a photoresist pattern for opening the high voltage element region B is formed, and the trenches of the high voltage element region B opened by the photoresist pattern become a second depth. The second shallow trench 114 is formed in the high voltage device region B by etching, and the second depth of the second narrow trench 114 in the high voltage device region B is about 7000 Pa to 15000 Pa. .

Subsequently, a process such as ashing is performed to remove the remaining photoresist pattern, and a wet process is performed again, for example, to remove the second hard mask film as shown in FIG. 3B as an example. As a result, the aspect ratio can be reduced during the gap fill process of the subsequent trenches.

Referring back to FIG. 3C, a gap fill insulating film is deposited on the entire surface of the semiconductor substrate 100 on which the first and second narrow trenches are formed by chemical vapor deposition (CVD) to completely gap fill the trench.

For example, the chemical vapor deposition process of the gapfill insulating film may be performed by LPCVD to deposit TEOS at low pressure, APCVD to deposit TEOS and ozone (O ₃ ) at atmospheric pressure, SACVD to deposit TEOS and ozone (O ₃ ) under atmospheric pressure, or high density plasma. An oxide film deposition (HDP-CVD) process or the like can be used.

Subsequently, a planarization process such as chemical mechanical polishing (CMP) is performed to planarize the gapfill insulation film until the surface of the first hard mask film 104 is exposed, thereby reducing the low voltage device region A and the high voltage device region B. First and second narrow trench device isolation layers 116 and 118 are formed in each trench.

Subsequently, although not shown in the drawing, the etching process is performed to remove the first hard mask layer 104 and the pad insulating layer 102 remaining on the semiconductor substrate 100, thereby reducing the cell according to the present exemplary embodiment. Complete the trench device separator manufacturing process.

Accordingly, according to another exemplary embodiment, a pattern for trenches is formed by using two hard masks and a pad insulating film having etch selectivity, and the substrates of the low voltage device region and the high voltage device region exposed by the pattern are at a first depth. By etching to form a first narrow trench, etching the high voltage device region again to have a second depth to form a second narrow trench, removing only the hard mask at the top, and then gapfilling the gapfill insulating film in the trench, A cell trench trench isolation layer having different depths may be manufactured in the low voltage device region and the high voltage device region, respectively.

4A through 4C are flowcharts sequentially illustrating a process of fabricating a device isolation layer of a high voltage and a low voltage semiconductor device according to another exemplary embodiment of the present invention.

Referring to FIG. 4A, a silicon oxide film SiO ₂ is formed on the semiconductor substrate 200 as a pad insulating film 202, and a silicon nitride film SiN is formed thereon as a hard mask film 204.

Next, a photolithography process using a mask defining a narrow trench region is performed to form a photoresist pattern 205 on the top surface of the hard mask film 204, and the hard mask exposed by the photoresist pattern 205. The film 204 and the pad insulating film 202 are dry etched to form a mask pattern.

Subsequently, the first substrate trench 206 is formed by etching the semiconductor substrate 200 exposed to the mask pattern to a first depth, for example, about 3000 Å to about 6000 Å. The resist pattern is removed.

Referring to FIG. 4B, a photoresist is applied to the entire surface of the structure in which the first cell trench is formed, a photo process using a mask defining a low voltage device region is performed to mask the low voltage device region A, and the high voltage device A photoresist pattern 208 that opens the region B is formed.

Next, the trench of the high voltage element region B opened by the photoresist pattern 208 is etched to have a second depth, for example, 7000 Å to 15000 하여, and the second narrow trench 210 may be etched in the high voltage element region B. FIG. ) Is formed, and then a process such as ashing is performed to remove the remaining photoresist pattern 208.

Referring again to FIG. 4C, a gap fill insulating film is deposited on the entire surface of the semiconductor substrate 200 on which the first and second narrow trenches are formed by chemical vapor deposition (CVD) to completely gap fill the trench.

For example, the chemical vapor deposition process of the gap-fill insulating film may include LPCVD for depositing TEOS at low pressure, APCVD for depositing TEOS and ozone (O ₃ ) at atmospheric pressure, SACVD for depositing TEOS and ozone (O ₃ ) at atmospheric pressure, or high density. A plasma oxide film deposition (HDP-CVD) process or the like.

Next, a planarization process such as chemical mechanical polishing (CMP) is performed to planarize the gap fill insulating film until the surface of the hard mask film 204 is exposed, thereby forming trenches in the low voltage device region A and the high voltage device region B. FIG. First and second gap trench device isolation layers 212 and 214 are formed in the gaps.

Subsequently, although not shown in the drawing, the hard mask layer 204 and the pad insulating layer 202 remaining on the semiconductor substrate 200 are etched to complete the process of manufacturing the trench trench isolation layer of the present embodiment.

Therefore, according to another embodiment of the present invention, a pattern for a trench is formed using a hard mask and a pad insulating film, and the substrates of the low voltage device and the high voltage device region exposed by the pattern are etched to a first depth to form a first pattern. By forming a trench trench and etching the trench of the high voltage device region back to a second depth to form a second trench trench, a shallow trench having a different depth in the low voltage device region and the high voltage device region may be realized. have.

5A through 5D are process flowcharts sequentially illustrating a process of fabricating a device isolation layer of a high voltage and a low voltage semiconductor device according to another exemplary embodiment of the present invention.

Referring to FIG. 5A, a silicon oxide film SiO ₂ is formed on the semiconductor substrate 300 as a pad insulating film 302, and a silicon nitride film SiN is formed thereon as a hard mask film 304.

Next, a photolithography process using a mask defining a trench region of the low voltage device is performed to form a photoresist pattern 306 on the upper surface of the hard mask film 304, and the hard exposed by the photoresist pattern 306. The mask film 304 and the pad insulating film 302 are dry-etched to form a mask pattern on the substrate of the low voltage device region A. FIG.

Subsequently, the semiconductor substrate of the low voltage element region A exposed by the mask pattern is etched to a predetermined first depth, for example, about 3000 Å to 6000 Å to form a first shallow trench 308, and then ashing or the like. The process proceeds to remove the remaining photoresist pattern.

Referring again to FIG. 5B, a photoresist is applied to the entire surface of the structure in which the first narrow trench is formed, and the low voltage device region A is formed by performing an exposure and development process using a mask defining a trench region of the high voltage device. The photoresist pattern 310 defining the trench region is formed while masking and opening the high voltage device region B.

Next, the hard mask film 304 and the pad insulating film 302 of the high voltage device region B opened by the photoresist pattern 310 are dry-etched to form a mask pattern on the substrate of the high voltage device region B. .

Subsequently, the semiconductor substrate of the high voltage device region B exposed by the mask pattern is etched to a second depth relatively deeper than the first depth described above, for example, about 7000 kPa to 15000 kPa, and the second cell is formed on the high voltage device region B. FIG. A row trench 312 is formed, and then, as an example, as shown in FIG. 5C, a process such as ashing is performed to remove the remaining photoresist pattern.

Referring again to FIG. 5D, a gap fill insulating film is deposited on the entire surface of the semiconductor substrate 300 on which the first and second narrow trenches are formed by chemical vapor deposition (CVD) to completely gap fill the trench.

For example, the chemical vapor deposition process of the gap-fill insulating film may include LPCVD for depositing TEOS at low pressure, APCVD for depositing TEOS and ozone (O ₃ ) at atmospheric pressure, SACVD for depositing TEOS and ozone (O ₃ ) at atmospheric pressure, or high density. A plasma oxide film deposition (HDP-CVD) process or the like.

Next, a planarization process such as chemical mechanical polishing (CMP) and the like is performed to planarize the gap fill insulating film until the surface of the hard mask film 304 is exposed, thereby forming respective trenches of the low voltage device region A and the high voltage device region B. FIG. The gapfill first and second shallow trench isolation layers 314 and 316 are formed.

Subsequently, although not illustrated, the hard mask layer 304 and the pad insulating layer 302 remaining on the semiconductor substrate 300 are etched to complete the process of manufacturing the trench trench isolation layer.

Therefore, according to another embodiment of the present invention, a pattern of the low voltage device region is formed using a hard mask and a pad insulating film, and the substrate of the low voltage device region exposed by the pattern is etched to a first depth to form a first cell. Forming a trench, forming a pattern of the high voltage device region, and etching the substrate of the high voltage device region exposed by the pattern to a second depth to form a second narrow trench, thereby forming each other in the low voltage device region and the high voltage device region, respectively. It is possible to implement shallow trenches with different depths.

In the above description has been described by presenting a preferred embodiment of the present invention, the present invention is not necessarily limited thereto, and those skilled in the art to which the present invention pertains should be within the scope not departing from the technical spirit of the present invention. It will be readily appreciated that various substitutions, modifications, and variations are possible.

1 is a vertical cross-sectional view showing a device isolation film structure of a high voltage and low voltage semiconductor device according to the prior art,

2A through 2E are process flowcharts sequentially illustrating a process of manufacturing a device separator of a high voltage and a low voltage semiconductor device according to an exemplary embodiment of the present invention;

3A to 3C are process flowcharts sequentially illustrating a process of fabricating a device separator of a high voltage and a low voltage semiconductor device according to another exemplary embodiment of the present invention;

4A through 4C are process flowcharts sequentially illustrating a process of fabricating a device separator of a high voltage and a low voltage semiconductor device according to another exemplary embodiment of the present invention;

5A to 5D are process flowcharts sequentially illustrating a process of fabricating a device separator of a high voltage and a low voltage semiconductor device according to another exemplary embodiment of the present invention.

<Description of the code | symbol about the principal part of drawing>

100, 200, 300: semiconductor substrate

102, 202, 302: pad insulating film

104: the first hard mask film

106: second hard mask film

108, 112, 205, 208, 306, 310: photoresist pattern

110, 206, 308: first shallow trench

114, 210, 312: second shallow trench

116, 212, and 314: first shallow trench isolation layer

118, 214, 316: second shallow trench device isolation membrane

204 and 304: hard mask film

A: low voltage device area

B: high voltage device region

Claims (6)

A method of manufacturing a device isolation film of a semiconductor device having a high voltage device and a low voltage device, Forming a mask pattern by sequentially stacking and patterning a pad insulating film and a hard mask film on the semiconductor substrate; Etching a portion of the semiconductor substrate exposed by the mask pattern to a first depth to form trenches in the high voltage device region and the low voltage device region, respectively; Etching the trench of the high voltage device region to a second depth by performing an etching process using a photoresist pattern for masking the low voltage device region and opening the high voltage device region; Forming a device isolation layer by gap filling each trench formed in the semiconductor substrate Device isolation film manufacturing method of a semiconductor device comprising a. A method of manufacturing a device isolation film of a semiconductor device having a high voltage device and a low voltage device, Forming a mask pattern by sequentially stacking and patterning a pad insulating film and at least two hard mask films on the semiconductor substrate; Etching a portion of the semiconductor substrate exposed by the mask pattern to a first depth to form trenches in the high voltage device region and the low voltage device region, respectively; Etching the trench of the high voltage device region to a second depth by performing an etching process using a photoresist pattern for masking the low voltage device region and opening the high voltage device region; Removing an upper hard mask film of the two hard mask films; Forming a device isolation layer by gap filling each trench formed in the semiconductor substrate Device isolation film manufacturing method of a semiconductor device comprising a. The method of claim 2, And the upper hard mask film is a silicon oxide film. The method of claim 3, wherein The silicon oxide film is a device isolation film manufacturing method of a semiconductor device, characterized in that the deposition by thermal decomposition of TEOS by low pressure chemical vapor deposition (LP-CVD) method. The method according to any one of claims 2 to 4, And the upper hard mask layer is removed by a wet etching process. A method of manufacturing a device isolation film of a semiconductor device having a high voltage device and a low voltage device, Sequentially depositing a pad insulating film and at least one hard mask film on the semiconductor substrate; Patterning the hard mask film and the pad insulating film formed in the low voltage device region to form a first mask pattern; Etching the semiconductor substrate in the low voltage device region exposed by the first mask pattern to a first depth to form a trench; Patterning the hard mask film and the pad insulating film formed in the high voltage device region to form a second mask pattern; Etching the semiconductor substrate of the high voltage device region exposed by the second mask pattern to a second depth different from the first depth to form a trench; Forming a device isolation layer by gap filling each trench formed in the semiconductor substrate Device isolation film manufacturing method of a semiconductor device comprising a.

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