SU720539A1 - Redundancy storage - Google Patents

Description

one

The invention under discussion relates to qi (digital computing technology and can be used as a backup memory device (RAM) in various types of computing devices to protect against memory failure.

A redundant storage device is known that contains an address register, the outputs of which are connected to the drive inputs, the outputs of which are connected to the corresponding word registers, a code equality circuit, the inputs of which are connected to the outputs of the word register and the other the input of which is connected to the control unit, and the output is connected to one of the word registers, the OR circuit, the AND circuit group by the number of drives and the output register, additional word registers by the number of drives, the inputs of which are connected to the outputs of the corresponding main registers of the word scheme

serial checks by the number of accumulators, one inputs of which are connected to the outputs of the corresponding main word registers, S) or — to the outputs of additional word registers, and outputs to the control inputs of groups, circuits I, information inputs of which are connected to the control unit, and outputs - to the inputs of the corresponding main registers of the word, the outputs of which through the scheme OR are connected to the output register til.

A disadvantage of the known device is that in order to correct errors, it is necessary to repeat and read information from the memory device, which is unacceptable in high-speed devices, and for long-term (constant) storage devices it is impossible.

The closest in technical essence is a device containing main and backup memory blocks, the outputs of which are connected to the first

the inputs of the registers with the second inputs of which are connected to the bus installation, the number of BS registers to the zero position, and the outputs of the numerical registers are connected to the first inputs of the valves, the second inputs of the backup memory block connectors are connected to the information register The second inputs of the main unit gates are connected to the buses that remove the code from the numeric registers of the main memory blocks. The gates of the backup module are connected to the corresponding third inputs of the numerical registers. moat work modules and working valves vosody mo rupey connected to the code rails 23

The disadvantage of this device is that the failure of the different nominal bits of two or three memory blocks does not parry, since the information of the first main unit from the restoring unit is restored using all of the bits of the healthy main AND; backup block memory (it is considered that all bits of the memory block fail at the same time). Therefore, subsequent failures of the remaining memory blocks are not countered.

The purpose of the invention is to improve the reliability of the device. This is achieved by the fact that the proposed device contains control and monitoring units,

registers of failures and control, two adders, elements AND, NOT and OR, and the same-name bits of the main and backup memory blocks are connected to the inputs of modulators two, the outputs of which are connected to the first inputs of the control register and through the OR element to the input control unit, the outputs of the control unit are connected to the first inputs of the control unit, the second inputs of which are connected to the outputs of the control register, the outputs of the control unit are connected to the inputs of the failure registers, the same outputs of which are connected to the terminals, The third and fourth inputs of the corresponding first And elements, the outputs of the first and second fault registers are NOT connected to the first inputs of the second And elements, the second inputs of which are connected to the outputs of the corresponding modulators two, and the outputs of the second And elements are connected to the control inputs number: registers.

The drawing is a functional block diagram of a redundant device.

The device contains basic I, 2

and backup 3 memory blocks, control block 4, control block 6, registers 6-8 failure, control register 9, modulators Yu, II modulo two, first AND control elements,

the second control elements are 16–17 and the elements 18–21 are NOT the element 22 OR, the first and second numeric registers are 23, 24.

The device works as follows. The information obtained by bitwise modulo two words with the same addresses from the main memory blocks are stored in the backup memory block. The initial states of registers 6-8 - 10 ... 1 I, register. 9 00 ... 00. Information from the main memory blocks 1.2 and the backup memory block 3 is fed to the inputs of the adders 10, 11 modulo two. In case of failure

one of the bits of the memory block at the output of the corresponding modulo-two adder has an error signal. Control register 9 is designed to store information about a failed bit. The result of the modulo-two summing is fed to the inputs of the control register 9 from the outputs of the adders 1О, 11 modulo da through the control elements 16, 17 And intended to generate a control signal in the absence of a block. By control signal

control unit 5 determines which of the memory blocks has failed, and the information

This is entered into control block 4, which generates control signals, according to which information from control register 9 is copied in inversion into one of registers 6-8.

the call corresponding to the failed memory block, after which the register 9 is set to the zero state. In the process of further functioning, the operational correction of the

failure occurs as follows. Information from the main blocks 1, 2 of memory and the backup block 3 of memory is fed to the inputs of numeric registers 23, 24. Elements 12-15

Claims (2)

The control And writing to these registers is made up of outputs of registers 7, 8 failures (through elements 18-21 NOT) and outputs of adders 10, 11 modulo two. If at least one of the fault registers contains information about the discharge failure (logical ... O) and the output of the identical modulo two adder has an error signal, then the corresponding control element and the information of the failed digit from the main memory unit will be written into the corresponding numeric register not in the direct code, as in the normal mode and in the reverse, which corresponds to the correct value of the bit. The processing of subsequent failures of the razP1shchov blocks 1 to 3 of memory occurs in a similar way. In this case, in case of detection by the adders 1O, 11, errors in bits, the failures of which were previously recorded by registers 6-8, the generation of the control signal does not occur, since the operation of the corresponding element 16, 17 And control is blocked by logical O bits of registers 6-8 Thus, an increase in the reliability of the device compared to the prototype is provided by parrying up to Si failures of independent bits, (t is the cube width), as in the device implemented according to the method described in the prototype pairing with only one failure. Claims of the invention A redundant memory device containing main and backup memory blocks, numeric registers, 39 informational inputs are connected to the corresponding outputs of the main memory blocks, characterized in that, in order to increase the reliability of the device, it contains control and monitoring units. fault and control registers, modulo-two adders, AND, NOT and OR elements, with the same outputs of the main and backup memory blocks connected to the inputs of modulo-two adders, all of which are connected with the first inputs of the first elements AND, the outputs of which are connected to the inputs of the control register and through the OR element to the input of the control unit, the outputs of the control unit are connected to the first inputs of the control unit, the second inputs of which are connected to the outputs of the control register, the outputs of the control unit , the single-output outputs of which are connected to the second, third, and fourth inputs of the corresponding first AND elements, the output of the first and second failure registers through the elements are NOT connected to the first inputs of the second And, the second inputs of which are connected to the outputs of the corresponding modulo-two adders, are connected to the outputs of the second And elements to control inputs of the numerical registers. Sources of information taken into account when examining 1. USSR author's certificate No. 385319, cl. G 11 C 29 / OO, 1973. 2. USSR author's certificate number 217458, cl. N OZ K 37/00, 1967 (PROTOTYPE). I I G 1I - M t t ±. "I I J I /" G 61 but , №, В. /9