SU1167659A1 - Storage with self-check - Google Patents

Abstract

1. A SELF-MONITORING STORAGE DEVICE containing a memory unit whose address inputs are device address inputs, a coding unit whose inputs are connected to information inputs of a first group of a memory block and are information outputs of a device, a control unit, outputs and inputs of the first group which are respectively the control outputs and the inputs of the device, the decoding unit, the outputs of the first group of which are connected to the inputs of the second group of the control unit, the error correction block, the inputs of the the second and second groups of which are connected respectively to the outputs of the second group of the decoding block and the inputs of the first group of the decoding block, which are also connected to the outputs of the memory block, the control inputs of which are connected to the outputs of the second group of the control block and the control inputs of the second group of the decoding block, different in order to improve the accuracy of self-control, it contains an error detection block, the first and second switches, and the inputs of the first group and the outputs of the first switch are connected respectively with the outputs of the coding unit and information inputs of the second group of the memory block, and the inputs of the second group of the first switch are connected to the inputs of the third group of the control unit, the outputs of the error detection unit, the control inputs of the third group of the decoding unit and the inputs of the first group of the second switchboard, the inputs of the second and The third groups of which are connected to the outputs of the error correction block and the third group of the control unit, respectively, the i inputs of the fourth group of the second switch are information inputs and (L devices, and the outputs are connected to the inputs of the coding unit and the inputs of the first group of the error detection unit, the inputs of the second, third, fourth and fifth groups of which are connected respectively to the outputs of the fourth group of the control unit, the address inputs of the memory unit, the outputs of the first group of the unit decoding and outputs on the memory block. 2. The device according to claim 1, characterized in that Od that the error detection block contains a switch and a register, the outputs of which are outputs of the block, one of the inputs from the register is connected to the outputs of the switch, and the other inputs of the register and the inputs of the third switch are corresponding inputs of the block.

Description

The invention relates to computing and can be used to create storage systems of increased reliability, performed on functional units of a high degree of integration, and also used in computer systems for implementing hardware and software control of equipment.

The purpose of the invention is to reduce hardware costs and expand functionality due to the possibility of implementing software and hardware control of device blocks.

FIG. 1 shows the structural scheme of the proposed self-monitoring storage device; in fig. 2 shows functional diagrams of a decoding unit and a diagnostic unit.

The device comprises a memory block 1, a decoding block 2, an error detection block 3, a control block 4, a first 5 switch, a coding block 6, an error correction block 7, a second 8 switch, address buses 9, input data inputs 10, data outputs 11, control inputs 12, response outputs 13 and errors.

Memory block 1 contains a memory 14 and a data register 15 consisting of two parts: information 16 for recording information bits of a word to be read and control part 17 for recording test bits of a word. The information inputs of the accumulator 14 are associated with the first and second group of information inputs of the memory unit 1, and the address inputs of the storage unit are the address inputs of the memory unit 1. Information outputs of the accumulator are connected to the information inputs of both parts of the data register 15: information and control, whose information outputs are connected to the first inputs of block 2. In addition, the outputs of the information part 16 of the data register 15 are connected to the first inputs of the error correction block 7, and the outputs of the control part The 17 registers are connected to the first inputs of the error detection unit 3. The control inputs of accumulator 14 and register 15 are the control inputs of memory block 1.

The decoding unit 2 (Fig. 2) contains an error syndrome generator 18, an error discrimination discrimination unit 19 and a fault discharge decider 20. The inputs of the generator 18 are the first inputs of the decoding unit, and the outputs of the decoder are connected to the inputs of the error discrimination unit 19 and the decoder 20, the second and third inputs of the decoding unit 2 are connected to the second inputs. The outputs of block 19 and de-blender 20 are respectively the second and first output of block 2 and are respectively connected to the second inputs of block 3

error detection and error correction block 7.

The error discrimination block 19, which is part of the decoding block 2, contains a parity generator 21 with a control input, AND-NO elements 22-27, AND-OR element 28, OR-NOT element 29.

The error detection unit 3 (FIG. 2) consists of a switch 30 and a register 31 containing bit 32 of a multiple error, bit 33 of a single error, bits 34 for storing the address or check bits of bit 35 of the diagnostic test mode, bit 36 of the correction lock, bit 37 permission to issue an error.

The device works as follows.

When performing a write operation in the address address memory 9, the address of the address (the address of the cell to be accessed) is sent, data buses 10 receive data, and, in control 12, a memory write signal by which control unit 4 generates a control sequence. signals for recording data in memory block 1. According to signals from control block 4, data switch 8 transmits data from data strip 11 to input of memory block 1 and coding block 6, which generates check bits for incoming data according to the received signal coding, for example, in a modified Hamming code according to Table. one.

The information bits in the modified Hamming code are encoded with code patterns containing 3 units each, and the check bits with code patterns containing 1 unit each. Thus, the number of units in a code combination is always odd. With an even number of units in the code combination there will be a double or a larger error. Moreover, the code combinations are chosen so that the formation of each control bit involved no more than eight information bits and the formation of the control bits were performed in parallel independently of each other, which allows for maximum performance in the formation of the control bits.

The generated check bits are transmitted to the memory 1 by the switch 5 check bits in the presence of an enable signal from the block 3. The control signals from the control block 4 are used to record information in the cell of the memory 1 determined by the address arriving at the 9 addresses. After the response signal is sent to the response and error bus 13, the write operation to the memory ends. When performing a read operation from the memory, the control bus 12 receives a read signal from the memory. The control unit 4 generates a sequence of control signals that are used to read information from a cell defined by the address supplied to address 9. After reading from the accumulator, the information is entered into the data register 15 by the gate coming from the control unit 4. Unit 2 controls the information coming from the data register 15 and forms the total syndrome. If the syndrome is zero, this means that there are no errors in the read information and information bits are transmitted through block 7 from the data register 15 to the input of the data switch 8 without any changes. The operation of the decoder 20 faulty discharge in this case is prohibited. The data switchboard 8 on the control signals from the control unit 4 transfers data to the data buses 11 on the data output signal generated by the control unit 4. If at least one discharge of the syndrome is equal to one, then there is an error in the information read: single (adjustable) or multiple (non-adjustable). If the code of the syndrome obtained has an odd number of units and coincides, for example, with one of the codes given in Table. 1, a single (correctable) error occurs, which is detected by block 19. Information about a single error is entered into block 3, and also goes to control block 4, which generates a signal for enabling the decoder 20 to have a faulty bit. The decoder 20 determines the faulty bit and, in block 7, corrects it. The corrected information via the switch 8 of data on the control signals from the control unit 4 is output to the device output 11. Information about a single error can be read when referring to block 3. If the code of the resulting syndrome has an even number of units or an odd number of units, but it coincides, for example, with one of the codes given in Table. 2, then there is a multiple (uncorrectable) error, which is detected by block 19. Error information is entered into block 3, and also fed to control block 4, which in this case stops the decoder 20 of the faulty discharge, generates a sequence of control signals to transmit information without changes to the output of the device through the data switch 8, and also exposes an error signal to the response and error buses 13, information about the repeated error can be read when accessing block 8 (in all considered In case of tires 13, a response signal is set). When a correction blocking signal is received from block 3, a single error is perceived by block 19 as a multiple (uncorrectable) error. The control unit 4 at the same time blocks the operation of the defective bit decoder 20 and generates an error signal on the response and error buses 13. When performing a write operation in block 3, the data switch 8 transmits information from the input data bus 10 to the input of block 3. By the gate coming from block 4, this information is entered into block 3, after which control block 4 generates a response signal. When performing a read operation from block 3, control block 4 generates a sequence of signals for transmitting information from block 3 output through data switch 8 to data bus II, and also generates a response signal. During preventive and diagnostic checks of the device, as well as when the device operates on operating systems as part of the computing complex, using block 3, various modes of operation of the device and block 3 can be set. When bit 37 of the error resolution is set to zero, the error signal is output to the buses 13 responses and errors by the control unit 4 are not performed. When setting the correction block bit 36, a single error is perceived as multiple (uncorrectable error). If bit 35 of the diagnostics mode of checks of block 3 is set to zero, then the normal operation of the device takes place, in which, upon detection of multiple (uncorrectable) errors, bits 34 for entering the address or check bits are filled with the highest bits of the error address. If bit 35 is set to one, then a diagnostic mode of operation of the device takes place, in which, in a write operation, instead of the check bits generated by the coding unit 6, the check bits written from the processor to bits 34 of the block are recorded 3. The writing of these check bits in memory block 1 is ensured by switching the switch 5 check bits to bit 35 of the mode of diagnostic checks for the direction of the transfer of check bits from the block 3. When reading information 1 from the memory block in this case block 3 will instead zanosits MSB address few control bits that can be read when reading information from the block 3. crush various known combinations of information bits, writing them together with the formed block 6

encoding the test bits into the 1-memory block in the normal recording mode and reading them in the diagnostic mode, determines the correct functioning of the coding unit 6.

Writing through the block 3 in the diagnostic mode various code combinations of the check bits under a certain code combination of the information bits in the block 1 of the memory, thereby artificially introducing single and multiple errors, and then reading the recorded information, determine the correct functioning of the block 2 decoding, block 3, block 7.

By writing to the memory block 1 and reading the information, the correct functioning of the memory block 1 is determined.

In this way, a hardware-software check of self-monitoring storage units is provided.

Correspondence of information and control bits to their binary representation in a modified Hamming code

Table 1

Bit number yes

16 17 18 19 20 21

о о о о о 1 Codes of odd uncorrectable errors

eight

Continued table. one

Syndrome code

z: r 2

about 1

about about 1

one

oh oh oh 1 oh

ABOUT

oh oh oh

ABOUT

Ltd

Ltd

table 2

W 11

Claims (2)

1. A MEMORY DEVICE WITH SELF-CONTROL, containing a memory block, the address inputs of which are the address inputs of the device, a coding block whose inputs are connected to the information inputs of the first group of the memory block and are information outputs of the device, the control unit, the outputs and inputs of the first group of which are respectively control the outputs and inputs of the device, the decoding unit, the outputs of the first group of which are connected to the inputs of the second group of the control unit, the error correction unit, the inputs of the first and which groups are connected respectively to the outputs of the second group of the decoding unit and the inputs of the first group of the decoding unit, which are also connected to the outputs of the memory unit, the control inputs of which are connected to the outputs of the second group of the control unit and the control inputs of the second group of the decoding unit, characterized in that, with In order to increase the accuracy of self-monitoring, it contains an error detection unit, first and second switches, and the inputs of the first group and the outputs of the first switch are connected respectively to the strokes of the coding unit and the information inputs of the second group of the memory unit, and the inputs of the second group of the first switch are connected to the inputs of the third group of the control unit, the outputs of the error detection unit, the control inputs of the third group of the decoding unit and the inputs of the first group of the second switch, the inputs of the second and third groups of which are connected with the outputs, respectively, of the error correction block and the third group of the control unit, the e inputs of the fourth group of the second switch are the information inputs of the device, and the outputs The odes are connected to the inputs of the encoding unit and the inputs of the first group of the error detection unit, the inputs of the second, third, fourth, and fifth groups of which are connected respectively to the outputs of the fourth group of the control unit, address inputs of the memory unit, outputs of the first group of the decoding unit, and outputs of the memory unit. 2. The device according to π. 1, characterized in that the error detection unit contains a third switch and a register, the outputs of which are the outputs of the unit, one of the inputs of the register is connected to the outputs of the switch, and the other inputs of the register and inputs of the third switch are the corresponding inputs of the block.