SU1651297A1 - Device for histogram shaping - Google Patents

Abstract

The invention relates to computing and measuring technology and, in particular, can be used to analyze binary images. The aim of the invention is to expand the class of tasks by forming two-dimensional histograms. The device contains counters 1 and 2, groups 12 and 13 of elements I, group 16 of counters, blocks 6 and 7 of addition, blocks 9 and 10 of memory, elements NOT 11.14 and 15, elements OR 3-5, element AND 8. 1 silt

Description

The invention relates to computing and measurement technology and can be used to analyze binary images.

The aim of the invention is to expand the class of tasks by forming two-dimensional histograms.

The following algorithm is proposed for generating a two-dimensional histogram of a binary image.

The one-dimensional histogram of the binary image can be represented as

G G ° G1

where G and G are, respectively, the numbers of zero and unit elements in a binary image.

By analogy, we present a two-dimensional histogram of a binary image as follows:

G °° G011, (1)

.G10Ј11

G lg

where G °°, G01, d10, G11 are, respectively, the number of pairs of elements 0-0.0-1.1-0.1-1 contained in this binary image. The elements of the matrix (1) are

an integral estimate of the number of pairs of elements of a certain luminance calculated independently of the spatial arrangement of these pairs, i.e. values (g, 0). When taking into account the spatial arrangement of the pairs, each element of the matrix (1), in turn, is represented by a set of values of the numbers grg of the pairs 0-0, 0-1, 1-0, 1-1 with parameters (g, c.

Since the elements of the binary image X xj.j, where x | Ј {0,1}, (i, j) 6 {lx3} are set on a rectangular raster, then the parameters r, 6 can be expressed in the Cartesian coordinate system in terms of the relative displacements of the elements of the pair along the abscissa axis (t) and the ordinate axis (n) :

in / m2 -Hi2arctg Ј.

cl

with

Och

ate

ten

Yu

V4

To find the total number of pairs of a certain type with a given offset m and n, it is necessary to calculate the following expressions:

-00 Зт, п

p Ј 2i - t, J -n,

$. Ј Ј Xlj.X | -m, J-m

ff t 1i 1

Jl

xij.xi - m. Jn

9.p- 2, 2,

i

f

X | j xi - m, J - n,

where (1st, Jn) e-lxJ.

Calculating the samples of the histogram of a binary image using formula (2) allows you to create both one-dimensional and two-dimensional histograms.

The drawing shows a block diagram of the device.

The device contains address counters 1 and 2, elements OR 3 - 5, blocks 6 and 7 of addition, element AND 8, blocks 9 and 10 of memory, element NOT 11, groups 12 and 13 elements And, elements NOT 14 and 15, group 16 accumulating counters, group 17 of information outputs, information input 18, mode setting input 19, inputs 20 and 21 of the ordinate setting and image displacement abscissa, start output 22, calculation end output 23, synchronization input 24 and clock input 25.

A device for forming histograms works as follows.

Preliminarily, information samples 18 are loaded with binary image samples X xij. At the same time, at the inputs 21 and 20, the values m 0 are set. N 0. And the signal O (loading mode) is set at the input 19 of the device mode setting. When a start signal is given, the input of the sync pulse to the device input is allowed. The trigger signal resets the address counters 1 and 2 in the presence of a pulse at the synchronization input 24. The trigger signal is reset by the decay of the first pulse at sync input 24. When loading samples of the original binary image, addresses are generated using address counters 1 and 2, and counter 1 generates the value of address I -1J. counter 2 generates the value of I TdG. The counting input of the address counter 2 receives clock pulses from the input 25. With the overflow of the counter 2, it is zeroed out and an increase by one in the state of the counter 1. With each pulse at the input 25, identical address addresses are set at the address inputs of blocks 9 and 10. Writing to blocks 9 and 10 of the memory of input samples arriving at input 18 is made in accordance with the arrival of synchronizing pulses at input 24. At the formation of the largest write addresses I and 3, counters 1 and 2 are set simultaneously at 0 and output 23 is generated calculations

When forming the histogram values, the device operates in accordance with

expression (2). In this case, the input 19 is set to 1 (mode of operation), which, upon receipt of clock pulses on the input 24, permits data reading

from memory blocks. At the inputs 21 and 20, the values of the type are set in additional codes. The formation of the histogram values starts from the moment the signal is fed through the input 22. At that

resetting the counters 1 and 2, and also writing the first values to the accumulating counters of group 16. At the outputs of the counters 1 and 2, addresses are generated for reading the counts xi.j from block 9, and at the outputs of blocks 6 and 7

additions are generated by addresses for reading the xi-mj-n counts from block 10. In this case, if the value Qn) becomes negative, then the output signal of the sign bit of the addition block 7 causes the counter to be zeroed out counter 1, if the value (fm) becomes negative, then both counters are reset and a signal of the end of calculations is generated.

8, the result of the formation of read addresses at the output of block 9 is the value of xij, and at the output of block 10, xi-m, j-n. When generating the signal of the end of the calculation, the calculation process ends and

the outputs 17 read the histogram values. The calculation of the first-order histogram values is performed (set 1 at input 19) with m 0, n 0.

Claims (1)

Claims An apparatus for generating histograms comprising a first address counter, a first group of elements AND, a group output counters, the counting inputs of which are connected to the outputs of the corresponding elements AND of the first group, characterized in that, in order to expand the class of solved, it is specified by forming two-dimensional histograms, it additionally contains a second address counter, two addition blocks, two memory blocks, the second group elements AND, three elements NOT, three elements OR, element AND, the first input of the first element AND of the second group is connected to the start input of the device, and the output of the first element AND of the second group is connected to the first input of the first e element OR vt to the enable inputs of the parallel recording of the initial state of the output group counters, the second input of the first element OR is connected to the output of the sign bit of the first addition unit, the first input of the second OR element and the zero input of the first address counter are connected to the output of the first OR element, the second input of the second OR element and the first input of the third OR element with the output of the sign bit of the second addition unit, the outputs of the third and second elements OR are connected, respectively, to the counting input of the first address counter and the zero input of the second address counter, the count input second The second address counter is a clock input of the device, the overflow output of the second address counter is connected to the second input of the third OR element. the outputs of zeroing the first and second address counters are connected respectively to the first and second inputs of the AND element, the output of which is the output of the end of the device calculations, the first inputs of the first and second addition blocks are connected, respectively, with the first and second address inputs of the first block the memory and information outputs of the first and second address counters, respectively; the second inputs of the first and second addition blocks are respectively the inputs for setting the abscissa of the image displacement and the ordinate displacements image read enable input of the first and second memory blocks are connected to the output of the second AND gate second group yn the formation inputs of the first and second memory blocks are connected to the information input of the device, the first and second address inputs of the memory block are connected respectively to the information outputs of the first and second addition blocks, the write enable inputs of the first and second memory blocks are connected to the output of the third element II of the second group , the first input of the second element AND the second group is connected to the input of the first element NOT and is the input of the device mode setting, the output of the first element is NOT connected to the first input of the third element And the second group, the first inputs of the first and second members of the first group and connected to the output of the second NOT member. whose input is connected to the first inputs of the third and fourth elements AND of the first group and the information outputs of the second memory block, the second inputs of the second and fourth elements AND of the first group are connected to the output of the third element NOT. the input of which is connected to the second inputs of the first and third elements AND of the first group and information output of the first memory block, the counting input of each output counter of the group is connected to the input of setting the initial state of the same output counter, the information outputs of the output counters of the group form a group of information outputs of the device, the second the inputs of the elements of the second group are connected to the synchronization input devices. 22 23 27 20