SU1633422A1 - Device for solving systems of linear algebraic equations - Google Patents

Abstract

The invention relates to computing and can be used in specialized computers and signal processing devices for solving systems of linear equations. The purpose of the invention is to reduce hardware costs. The goal is achieved by the fact that the device contains n operational blocks 5, where n is the order of the system of linear algebraic equations, register 6 and block 7 of analysis. 1 hp f-ly, 3 ill.

Description

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The invention relates to the field of computing and can be used in high-performance specialized computers and digital signal processing devices.

The purpose of the invention is to reduce hardware costs.

FIG. I is a diagram of the device, FIG. 2 is a diagram of an operation unit, FIG. 3 is a diagram of an analysis unit.

A device for solving systems of linear algebraic equations contains inputs of the I coefficients of a system of linear algebraic equations of a device, an input of 2 free members of a system of linear algebraic equations of a device, an input 3 values of a device's resolution accuracy, an input 4 of device synchronization, n operational blocks 5, register 6, analysis block 7 exits

8 results of device solutions and outputs

9signs of device termination

Each operational unit 5 contains the first information input 10, the second information input 11, the third information input 12, the clock input 13, the first to the third registers 14-16, the multiplier 17, the adder 18, the first output 19, the second output 20

The analysis unit 7 contains the first information input 21, the second information input 22, clock input 23, registers 24 of the first group, registers 25 of the second group, readers 26, comparison nodes 27, first and second elements 28 and 29, trigger 30, group of outputs 31 and exit 32

The device is based on the Zadel method of finding the roots of x, a system of linear equations of the form (Е А) (Е -L unit matrix) by the formula ,, i 1, п

L-1. K, L. (A. f)

x Ha „x LЈaih, -r-b„, 2,

/ /

In the above formula, the values of are determined by the recurrence relations

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 Bn, n, k 1,2,3,

/ h, «l / -fl | a i-.fix, -2i J i ,, 2,

(a, „. x,.,;% ,, j 1,1-1, k 1,2,

  Np, k 1,2,3,

When describing the operation of the device in the designation x1, - /, the first index in brackets (k) indicates the iteration number, and the second index in brackets (j) indicates the number of the recurrent step for k and iteration

Operational unit 5 performs a multiply-accumulate operation, those for information inputs 10-12 are respectively supplied values a, c and b, which are written respectively to registers 14-16 and the output c -) ab is formed at the output of adder 18, which is fed on exit 19

The analysis block 7 is designed to determine the accuracy of calculating the values of x, (il, n) and output them to the outputs 31j of block 7 The accuracy of the calculation is determined by the value of F continuously supplied to input 22 When the required accuracy of calculation is fulfilled, output 32 the signal of the end of the calculation and from the outputs 31, all values are read out. The values can be output sequentially to the output 311

0 of the block 7. The accuracy of the calculation is determined as follows. Values are fed from the output of the register 6 to the input 21 of the block 7 through a clock. Therefore, in order to reduce the number of registers 24 and 25 of the block 7, clock pulses to the write inputs of the registers 24 and 25 served through the clock (such as in-clock is provided by the counting mode of operation of the trigger 30, which opens the AND 29 element through the clock to pass the clock pulses to the write inputs

0 read registers 24 and 25) The recorded values are register 25, and the values in register 24 are fed to subtractors 26, where the difference x, x, -xf Ha is determined, the inputs of node 27, compare to give the difference x, and the value t, specifying

5 calculation accuracy x If / 4X, / "Ct, then the output of node 27, the comparison will have a single signal. If there are single signals at the output of all nodes 27 of the comparison, the output signal of the element 28 will generate a signal that is suppressed by the sign of the end of the calculation

Claims (2)

Formula invention 1 A device for solving system of linear algebraic equations, containing n operational blocks, where the order of the system of linear algebraic equations, an analysis block and a register, with r and vnsn coefficients of the system of linear algebraic equations of the device (,, p) connect to the first information input of the 1st operational block, the second information input of the kth operational block (where k 1,, p - 1) is connected to the first output (k + I HO of the operating unit. The second information input of the nth operational block is connected to the input of the coefficients of the linear algebraic equations system of the device, the synchronization input of which is connected to the clock inputs of all the operational blocks, the analysis block and the register write-read input, information the input is connected to the first output of the first operational block, the output of the register is connected to the third information the first input of the first operating unit, the second output of the k-ro operating unit is connected to the third information input (k-j-1) of the first operating unit, characterized in that, in order to reduce hardware costs, the register output is connected to the first information input of the analysis unit, the input value of the decision accuracy of the device is connected to the second information input of the analysis unit, the outputs from the first to the nth group and the output of which are connected respectively to the output results of the decision of the device devices. 2. The device according to claim 1, wherein the analysis unit comprises a first group of n registers, a second group of n registers, n subtractors, n comparison nodes, a trigger and two AND elements, with the first information input of the block connected to the information input of the first the register of the first group, the output of the k-ro register of the first group (where k 1, ..., p-) is connected to the k-th output of the group of the block, to the information input (k + l) -ro of the register of the first group and to the first information input k-ro subtractor, the output of the n-th register of the first group is connected to the n-th output of the unit analysis a the information input of the first register of the second group and to the first information input of the nth subtractor, the output of the k-ro register of the second group is connected to the information input of the (k +) -th register of the second group and to the second information input of the k-ro subtractor, output of the n-th register the second group is connected to the second information input of the nth subtractor, the second information input of the block is connected to the first information inputs of the comparison nodes from the first to the fifth, the second information inputs of which are connected respectively to the outputs of the subtractors from the first to the fifth, the outputs of the comparison nodes are connected respectively to the inputs of the first element I, the output of which is connected to the output of the block, the clock input of which is connected to the first input of the second element And to the counting input of the trigger, the output of which is connected to the second input of the second element And the output 0 which is connected to the write-read inputs of the registers of the first and second groups. five FIG. 2 Fig.Z