SU1649614A1 - Self-monitoring memory unit - Google Patents

Abstract

The invention relates to computing and can be used in memory devices of electronic computers. The purpose of the invention is to increase the reliability of the device. The device contains a 1cm memory block with accumulators 2, address register 3, input 4 and output 5 number registers, three registers 6, 7, 8, two control units 9, 10, a coding block 11, a decoding block 12, a correction block 13 and a multiplexer 14. The reliability of the device is increased by providing control of the address and modulo 3 input number, correcting a single error and fixing multiple errors for each of the memories of the memory block, as well as by the possibility of checking the device blocks. 1 il.

Description

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The invention relates to computing and can be used in memory devices of electronic computers.

The aim of the invention is to increase the reliability of the device.

The drawing shows the functional diagram of the device.

The self-monitoring memory device contains a memory block 1cm by storage devices 2, address register 3, input register of number 4, output register of number 5, status register including the first register 6, second register 7, third register 8, first control unit 9, second the control unit 10, the coding unit 11, the decoding unit 12, the correction unit 13 and the multiplexer 14. The memory unit 1 contains m drives 2. The number of bits of each drive is determined by the required number of bits of the Hamming code used.

The device operates in three modes: write, read information and monitor the health of the device blocks. Before the start of each mode, all the blocks and nodes of the self-monitoring memory device are reset to the initial state by the Installation signal.

In the information recording mode, the address code 3 is sent to the address register, which is transmitted to the second control unit 10, where it is monitored modulo 3 if there is no control lock signal. The control is made by comparing the check bits that come along with the address code with the code generated by the second control unit 10. In case these codes do not match, an address error signal is output to the first register 6. Code number with input

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register number 4 is monitored by the first control unit 9. Information on the presence of a fault is transmitted to another bit of the first register 6, simultaneously the code number is fed to the coding block 11, where the check bits of the Hamming code are formed, and the received code of the number is recorded together with the formed bits of the Hamming code and the control bits of modulo 3. The test bits of the Hamming code are fixed in the third register 8, from where they are copied to the second register 7 to the part that is For the bits of this accumulator 2 of memory 1, information is also transmitted from the first register 6 to the second register 7. By reading the status word, the memory information from the second register is transmitted through multiplexer 14 to the information outputs of the device for control by the processor or a computing device.

In read mode, the address code is monitored modulo the write mode. The read number from memory 1 goes to output register 5, and the bits of the Hamming code are decoded using decoding unit 12. If a single error occurs in the correction block 13, it is corrected. In the decoding unit, in addition, signals are generated Correctable error or Uncorrected error for each of the drives 2 memory blocks 1. which are transmitted to the corresponding bits of the first register 6.

After that, the corrected number is transmitted via the multiplexer 14 by the signal. The reading of the corrected number is transmitted to the information outputs of the device. The code of the number directly from the output register 5 by the signal. The reading of the uncorrectable number goes through multiplexer 14 to the information outputs of the device.

In the control mode, the blocks and nodes of the memory device control the operation of the control units 9 and 10, the coding unit 11, the decoding unit 12 and the correction unit 13. The control of the control units is performed according to the correctness of the generated fault signals recorded in the first register B. The control of the operation of the coding block is carried out by transmitting in the status word from the third register 8 through the second register 7 check bits of the Hamming code. The control of the decoding block 12 and the correction block 13 is carried out by transmitting the corrected and uncorrectable numbers

through the multiplexer 14 directly from the output register 5 and the correction block 13. When monitoring the performance of the drives 2 of the memory block, latching is possible

errors in each of m drives 2, since the check bits for each drive 2 are written separately to the second register 7, and information about correctable and uncorrectable errors is given in

The first fault register 6 is also separately for each accumulator 2.

Claims (1)

The invention includes a self-monitoring storage device containing a memory block, an address register, input and output number registers, a coding block, a decoding block and a correction block, the inputs of the first group of which are connected to the outputs of the decoding block, whose inputs are connected to the outputs of data and control bits the output register of the number, the inputs of the second group of the correction block are connected to the outputs of the information bits of the output register of the number, the inputs of the information and control bits of which are connected to The corresponding outputs of the memory block, the information and check bits inputs of which are connected respectively to the outputs of the input number register and the outputs of the coding block whose inputs are connected to the outputs of the input number register whose inputs are information inputs of the device, the address inputs of the memory block are connected to the information outputs of the address register, whose inputs are the address inputs of the device, due to the fact that increasing the reliability of the device, the first and second control units are entered into it, the status register, the multiplexer, the outputs of which are information outputs and devices, the information and control bits of the input number register are connected to the corresponding inputs of the first control unit whose output is connected to the input state register control, inputs the control bits of the code of which are connected to the outputs of the coding block, the outputs of the information and control bits of the address register are connected to the corresponding inputs of the second block control, the output of which is connected to the input of the control of the address of the register of the state, the outputs of which are connected to the information inputs of the first group of the multiplexer, the information inputs of the second group of which are connected to outputs of information bits of the output register of the number, information inputs of the third group of the multiplexer are connected to the outputs of the correction unit, the control outputs of the decoding unit are connected to the corresponding inputs of the control bits of the number by code, the inputs of the state register, the inputs of the control bits modulo three with the corresponding outputs of the memory block, The control inputs of the first and second control units are combined and are the control lock input of the device; neither