SU1472908A1 - Pulse distributor checkout unit - Google Patents

Abstract

The invention relates to the field of digital computing and automation and can be used in digital systems with increased reliability of operation. A distinctive feature of the device is that it allows to control the sequence of input and removal of signals at the inputs of the device and generates an error signal at the output of the device when the order of arrival and removal of signals at the output of the controlled pulse distributor is violated. The aim of the invention is to enhance the functionality by controlling the pulse duration of the ring distributor. The goal is achieved by introducing a second group of AND elements, a group of delay elements and a group of NOT elements. 3 il.

Description

The invention relates to digital computing and automation and can be used in digital systems with increased reliability of operation.

The aim of the invention is to enhance the functionality by controlling the pulse duration of the ring distributor.

FIG. 1 shows a functional diagram of the device; in fig. 2 and 3 - time diagrams of his work.

The device contains triggers 1.1-1.n, the first group of elements And 2.1-2.n, the second group of elements And 3.1-3. (p-1), the group of elements 4 .1-4. (n-1) delays, a group of elements NOT 5.1-5. (n-1), elements OR 6, inputs 7.1-7, and output 8 of the device.

The device works as follows.

In the initial state, the triggers 1 .2-1. P are set to one, and the trigger 1.1 is set to the zero state. The setting circuits of the flip-flops 1.1-1. And reset to FIG. 1 conventionally not shown.

With the correct receipt and removal of the input sequences, the device operates as follows. The impulse arriving at the input 7.1 of the device, the output of the element 2.1 of the first group of elements And does not pass, since the trigger 1.1 is in the zero state. With its leading edge, it resets the trigger 1.2, and the rear sets the trigger 1.1 to one. Elements 4.1 Delay

3

ki and NOT 5.1 form a signal at the inputs of an AND 3.1 element of the second group, which does not pass to its output, since the n-flip-flop 1, n is in the enich state.

On the leading edge of the pulse at the input 7.2 of the device, the trigger 1.3 is set to zero, and on the trailing edge, the trigger 1.2 is set to one. The error signal on the second element 2.2 of the first group is not generated, since in the presence of an impulse at the input 7.2 of the device, the trigger 1 .2 is in the zero state. On the leading edge of the pulse at the input 7.3 of the device, the trigger 1.4 is set to zero, and on the trailing edge, the trigger 1.3 is set to one. The formation of an error signal at the output of the AND 2.3 of the first group does not occur, since when a pulse arrives at the input 7.3 of the device, the trigger 1.3 is in the zero state. The error signal at the output of element And 3.2 of the second group is also not generated since after the end of the pulse at the input 7.3 of the device, when there are signals at the first and second inputs of this element, coming from the second delay element 4.2 and the second element NOT 5.2, respectively, at its third input there is a zero signal due to the fact that trigger 1.2 is already set to one.

Similarly, the device operates with sequential receipt and removal of pulses on the fourth, fifth, ..., (n-1) -th input of the device.

When a pulse arrives at the input 7.d of the device, a trigger 1 .1 is reset on its leading edge, and on a falling front, the trigger I.n is set to one. Error signals at the outputs of the elements of And 2.p and 3. (p-1) of the first and second groups are not formed for reasons similar to the above,

Consider the operation of the device in violation of the sequence of the postulation and removal of input signals, for example, with the number of inputs of the device n - 4.

Figure 2 shows the timing diagram of the device when the pulse arriving at

0

five

0

five

0

five

0

Input 7.2 of the device, in case of violation of the sequence of signal removal at the input 7.4 of the device and in the presence of a false pulse at the input 7.2 of the device.

When the pulse at the input 7.2 of the device disappears, the trigger 1.3 does not return to the initial state. As a result, the element And 2.3 of the first group remains open and the next pulse at the input 7.3 of the device generates an error signal at its output. In addition, the trigger 1.2 remains in the initial state by the moment the pulse ends at the device input 7.3 and at the output of the element 3.2 of the second group of elements. An error signal is also generated, the duration of which is determined by the delay time Ј of the delay elements 4.1-4. (N-1) . At the output of the element OR 6, a total error signal is generated, which is fed to the output 8 of the device.

If the sequence of the signal removal at input 7.4 of the device is disturbed, the trigger 1 .4 until the signal arrives at the input 7.1 of the device remains in the initial state, and at the output of the AND 3.1 element of the second group, an error signal of duration 2-j appears. which then through the element OR 6 enters the output of the device.

When a spurious pulse arrives at the device input 7.2, the trigger 1 .2 is in the one state and allows the output of the AND 2.2 element of the first group to pass through the element OR 6 to the output 8 of the device.

The device provides pulse sequence control if

they overlap in time.

FIG. Figure 3 shows the time diagrams of the device operation during the control of partially overlapping in time input sequences in the case of loss of a pulse at the device input 7.3 and in case of a violation of the signal removal sequence at the device input 7.2.

The operation of the device in the control of such sequences is similar to that described. The difference is that with a deep overlap of the pulses, when the pulse at the input 7.p starts before the end of the pulse

at input 7.1 during normal operation of the device (no errors in

controlled sequences x), trigger I .1 does not fire. Failure of the trigger 1 .1 causes the impossibility of controlling its triggering at the end of the pulse at the input 7.2 of the device. However, this is not a drawback of the device, since monitoring the end of the pulse at input 7.1 of the device before the end of the pulse at input 7.2 is ensured by the fact that trigger 1.2 is not set to one due to the presence of a signal from input 7.1 at its R input. In this case, the fact of an error is established at the end of the pulse at the input 7.3, since the trigger 1.2 remains in the initial state.

Claims (1)

Formula of gain A device for controlling the pulse distributor, containing n triggers (where n is the number of outputs of the controlled distributor), the first group of n elements AND, the OR element, and the inputs of the device for connecting to the outputs of the controlled distributor from first to. (p-1) -th are connected to the J- and C-inputs of the respective triggers, with the first inputs of the corresponding elements AND of the first group and the R-inputs of the subsequent triggers from the second to the nth, nth input of the device for connecting n th output of the controlled distributor is connected to the J- and C- inputs of the n-th trigger, the first input of the n-th element AND of the first group and the R-input of the first trigger. K-inputs of triggers from the first to the n-th are connected to the bus of zero potential set729086 Arrangements, direct outputs of the flip-flops are connected to the second inputs of the corresponding AND elements of the first group, the t-outputs of which are connected to the inputs of the OR element, the output of which is a device output output, characterized in that, in order to expand the functional capabilities by ensuring control of the duration pulses of the ring distributor, the second group of elements is entered into it from the first to (p-1), the group of delay elements from the first to (p-1), and the group of elements from the first to (p-1) , with the input of the first element of the delay and the group is connected to the first input of the device and the second input of the first element AND of the second group, the output of the first delay element - to the input of the first NOT element of the group, the output of which is connected to the first input of the first element AND of the second group, the input of the delay elements from the second through ( -1) -groups are connected to the inputs of the corresponding elements NOT from the second to (n-1) -and groups and to the inputs of the device from the third to the n-and corresponding 30, the outputs of the delay elements from the second through (p-1) -and group, respectively, with the first inputs of the corresponding elements AND from the second through (p-1) -and the second group, the second inputs 35 of which are connected to the outputs of the corresponding elements of the NOT group, the third inputs of the elements of the second group are with the inverse outputs of the flip-flops from the second to (n-1) -and, respectively, 40 inverse output of the n-th trigger with the third input of the first element And the second group, the outputs of the elements And from the first to (n-1) -and the second group - with the inputs of the element OR. V V V to V