SU1381695A1 - Single-pulse former - Google Patents

Description

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The invention relates to a pulse technique and can be used in devices for converting, processing and transmitting pulse information.

The purpose of the invention is to increase the speed of twi while maintaining the guaranteed minimum duration of the output pulse.

The drawing shows an electrical functional diagram of the device.

The single pulse generator contains the first trigger 1, the first S- input of which is connected to the output of the first element AND-NOT 2, the first input of which is connected to the output of the element NO 3 and to the first input of the first element AND block 3-ZI-2IPI-II 4, the second the input of which is connected to the direct output of the second trigger 5, the third input with the D input of the third trigger 6, the direct output of the first trigger 1 and the output bus 7, the second input of the second element AND of the 3-ЗИ-2ИЛИ- НЕ 4 is connected to the first input of the second element I-YA 8, with the input of the element NO 3 and with the bus 9 clock pulses owls, the third input of the second element AND block 3-ZI-2ILI-NOT 4 is connected with the inverse output of the second trigger 5, with the second S-input of the first trigger 1 and with the second input of the first element AND-HE 2, the third input of which is connected to the second input The second element IS-HE 8, with the R-inputs of the first and second triggers 1.5 and with the inverse output of the third trigger 6, the output of the second element AND-HE 8 is connected to the S-input of the second trigger 5, the output of the 3-ЗИ-2ILL- unit NOT 4 is connected to the C-input of the third trigger 6, the R-input of which is connected to the input bus 10, with the fourth input of the first element AND – N E 2 and with the third input of the second element AND-HE 8, the fourth input of which is connected to the inverse output of the first trigger 1.

The device works as follows.

In the initial state, bus 10 is low and triggers 1,5,6 are in the zero state, and bus 7 is low.

If a high level on bus 10 enters during a low level on bus 9, then a low level is formed at the output of element 2.

0

which sets trigger 1 to one state, i.e. the leading edge of the output pulse is formed. When the next cutoff of the clock pulse arrives at the output of block 4, the pulse front is formed, which is fed to the C input of the trigger 6. The trigger 6 is set to

Q is a single state; at its "inverse output, a low level appears, which resets trigger 1, forming a slice of the output pulse.

If a high level on bus 10 follows a high level during operation of a high level on bus 9, the device operates in the same way, and the front of the output impulse is formed by sequentially switching triggers 5 and 1.

Thus, the front of the output pulse coincides with the front of the pulse on the input bus, and the duration of the output pulse is not more than a period,

5 but not less than half a cycle of clock pulses.

Claims (1)

Invention Formula 0 Single pulse shaper, containing the first trigger, the first S-input of which is connected to the output of the first NAND element, the first input of which is NOT connected through the element 5 with the first input of the second NAND element and the clock pulse bus, the second and third triggers, the input and output bus, characterized in that, in order to increase the speed of the operation, a 3-ZI-II-NI unit is inserted into it input of the first element And which is connected to the output of the element NOT, the second input - with the direct output of the second trigger, the third input 5 with the D-input of the third trigger, the C-input of which is connected to the output of the 3-ZI-2ShSh-NOT unit, with the my output of the first trigger, with the output bus and with the first input of the second element And the block 3-ЗИ-2ШШ-НЕ, the second input to The third input is connected to the second S input of the first trigger, the second input of the first NAND element and the inverse output of the second trigger, the S input of which is connected to the output of the second element NAND, R input - with the R input of the first trigger, with the third input of the first NAND element, with the second input 31381695 the second element I-PE and with the inverse AND-NOT and the third input of the second element, the output of the third trigger, the R input and the IS-NOT, the fourth input of which is connected to the input bus, is united with the inverse of the first one the fourth entry is the first element of the trigger.