SU1291977A1 - Device for calculating values of simple functions in modular number system - Google Patents

Abstract

The invention relates to computing and is focused on the use of high-speed specialized digital signal processing systems for calculating various elementary functions (trigonometric, logarithmic, exponential type, and others) from the arguments presented in the modular number system. The purpose of the invention is to increase speed. The goal is achieved by the fact that a device containing a shift register, a memory block for storing constants, a counter, a register of constants, a multiplication unit, a cumulative register, an addition block, three buffer registers, and a control constant memory block , a control register and three groups of multiplexers with corresponding connections. 1 ill., 2 tab. (O (L to with so

Description

The invention relates to computing and is focused on the use of high-speed specialized digital signal processing systems for calculating various elementary functions (trigonometric, logarithmic exponential type and others) from arguments varying in the f-1,1 interval and presented in a modular number system.

The purpose of the invention is to increase speed.

The drawing shows a diagram of an apparatus for calculating elementary functions in a modular number system.

A device for calculating elementary functions in a modular numbering system contains a clock input 1 of the device, input 2 of the code for setting the function of the device, installation input 3 for the device, input 4 for the device constant, input 5 for the argument

devices, shift register 6, memory block 7 for storing constants first and second buffer registers 8 and 9, counter 10, register constants 11, first and second groups of multiplexers 12 and 13, constant memory unit 14, third group of multiplexers 15, a multiplication unit 16, a third buffer register 17, a control register 18, a cumulative register lr 19, an addition unit 20, a constant division unit 21, and a device output 22.

The shift register 6 is 2 Hlog N bits, where N is the number of functions computed by the device, x is the smallest integer not less than x. Register 6 performs a cyclic shift of the content by Jlog N bits, thereby swapping the contents of the lower and higher bits. The counting module of the counter 10 is thirty-two.

The memory unit 7 for storing constants has a capacity of 2

to.

word bit

ha ,, t,, ..., t - base modularly

number systems, k is the number of bases, with m, 2p + k-2 (p is a fixed natural number),. , In the memory block 7 with addresses

8-n, 8-n + 1, ..., 8n + 7 write modular codes of constants related to the nth of the functions calculated by the device (n CJO, 1, ..., N-1J). The rule for forming the content of block 7 is given in Table 1.

Table 1

In table 1 through And.

f, n

with numerator fraction a.

denotes A,.,. M is the approximation of the i-ro 5 coefficient of a truncated power series approximating the nth function

40

f, (x) - tl

i; 0

 , aj,, lfi

A ;, 6 D {-pM, -pM, + 1, ..., PM., - 1 /, (1)

K-i

45 where M I m 1.

to - L. J t -J

M is a natural number that determines the accuracy of the calculation and is chosen from the conditions

 p -M, a make

K-1 max.

/BUT.

1.and

55

Control block 14 has leMKocTb eight-word words and is used to form sets of control signal values in accordance with Table 2. B, b,. ..,

About About About 1

About About About 1 About

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4 o o o

ABOUT

ABOUT

ABOUT

ABOUT

one

one

one

one

one

one

ABOUT

one

oh oh

The width of the registers is 8,9,11,17 and 19 and the number of multiplexers in groups 12,13 and 15 is

to

d log m bit eleven

Blocks 16,20 multiply and add implement the corresponding operations on integers from the range of the modular number system. Block 21 divides the input number A, given by the modular code, by the constant M.

The calculation of the elementary functions is based on the approximation of functions by series of the form (1), not necessarily Taylor functions. In particular, power series can be used that are obtained from expansions of functions in orthogonal bases of Legendre, Chebyshev, Hermite, and others.

table 2

3

about 1 about

2

1 o

2 o 2 o

1 o

about

1 1 1 1 о о о 1

about 1

oh oh oh

about

about

about

about

about

about

about

one

about

about

one

one

about

about

one

about 1

about 1 1 about

0

about 1

oh oh oh

(1) the following calculation relationships are derived for calculating the value

at

f of functions f (x) with X -.

f. lf- РЬ, + в, .г,) 2)

C, Bo, n-B, .USHZ) V. M A,, + A ,, „X. (four) ,. , b. X) D; (five)

whose

 .A - A, „. X): (6)

X2

Y2

,

(7)

For the most common functions, including trigonometric

five

(direct and inverse), logarithmic, exponential type and others, approximation by the first six members of the power bits of the considered type gives the absolute error from 10 to 10

The device works as follows.

The signal supplied to the setup input 3 of the device, the shift register 6 is zeroed out, and the binary code of the number 31 is recorded in the counter 10, then from the block 14 of the permanent control memory at address 31 coming from the zero, first, third and fourth outputs bits of the counter 10 to the address input of the block 14, is read the initial set of control signals b, ..., b (Table 2), which from the output of the block 14 of the permanent memory is transmitted to the control register 18. On each operation cycle of the device control signals generated in register 18 s on the seventh exe outputs, respectively, are fed to the shift control register shift input 6, the control input for issuing the register code 17, the control input for receiving the register code 9, the control inputs for the multiplexer groups 12, 13 and 15 and the zero input for the accumulative register 19, and depending on the values of the control signals, actions are taken to ensure that the inputs of the block 16 multiply the required operands in the current clock cycle and form the content registers 6,8,9,17 and 19 for the next clock cycle. The multiplication unit 16 performs the modular multiplication operation of the operands arriving at the first and second inputs, respectively, from the outputs of the multiplexer groups 12 and 13, the modular product code output from the block 16 is transmitted to register 8 The adding unit 20 summarizes the modular codes generated at the outputs of the registers 8 and 19 and the modular sum code from the output of block 20 is fed to the information input of the group of multiplexers 15 and the input register of block 21. At the same time, the contents of the ith group of bits with nanometers of 0.1.3 counter 10 are fed to the address inputs of the block and 7 memory and block 14, to the address inputs of which are also served respectively soda

five

0

five

the shift n of the group of lower bits of the shift register 6 and the contents of the higher bit of the counter. From memory block 7 at the address read

The modular code of the next constant in register 11 is also fed to the first information input of the group of multiplexers 15. From block 14 to register 18, a set of control signal values is read for the next clock cycle. At the same time, the signal supplied from the clock input 1 of the device to the counting input of counter 10 increases its content by one, with the result that the address of the next control word is formed at the outputs of counter 10.

At the preliminary (zero) operation cycle of the device, the control input of the reception of the register code 9 is given a signal, and since at the moment the control input for issuing the register code 17 has a single signal, then the register 9 through the input 5 of the device argument receives the modular numerator code X value

five

0

0

the function argument f (x),

four

subject5

five

Xj

m

In this case, the binary code of the function number r is entered into the lower bits of the shift register through input 2 of the function code of the device. At the same time, the control word with zero address is read into register 18 from block 14 (Table 2). 10, the address of the next control word is obtained.

During the first clock cycle, the control inputs of the groups of multiplexers 12 and 13 are given signals (Table 2), as a result of which the outputs of the groups of multiplexers 12 and 13 pass through the values arriving respectively at their information inputs from the output of the buffer register 9. The multiplication unit 16 finds the module The code of the number X, which is stored in the buffer register B. At this time, the modular constant code is read into register 11 from memory block 7 at (8-g + 1), accumulative register 19 is zeroed out. The control register 18 of block 14 receives the control word for the second clock cycle, and the contents of counter 10 are incremented. Addition and division blocks 20

Standant 21 is not doing useful work at this time.

At the second cycle, the outputs of the multiplexer groups 12 and 13 will go through the contents of register 11, register 9, multiplication unit 16 will receive a modular code of value A. , j, X, which is stored in register 8. The previous contents of register 8 in block 20 are added to the contents of the (currently zero) register 19, the modular code of X from the output of block 20 is transmitted to block 21. Also with the indicated actions On the second cycle, from block 7 of memory at the address (8 G + 2) is read the modular code of the value M-A, which through the information input of the group of multiplexers 15 enters register 19.

In the third cycle, block 20, adding the contents of registers B and 19, finds the value + A p X entering the input register of block 21 The first and second inputs of multiplication unit 16 from the outputs of the multiplexer groups 12 and 13 receive, respectively, the values M and X supplied to the information input of the multiplex group of the multiplexer group 15 transmits 12 through the device constants input 4 and the information input of the multiplexer group 13 from the register output 19, multiplication unit 16 finds the modular code of the value M-X stored in register 8. From block 7

35

the memory receives the constant A 3, d in the control register 18 a control word is formed with the address 3, and the register 19 is zeroed out.

In the fourth cycle, the addition unit 20 generates the value M X ,, transmitted to the unit 21, the multiplication unit 16 receives the modular code of the number

40

45

c to register 19, from block 14 to register 18 a control word with address 4 is received, and at the first output of counter 10, after increasing its content by one, the code of number 5 is formed. Since the operation in block 21 takes six cycles, starting from the eighth cycle, from the output of block 21 to the buffer register 17, the processed values of the input values of block 21 begin to arrive in the order of their arrival at the input. In particular, on the eighth cycle, the register 17 receives the modular code of the value Y in accordance with formula (7).

Z.G-su 8X, from block 7 of memory by the address of the constant is read М-А,

11 and

which is written to the register via the information input of the group of multiplexers 15 is passed to its output and written to register 19, and the control word with the address O is transferred to register 18 of block 14. In register 6, the contents of the groups of the lower and upper digits are exchanged this group of low-order bits through the input 2 of the function code of the device receives the binary code of the number S of the function f (x), the calculation

which is combined with the calculation of the function f (x), and in register 9, through input 5, the device argument takes-- with the modular code of the numerator X corresponding to

Ha

argument value -.

M

In the next four cycles of operation of the device (from the fifth to the eighth), for the function ff (x), the operations performed on the cycles from the first to the fourth for the function f | v (x) are repeated. As a result, on the cycles from the fifth to the eighth block 21, respectively, receives the values of M-A + A X ,, x, M-A, J + A,., - Xg, MH. The difference from the fourth clock cycle on the eighth clock after rearranging the contents of the lower and higher bits of the shift register 6 in places through the input 2 of the function code of the new information device does not arrive, respectively, the flow of new information stops and through the input of the 5 argument of the device. On the eighth clock cycle from memory block 7 at 8 S + 4, the constant M-A is read through the information input

gz

about a group of multiplexers 15 transmits

five

0

five

0

five

c to register 19, from block 14 to register 18 a control word with address 4 is received, and at the first output of counter 10, after increasing its contents by one, the number 5 code is generated. Since the operation in block 21 takes six cycles, then From the eighth cycle, from the output of block 21 to the buffer register 17, the processed values of the input values of block 21 begin to arrive in the order of their arrival at the input. In particular, on the eighth cycle, the register 17 receives the modular code of the value Y in accordance with formula (7).

On the ninth cycle, the modular code of the YI number from the T7 register is transferred to the register 9 and through the information input of the group of multiplexers 12 and through the information input of the group of multiplexers 13 enters the inputs of the multiplication unit 16, which finds the value Y ,, stored in register 8 , the previous contents of register 8 in block 20 are added to the contents of accumulative register 19 and the resulting sum X is transferred to block 21. In register 18

the control word with the address 5 is formed, the register 19 is zeroed out, and the modular code number enters the buffer register 9 from the output of block 21

AT

2, g

In accordance with the formula (6). 5 On the tenth cycle from the block output

The addition unit 20 receives the value Y, the multiplication unit 16 finds the product of the numbers M, B, supplied to the information input of the group of multiplexers 12 and the information input of the group of multiplexers 13, respectively. From memory block 7 at address 8g + 6, the constant A I is read, stored in register 11, the sixth control word is written to register 18, register 19 is zeroed, and the modular code of X is fed to buffer register 17 from the output of block 21.

On the eleventh cycle, block 21 receives the value M-B,, in register 8, a modular product code A, J. X, j, obtained by block 16, is formed, and the constant М- is read from memory block 7 at address (8 g + 7) And which, through the information input of the group of multiplexers 15, is transferred to the register 19, and the control word with the address 7 is written to the register 18. In this case, after increasing the content of the counter 10 by one, the binary code of the number 4 is formed at its first output.

In the twelfth cycle, the addition unit 20 determines the modular code of the GOD number in accordance with formula (4), which from the output of unit 20 through the information input of the group of multiplexers 15 enters the cumulative register 19. The first and second inputs of the multiplication unit 16 through the information input of group the multiplexers 12 and the information input of the group of multiplexers 18 from the outputs of the buffer registers 17 and 9 are given the values of B and Y, respectively, as a result of which their product is received in register 8. B register 17 receives the modular code of the number V in with tvetstvii of formula (7), in the shift register 6 is accomplished exchange group content of younger and older bits in the register 18 of the block 14 is read out from the control word location 4.

On the next four cycles, the actions performed on the cycles with

five

0

five

0

five

0

45

50

ninth to twelfth, are repeated, with the result that in block 21 post2

are the values of B f. + B Y | , Y, j, MB ij 5 3 after the expiration of the sixteenth cycle, the modular code of the number Z enters the buffer register 17 from the output of block 21, in accordance with formula (7). In addition, on the sixteenth clock cycle in register 18, a control word WRITTED with address 8 is generated.

On the seventeenth clock cycle, the adding unit 20 finishes the calculation of the BO + B value, 5 Y, j entering the block 21, the modular code of the Z number from the register 17 is sent to the register 9, and the B values are sent to the register 17. .

On the eighteenth tact block, 16 multiplies gets the product B,}, g Z | stored in register 8,

and register 19 is zeroed. )

During the nineteenth clock cycle, the accumulative register 19 is transferred by the addition unit 20 and the group of multiplexers 15 to the register 8. In this case, the value Cg is supplied to the register 17 from the output of the unit 21. According to formula (3).

On the twelfth cycle, the value of Cr is multiplied by the constant M, and on the twenty-first cycle, the resulting product by the addition unit 20 is summed with the contents of the cumulative register 19. B as a result, block 21 receives the value M-C + B. Z. After performing the above actions for the function f gCx), after the twenty fifth cycle has elapsed, block 21 receives the value of MS, + B, Z.

At the twenty-seventh and thirty-first steps, block 1 completes the formation of the values of fr and fj in accordance with formula (2). The modular codes of the quantities sought at the indicated clocks are removed from the output 22 of the device, and the process of calculating the functions at the given points ends.

Starting from the twenty fifth measure, in the proposed device, you can start calculating a new pair of values of the same or two different functions.

55

Claims (1)

Invention Formula Device for calculating elementary functions in a modular system a number containing a shift register, a memory block for storing constants, a counter, a register of constants, a multiplication unit, a cumulative register, an addition block, three buffer registers and a constant control memory block, the input of the function setting code of the device is connected to the inputs of the lower bits the shift register, the zero input of which is connected to the installation input of the counter and is the installation input of the device, the output of the memory block for storing constants is connected to the information input of the register of constants, the output of the block is more It is connected to the information input of the first buffer register, the output of the filling register is connected to the input of the first addend unit, the input argument of the device is connected to the installation input of the second buffer register, characterized in that it contains a division unit by a constant a control register and three multiplexer groups, the clock input of the device connected to the counter input of the counter, the bit output of which is connected to the address input of the control unit of the permanent memory The output of which is connected to the information input of the control register, the first to the seventh outputs of which are connected respectively to the shift shift register control input, the third buffer register code control input, the second buffer register code input input, five 0 five 0 five 0 the equal inputs of the multiplexers of the first, second, third groups and the zeroing input of the cumulative register, the information input of the third buffer register is connected to the output of the dividing unit by a constant whose output is the device output, the output of the constant register, the input of the device constant, the outputs of the third and second buffer registers are connected respectively to the information inputs of the first to fourth multiplexers of the first group, the outputs of KcfTopbix are connected to the input of the first multiplier of the multiplication unit, the input of the second question The consumer is connected to the outputs of multiplexers of the second group, the first and second information inputs of which are connected respectively to the outputs of the third and second buffer registers, the output of the third buffer register is connected to the information input of the second buffer register, the output of the first buffer register is connected to the input of the second addend block, output which is connected to the input of the division unit by a constant, the input of the storage unit for storing constants and the output of the addition unit are connected respectively to the first and second The third information groups of the third group multiplexers, the outputs of which are connected to the information input of the cumulative register, the upper and lower bits of the address input of the memory block for storing constants are connected respectively to the low end bits of the shift register and the low end bits of the counter.