SE517591C2 - Communication system - Google Patents

Abstract

FIELD: communication engineering. SUBSTANCE: device functions to implement high/low-speed mode of operation using low-speed voice code and high-speed channel code whose input is adapted to communication with low-speed voice code; bit relocation module is provided at input. EFFECT: improved design and reliability of control.

Description

20 25 30 35 517 591 "z" 2. improve the subjective quality of the received speech.

The types of operation include full speed numbers and half speed numbers. the encoder / decoder.

In these 3 kbit, the service type of the call is also transmitted.

This type of operation is transmitted to the channel The channel encoder / decoder then sends this operation information to the speech encoder / decoder.

The speech encoder / decoder leaves a frame with compressed speech bits, representing the original speech. which are grouped in terms of speech parameters which These parametrically ordered bits are rearranged by the channel encoder / decoder into a sensitivity order. A single bit error in any of the most sensitive bits will fully recreate it, resulting in bit errors in the least sensitive bits resulting in an inability of the original speech. On the other hand, decoded speech is perceived as only slightly, if at all, deteriorated.

The channel encoder / decoder is usually located in the base station (BTS station), pure can be found in the BTS, in the base station controller (BSC) (MSC). When the speech encoder / decoder is not present in the BTS station, the GSM receiver station, while the speech encoder / decoder or in the mobile station exchange, specifies the interface or protocol that must be used between the remote speech encoder / decoder and the channel encoder / decoder. Such an interface exists for full speed (GSM 08.60) and has begun to be planned for half speed (either GSM 08.60 or a new document).

The algorithms used in the full speed channel encoder / decoder and those recently proposed for the half speed speech encoder / decoder are completely different. Consequently, the parameters they generate and the restructuring from parametric order to sensitivity order are also different.

In both the full speed operation and the half speed operation, the channel encoder / decoder has 3 bit classes: 1a, 1b and 2, where 1a is the most sensitive and 2 is the least sensitive. Different types and degrees of channel coding are applied to each of these three classes.

At full speed, there are 50 bits of class 1a, 3 bits of cyclic redundancy check (CRC), 132 bits of class lb, 78 bits of class 2 and 4 end bits, which after coding form 456 bits. At half speed there are 22 3 CRC bits, 73 bits of class lb, 17 bits of class 2 and 6 end bits which after coding form 228 bits.

At both full and half speed, the 1A bits have one (CRC); the lb and CRC bits are convolutionally coded; and no extra protection is added to the class 2 bits. bits of class Ia, associated with cyclic redundancy check Ia-, At full speed is the primary use of CRC At half speed, this BFI is set not only by the CRC but also by (WED scheme), ficated as part of Motorola's half speed algorithm. to flag an incorrect frame (said BFI). a window error detection scheme as speci- The interface between the remote speech encoder / decoder for full has- (GSM 08.60). could use full speed and the channel encoder / decoder uses a 16 kbit GSM interface The equivalent half speed interface goes down to 8 kbit and has the advantage that it reduces the sing cost by half the cost of the serial the base station (channel encoder / decoder). Plans are being developed to formulate modes with both 8 kbit and 16 kbit for the half-speed interface between the remote speech encoder / decoder and the channel encoder / decoder.

Fig. 1 shows an uplink communication according to the prior art, where a full-speed channel operation is implemented by means of a full-speed speech encoder 14 and a full-speed channel encoder 20. Speech is delivered to an input 10 of an audio interface 12 in a mobile station 11. The speech is encoded in the mobile station's full-speed speech encoder / decoder 14. The encoded speech is provided to a channel 1 encoder / decoder processor 16. The processor 16 includes both a module llllll I Illlll 10 15 20 25 30 35 517 591 4 18 for reorganization from order according to a predefined standard parameter to order according to sensitivity as a full speed channel encoder / decoder 20. The output of the full speed speech encoder / decoder 14 is output to the module 18. The output of the module 18 is output to the full speed channel encoder / decoder 20 for further processing (RF-22 for transmitting representative signals). and then left to the radio frequency interface (24) over the ether.

The representative signals 24 are received at a base transceiver station 13 and processed by an RF interface 22 to be supplied to a channel encoder / decoder processor 17 which is similar to the channel encoder / decoder. the processor 16 in the mobile station ll.

The signals are output to the full speed channel encoder / decoder 21 for initial decoding and are then processed by a module 19 for restructuring from sensitivity order to parameter order. The output of the module 19 for restructuring from sensitivity order to parameter order is then output to a full speed speech encoder / decoder 15 for further decoding and output of speech 26 at a rate of 64 kbit / sec. The full speed speech encoder / decoder 15 is located in the BTS station for clarity. implemented using half-speed speech and In the same way, a half-speed operation can half-speed channel encoder / decoder.

It is desirable to be able to offer a combination of full-speed and half-speed service, whereby advantages in the form of the lower costs of half-speed service can be combined with the robustness and quality of the full-speed service.

Summary of the Invention In accordance with the present invention, there is provided a communication system having a combination of full speed and half speed service types and comprising a half speed speech encoder / decoder and a full speed channel encoder / decoder having a front provided. 5 35 517 591 šš 5 for communication with the half-speed speech encoder / decoder, the front comprising a bit imaging restructuring module.

In accordance with the present invention, there is described a method of providing a combined full speed and half speed operation in a communication system having a speech encoder / decoder and a channel encoder / decoder, comprising the step of providing a bit mapping restructuring. as a front for the channel encoder / decoder for communication with the speech encoder / decoder.

Brief description of the drawings Fig. 1 shows a block diagram of uplink communication with full-speed operation.

Fig. 2 shows a block diagram of a combination of full speed and half speed operation in accordance with the present invention.

Fig. 3 shows a block diagram of an uplink communication comprising the combination of full-speed operation and half-speed operation according to Fig. 2.

Fig. 4 shows a flow chart for speech coding / decoding in accordance with the present invention.

Fig. 5 shows a flow chart of a channel encoder in accordance with the invention.

Fig. 6 shows a flow chart for a channel decoder according to the invention.

Detailed Description of a Preferred Embodiment As shown in Fig. 2, a communication system may provide a combination of full speed and half speed service types including a half speed speech encoder / decoder 30 and a full speed channel encoder / decoder 32 having a front provided. for communication with the half-speed speech encoder / decoder 30, the front comprising a module 33 for bitmap restructuring.

In particular, an implementation of such a combined type of service can be described with reference to Fig. 3. Fig. 3 shows a block diagram of an uplink communication utilizing the full speed / half speed service according to the present invention.

Speech is provided to an input 10 of an audio interface 12 in a mobile station 11. The audio interface transmits the speech to a first half rate speech encoder / decoder 30 for generating encoded signals.

The coded signals are provided to a module 33 for restructuring from parameter to sensitivity order in a first hybrid channel processor 32 which restructures the bits of the coded signals in a manner which will be described in more detail below. The restructured bits are then left to a full speed channel encoder / decoder for further processing. The output signal from the full speed channel encoder / decoder 20 is transmitted through the air via the RF interfaces 22 to a second hybrid channel processor 31 located in a base transceiver station 13.

A full rate channel encoder / decoder 21 in the hybrid channel processor 31 decodes the transmitted signals 34 and leaves them to a module 35 for restructuring from sensitivity order to parameter order in the second hybrid channel processor 31 for restructuring the bits in the decoded signals. The restructured bits are then sent to a second half rate speech encoder / decoder 37 via a serial link 39 for further decoding and outputting speech at the rate of 64 kbit / sec at its output 26. The encoder / decoder 37 is spaced from the hybrid. The serial link 39 is needed if the second half-speed speech processor 31. In other words, the second half-speed encoder / decoder 37 need not be spaced from the hybrid channel processor 31.

Fig. 4 shows a flow chart of the work performed by the speech encoder / decoder 30, 37 according to the present invention. Since the speech encoders / decoders must be able to operate with full speed operation, half speed operation or full speed / half speed operation in accordance with the present invention, it is necessary to specify the desired mode and function of speech encoder / decoder. In Fig. 4, for example, the speech encoder / decoder determines which mode of operation is desired, which takes place in step 40, and if it is full speed then speech coding or speech decoding is implemented at full speed, step 44. speed is desired to implement the operation for normal half- which happens in About either half speed or full / half hash speed speech coding or decoding, in step 42.

However, for a channel encoder operation in the hybrid channel processor 20, a bit restructuring module 33 is applied and according to a preferred embodiment of the present invention, it operates in the manner described in Fig. 5.

The hybrid channel processor or encoder / decoder 32 determines which type of channel operation is desired in step 48. If it is full speed, full speed channel coding is implemented, in step 53. Similarly, the normal half speed channel coding operation, 51, is implemented in steps if it is half speed.

If, on the other hand, full / half-speed channel operation is specified, the bit restructuring module 33 in the hybrid channel processor 32 maps half-speed number parameters to sensitivity order, as defined in the standard half-speed algorithm, in step 50. The bit restructuring module 33 then takes all 22 class-la bits half speed and determines 3 bits of CRC using the standard half-speed method, in step 52, which results in 22 class Ia coded bits and 3 CRC bits. At the same time, in step 56, the bit restructuring module 33 then takes all 73 bits of class 1b and 17 bits of class 2, which are defined at half rate, and adds 70 zeros resulting in 160 channel coded bits of class lb.

The obtained 22 channel coded bits of class 1a and the 3 CRC bits and the 160 channel coded bits of class 1b are all processed separately in step 54, since 22 3 bits of CRC, 160 bits of class 1b and 4 end bits through a full speed convolutional encoder give bits. of class la, ICC-Û '10 15 20 25 30 35 517 591 8 IQOUIO 378 convolutionally coded bits. The convolutionally coded bits are added with class 2 channel coded bits (78 zeros) to form 456 bits. The 456 coded bits are sent to the rest of the full speed channel encoder, step 60.

A channel decoding operation in the hybrid channel processor in step 58. which includes interleaving, 21 requires the bit reorganization module 35 to perform the reverse work, in accordance with a preferred embodiment of the present invention described in Fig. 6.

The hybrid channel processor or encoder / decoder 31 determines which type of channel operation is desired, step 60. If it is full speed, normal full speed channel decoding is implemented, step 61. Similarly, normal half speed channel decoding is implemented, step 63, if it is half speed.

If, on the other hand, full / half speed is specified, normal resolution of the interleaving is performed at full speed, in step 62, which gives 456 coded bits. The 456 coded bits are processed in step 64 to eliminate the redundant channels (78 zeros), which The 378 convolutionally coded bits are processed in step 66 by normal Class 2 squeegee / decoder bits giving 378 convolutionally coded bits. (standard) full rate channel decoding, optionally including WED, and is divided into class 1a and 1b channel encoders / decoders bits.

The 22 bits of class Ia and the 3 CRC bits thus obtained are processed, as in step 68, by the standard procedure for CRC control at half speed, selectable with WED, which gives a BFI. The expected result with 22 class 1a bit coded bits is plotted on parameters as required for a standard type half-speed speech decoder. The other obtained 160 channel encoder / decoder bits as in step 70. class 1b are also plotted on parameters, as required for a standard half-speed decoder, as in step 70. The new operating type can be specified by adding a dimension to the flag sent to the channel decoder / decoder and which indicates the type of operation such as full speed, half speed or full / half speed. used: The figures can be easily extrapolated to a downlink communication.

In summary, the bit restructuring module can use a table to map bits. First, the table it uses to map the bits supplied from the speech coder is from parameter order to the half-speed table instead of the full-speed table. the bits are mapped again, in order of subjective sensitivity. Second, after the mapping of these bits, on the three full-speed channel coding / decoding classes. It is proposed that the number of Class Ia encoding / decoding bits be 22, the Class 1b channel encoding / decoding bits should be 160 and the Class 2 decoding / decoding bits should be 78 .

This is accomplished by re-mapping: all 22 class 1a encoding / decoding bits of class 1a to all 22 class 1 channel encoding / decoding bits of all 22 class 1 channel encoding / decoding bits; all 73 class 1b speech-encoding / decoding bits and all 17 class 2 encoding-decoding / decoding bits on 90 of the 160 class 1b channel-encoding / decoding bits; sets the remaining 160-90 = 70 channel encoding / decoding bits of class 1b to any known value, such as 0; and sets all 78 class 2 channel encoding / decoding bits to any known value, such as 0.

Thereby, all the speech bits will have protection provided by the channel encoder, since they are all mapped to either class la or class lb. 10 15 20 25 30 35 517 591 / O One reason for reducing the number of bits in class Ia is as follows. The said CRC shall only work on those pieces whose significance is so great that an error in any of them could mean that the ability to acceptably reconstruct the original number is lost. Having more (la) without the extra bits meeting the criterion for the CRC purpose could lead to Consequently, there is a need to make a constraint so that bits only bits in this class that a frame is unnecessarily miscoded. be included in class la if they are absolutely necessary. The negative (or availability of more) class lb bits to have as a result of this is the need to have more enough bits to send to a normal full speed management encoder. In the normal full speed scheme, the number of bits sent to the convolutional encoder is 189 (50 la, 3 CRC, 132 lb and 4 end). with the present invention, the number of bits in class 1a is 22, the number of CRC bits 3 and the number of end bits 4 so that the number of remaining bits in class 1b is 160 (899-22-3-4).

A third change for the channel coding / decoding accordingly could be to introduce WED in the channel decoding, as indicated for the half-rate channel coding / decoding described with reference to Fig. 6.

The full and half speed combination system and method of the present invention provides more robust half speed operation while it is possible to retain the benefits of 8 kbit partial rate multiplexing between a remote speech encoder / decoder and a channel. encoder / decoder. The present invention provides a service similar to full speed service but with the advantages of lower costs of the 8 k partial speed multiplexing between a remote speech encoder / decoder and a channel encoder / decoder.

The advantages of the present invention over full speed operation are as follows. The present invention provides full speed operation with the half speed leasing costs for the serial links between the remote encoder / decoder and the base station, since the speech encoder to the channel encoder is at half speed (ie 8 kbit in instead of 16 kbit). In addition, there is a more robust / better perceptual speech quality as the full-speed channel encoder could be designed to use half-speed WED to improve channel decoding.

The advantages of the present invention over the half-speed operation are as follows. The present invention provides a more robust / better perceptual speech quality because the half-speed speech bits are protected and even if the interleaving is the same, more than half of the channel bits are known.

The present invention introduces a full / half speed speed control type in addition to the existing full speed. manufactured half-speed speech encoder / decoder for the benefit of the full speed speech encoder / decoder during such a call. Consequently, a half-speed speech encoder / decoder is mixed with a modified full-speed channel encoder / decoder. The channel encoder / decoder used during such a call could be the full speed channel encoder / decoder with a different front. Consequently, a more robust half-speed operation is presented, which provides cost savings for the link between the speech encoder / decoder and the channel encoder / decoder.

Claims (6)

10 15 20 25 30 35 517 531 PATENT REQUIREMENTS 1. Communication system for providing a type of operation with combined full / half speed operation, characterized by: a half speed speech encoder / decoder; and a full speed channel encoder / decoder having a front arranged for communication with the half speed speech encoder / decoder, the front comprising a bit mapping restructuring module. Communication system according to claim 1, characterized in that the full-speed channel encoder / decoder is located in a base transceiver station and that the half-speed speech encoder / decoder is located at a distance therefrom. 3. A mobile station arranged for communication in a communication system, characterized by: a half-speed speech encoder / decoder; and a full speed channel encoder / decoder having a front arranged for communication with the half speed speech encoder / decoder, the front comprising a bit mapping restructuring module. Device according to one of the preceding claims, characterized in that the bit mapping restructuring module comprises bit restructuring from parameter to sensitivity order or sensitivity to parameter order. A method of providing combined full / half rate operation in a communication system having a half rate speech encoder / decoder and a full rate channel encoder / decoder, characterized by the step of providing a bit mapping restructuring as a front of the full speed encoder channel decoder for communication with the half-speed speech encoder / decoder. A method for providing a combined full / half rate operation in a communication system having first and second half rate speech encoders / decoders and a first and a second hybrid channel encoder / decoder, respectively. full speed processor, characterized by nine of the steps of: transmitting speech to the first half speed speech encoder / decoder for generating coded signals; transmitting the encoded signals from the half rate speech encoder / decoder to the first hybrid channel encoder / decoder processor at full speed; restructure the bits of the encoded signals in the first hybrid channel encoder / decoder processor at full speed; transmitting the restructured bits to a full rate channel encoder / decoder to generate additional encoded signals; transmitting said additional encoded signals to a full rate channel encoder / decoder in the second full speed hybrid channel encoder / decoder processor, for generating decoded signals; restructure the bits of the decoded signals in the second hybrid channel encoder / decoder processor at full speed; send the restructured bits to the second and half speed speech encoder / decoder for further decoding.