RU2157590C2 - Communication network, mobile communication station, and method for controlling operation mode of communication network - Google Patents

Abstract

FIELD: communication equipment. SUBSTANCE: invention may be used for combination of operation modes with total standard data transmission rate and halved data transmission rate. Claims of invention disclose device and method in which high and low data transmission rates are combined, so that low-rate voice encoder- decoder and high-rate channel encoder-decoder are used. Input of channel encoder-decoder is suited for communication to low-rate voice encoder-decoder. Input is equipped with bit redistribution module. EFFECT: increased functional capabilities. 4 cl, 6 dwg

Description

 The invention relates mainly to communication systems, in particular to methods and devices for combining operating modes with a full standard data transfer rate and a halved data transfer rate in a communication system.

 In digital communication systems there are devices that encode and decode speech signals to provide communication on radio frequencies. In GSM (Global System for Mobile Communications), a speech transcoder provides encoding and decoding functions in one device, which is sometimes called a speech codec (encoder-decoder). According to GSM Recommendation 06.10, the speech transcoder used in this system must be a 16-bit device. The channel codec has the same parameters, which is used to encode and decode additional information and voice data for transmission and reception over the air.

 In the modern GSM Digital Cellular Radio System, a speech codec provides 13 Kbps of compressed speech signals to a channel codec, which, in turn, provides 22.8 Kbps to the radio frequency path. This mode of operation is called a high-speed data transfer mode. It is also intended to use a speech data transmission mode with a speed reduced by half (low-speed mode), when the speech codec will output about 6 Kbps to a low-speed channel codec, which, in turn, will output 11.4 Kbps to the radio frequency path.

 In addition to data compression, an additional 3 Kbps are also used in the speech / channel codec interface for transmitting control and control information. Such information includes a Bad Data Block (BFI) flag, which serves as a warning to the speech decoder about the presence or absence of errors in the current block of compressed data coming from the channel decoder. This flag is used by the Continuous Transmission (DTX) scheme in a speech decoder to improve the quality of received speech. As part of the same 3 kbps, the type of call and operation modes is also transmitted, which can be characterized by high or low speed of voice data transmission. The mode of operation is transmitted to the channel codec, which then forwards this overhead information to the speech codec.

 The speech codec produces a block of compressed speech bits, grouped by speech parameters specific to the original speech. These parametrically ordered bits are then tuned by the channel codec in order of sensitivity. An error in one of the most sensitive bits makes it impossible to intelligently reproduce the original speech. Errors in the least sensitive bits cause only weak or even subjectively imperceptible distortions in the decoded speech.

 The channel codec is usually installed in the Base Transceiver (BTS), while the speech codec can be located in the BTS, in the Base Station Controller (BSC) or in the Mobile Switching Center (MSC). When the speech codec is not located on the BTS site, GSM establishes (sets) the interface or protocol to be used between the remote speech codec and the channel codec. Such an interface exists for the high-speed transmission mode (GSM document 08.60) and is planned for operation in the low-speed mode (08.60 or another GSM standard).

 The algorithms used in the high-speed speech codec and those that are supposed to be used in the low-speed speech codec are completely different. As a result of this, the parameters that they produce and the parametric distribution of sensitivity are also different.

 In both high-speed and low-speed operating modes, the channel codec uses 3 classes of bits: 1a, 1b, and 2, where the class 1a bit is the most sensitive, and the class 2 bit is the least sensitive. The types and volumes of channel coding for the bits of these three classes are different.

 In high speed mode, 50 bits of class 1a, 3 bits of Cyclic Control using the Redundant Code (CRC), 132 bits of class 1b, 78 class 2 and 4 terminal bits are used, which after encoding is 456 bits. In low speed mode, 22 bits of class 1a, 3 bits of CRC, 73 bits of class 1b, 17 bits of class 2 and 6 end bits are used, which after encoding is 228 bits.

 In both high-speed and low-speed modes, class 1a bits have Cyclic Monitoring using the Redundancy Code that is associated with these bits; class 1a, 1b and CRC bits are convolutionally encoded, and no extra protection is required for class 2 bits.

 In high-speed mode, the main thing for the CRC is the generation of the Defect Block flag (BFI). In low speed mode, the BFI flag is set not only by CRC, but also by the Error Detection Window (WED) scheme introduced as part of Motorola’s low speed mode algorithm.

 The GSM interface (GSM standard 08.60) between the remote speech codec and the channel codec operating in high-speed mode uses 16 Kbps. In the equivalent interface in low-speed mode, this figure should be reduced to 8 Kbps, which will lead to a halving of the rent for serial communication lines between the remote speech codec and the base station (channel codec). Plans are also underway to implement, in a low-speed mode, an interface between a remote speech codec and a channel codec using both 8 Kbit and 16 Kbit.

 In FIG. 1 shows the well-known Earth – LA communication line, where the high-speed speech transmission mode is performed using the high-speed speech codec 14 and the high-speed channel codec 20. The speech signals are input 10 and further to the audio interface 12 of the mobile station 11. Speech is encoded in a high-speed speech codec 14 mobile station. Next, coded speech is supplied to the processor 16 channel codec. This processor contains a standard and pre-prepared module 18 for parametric tuning in sensitivity, as well as a high-speed channel codec 20. From the output of high-speed speech codec 14, the signals are fed to a standard tuning block 18 for parametric tuning of bits for sensitivity. From the output of the standard module 18, the signals are fed to a high-speed channel codec 20 for further processing, and then fed to the radio frequency interface 22 for subsequent transmission of the working signals 24 through the air.

 The working signals 24 are received at the base transceiver station 13, processed in the radio frequency interface 22 and then fed to the processor 17 channel codec, which is similar to the processor 16 channel codec mobile station 11.

 The signals are fed to a high-speed channel codec 21 for initial processing (decoding), and then processed in module 19 with the tuning of bits according to the principle of "sensitivity - parameter". From the output of this module 19, the signals are fed to a high-speed speech codec 15 for further decoding and outputting speech 26 at a speed of 64 Kbps.

 High-speed speech codec 15 is shown as part of the BTS for reasons of clarity. Low speed mode can be implemented using a low speed speech and channel codec.

 It is desirable to provide a combined high / low speed mode of operation, which combines the advantages of low cost with high quality work and resistance to harmful influences.

 The present invention is based on the task of developing a communication system using a combined mode of operation with a high and low data rate, and containing a low-speed speech codec and a high-speed channel codec, when the input communication is carried out using a low-speed speech codec, including a module for redistribution, bit conversion .

 Also, the present invention is based on the task of creating a method for combining the operating modes of a communication system with a high and low data transfer rate, including the operation of redistributing the bit conversion when the input channel codec provides communication with the speech codec.

The invention is further illustrated by a specific embodiment with reference to the accompanying drawings, in which:
In FIG. 1 shows a block diagram of a communication line Earth - LA, operating in high speed mode.

 In FIG. 2 shows a block diagram of a device operating in a combined high / low speed mode in accordance with the present invention.

 In FIG. 3 shows a block diagram of an Earth – LA communication line operating in a combined high / low speed mode similar to the system shown in FIG. 2.

 In FIG. 4 illustrates an algorithm for operating a speech codec in accordance with the present invention.

 In FIG. 5 is a flowchart of a channel encoder according to the present invention.

 In FIG. 6 is a flow chart of a channel decoder according to the present invention.

 Shown in FIG. 2, a communication system capable of operating in a combined high / low speed mode and including a low speed speech codec 30 and a high speed channel codec 32, the input of which is adapted to communicate with a low speed speech codec 30 and containing an input module 33 for redistributing the bit conversion.

 The implementation of such a device operating in a combined mode can be described in particular with reference to FIG. 3, which shows a block diagram of a communication line Earth - LA, which also implements the combined high / low speed mode of operation in accordance with the present invention.

 The speech signals are fed to the input 10 of the audio interface 12 of the mobile station 11. The audio interface sends these signals to the first low-speed speech codec 30 to generate encoded signals.

 The encoded signals are supplied to the parameter-sensitivity redistributive conversion module 33 of the first hybrid channel processor 32, which redistributes the encoded signal bits, as described below. The redistributed bits are then fed to the high speed channel codec 20 for further processing. From the output of the high-speed channel codec 20, the signals are fed to the radio-frequency interface 22 and transmitted over the air to the second hybrid channel processor 31, already located at the base transceiver station 13.

 The high-speed channel codec 21 of the second hybrid channel processor 31 decodes the transmitted signals 34 and feeds them to the “sensitivity-parameter” bit redistribution module 35 of the second hybrid channel processor 31 to perform this bit allocation operation. The redistributed bits are then transmitted to the second low-speed speech codec 37 via a serial line 39 for further decoding and outputting 26 signals at a speed of 64 Kbps to its output. Serial line 39 is necessary if the second low-speed speech codec 37 is remote from the hybrid channel processor 31. Therefore, it is undesirable for the second low-speed speech codec 37 to be located away from the hybrid channel processor 31.

 In FIG. 4 shows the operation algorithm of speech codecs 30, 37 in accordance with the present invention. Since speech codecs must operate in high speed, low speed, and combined high / low speed modes in accordance with the present invention, it is necessary to indicate the desired mode of operation of the speech codec. For example, in FIG. 4, the speech codec determines which mode of operation is desired in step 40 of the algorithm, and if it is a high speed mode, then in step 44 a normal high speed encoding or decoding operation is performed. If a low-speed or combined high / low-speed mode is required, then the corresponding low-speed encoding or decoding operation is performed normally in step 42 of the algorithm.

 However, the operation of the channel encoder of the hybrid channel processor 20 is determined by the presence of the bit conversion redistribution module 33, which operates in accordance with the present invention, as described in FIG. 5. The hybrid channel processor or codec 32 determines in step 48 of the algorithm which channel operation mode is required. If this is a high-speed mode, then the normal high-speed channel coding operation is performed in step 53. Similarly, if a low-speed mode is required, then the normal low-speed channel coding operation is performed in step 51 of the algorithm.

 However, if a combined high / low speed mode of operation of the channel is specified, then the bit conversion redistribution module 33 of the hybrid channel processor 32 converts the low-speed speech parameters according to their sensitivity, which is specified by the standard low-speed algorithm in step 50. Then, the bit conversion redistribution module 33 receives all 22 bits class 1a with a low speed and determines a 3-bit CRC using the standard low-speed method in step 52, which results in a channel codec and 22 bits of class 1a and 3 bits of CRC. At the same time, in step 56, the bit tuning module 33 processes 73 bits of class 1b and 17 bits of class 2 with a low speed and adds 70 zeros to them, which results in 160 bits of class 1b for the channel codec.

 The resulting 22 bits of the channel codec of class 1a, 3 bits of CRC and 160 bits of the channel codec of class 1b are processed in step 54, respectively, as 22 bits of class 1a, 3 bits of CRC, 160 bits of class 1b and 4 terminal bits with high speed in the convolutional codec, which results in 378 convolutionally encoded bits. These convolutional encoded bits are combined with the class 2 bits of the channel codec (78 zeros), resulting in 456 bits being generated in step 58. These 456 bits go to the high-speed channel encoder, including interlace in step 60.

 The operation of the channel decoder of the hybrid channel processor 21 requires the reverse order of the bit redistribution module 35 in accordance with a preferred embodiment of the present invention, as explained in FIG. 6. The hybrid channel processor or codec 31 determines in step 60 which channel operation mode is required. If this is a high speed mode, then in step 61, channel decoding is performed normally. Similarly, if a low speed mode is required, then in step 63 a channel decoding operation with a low speed is performed.

 However, if the combined high / low speed is indicated as the desired mode, then in step 62, the non-intermittent normal high-speed signal is processed, resulting in 456 encoded bits. These 456 encoded bits are processed in step 64 to remove the redundant bits of the class 2 channel codec (78 zeros), resulting in 378 convolutional encoded bits. These 378 encoded bits are processed in the step of algorithm 66 by normal (standard) high-speed channel decoding with optional WED and are divided into bits of the channel codec classes 1a and 1b.

 The resulting 22 bits of class 1a and 3 bits of CRC are processed in step 68 by the standard low-speed cyclic control method using redundancy code with optional use of WED, resulting in the BFI flag being set. The expected 22 speech encoded bits of class 1a are converted in parameters, as required by the standard low-speed speech decoder, in algorithm step 70.

 The remaining 160 bits of the class 1b channel codec are also parameter-converted, as required by the standard high-speed speech decoder (step 70).

 The new required operating mode can be specified by adding the flag size, which is sent to the channel codec, indicating which type of operating mode you want to set: high-speed, low-speed or combined high / low-speed.

 The considered drawings can very easily be extrapolated in relation to the communication line LA - Earth.

 To summarize, we can say that the bit redistribution module can use the table to convert (display) bits.

Firstly, such a table, compiled according to the data of the speech encoder and according to the correspondence of the order of the parameters to the order of the distribution of sensitivities, is a table of low speed, not high speed. Secondly, after bit conversion, they are again divided into three classes for a high-speed channel codec. It is assumed that the number of bits of the channel codec of class 1a is 22 bits, class 1b is 160 and class 2 is 78. By converting, the following is achieved:
- all 22 bits of a class 1a speech codec correspond to 22 bits of a class 1a channel codec;
- all 73 bits of a class 1b speech codec and 17 bits of a class 2 speech codec correspond to 90 out of 160 bits of a class 1b channel codec;
- setting the correspondence of the remaining 160-90 = 70 bits of the channel codec of class 1b to some known value, for example, zero, and
- setting the correspondence of all 78 bits of a class 2 channel codec to a certain known value, for example, zero.

 As a result, all speech bits will have protection added by the channel encoder after they are assigned to class 1a or 1b.

 The reason for reducing the number of bits of class 1a is as follows. CRC control should be performed only with respect to those bits whose value is so large that an error of 1 could mean the impossibility of intelligible reproduction of the original speech. An increase in the number of bits of this class (1a) without an additional number of bits fulfilling the functions of CRC criteria could lead to unnecessary defects in the data block. Therefore, there is a need to assign bits to class 1a only when it is really necessary. An alternative to this is the need to have more bits of class 1b in order to have enough bits reaching the normal high speed convolutional encoder. In the normal scheme, the number of bits reaching such an encoder is 189 (50 class 1a, 3 CRC, 132 class 1b and 4 terminal). According to the present invention, the number of bits of class 1a is 22, 3 bits of CRC and 4 terminal, so that the number of bits remaining for class 1b is 160 (189-22-3-4).

 A third change in the channel codec is to introduce WED into the channel decoding process, as required for the low-speed codec (channel), and as shown in FIG. 6.

 The combination of high / low speed modes of the system and the method according to the present invention provide more stable operation in low speed and at the same time allow you to take advantage of multiplexing in the amount of 8 Kbit during communication between the remote speech codec and channel codec.

 The advantages of the present invention in high speed are as follows. The present invention provides high-speed operation, but with serial line rental between the remote speech codec and the base station corresponding to the low-speed mode, since the communication between the speech encoder and the channel encoder is in the low-speed mode (i.e. 8 Kbps instead of 16 Kbps ) In addition, it provides increased resistance to harmful effects and improved understanding of speech, since a high-speed channel encoder can use WED to improve channel decoding.

 The advantages of the present invention in low speed mode are as follows. The present invention provides increased resistance to harmful influences and improved speech intelligibility, since all speech bits in the low-speed mode are protected, and although interleaving takes place, more than half of the bits are known.

 In the present invention, the high / low speed mode is used in addition to the existing high speed and low speed modes. In combined mode, Motorola prefers a low-speed speech codec over a high-speed one. Thus, a low-speed speech codec is used in conjunction with a modified high-speed channel codec. The channel codec used during a call should be a high-speed channel codec with a different input. Thus, increased resistance to harmful effects in low speed mode is achieved, which also saves money when using the communication line between speech and channel codecs.

Claims (4)

 1. A communication device for providing a combined high / low speed mode of operation, said device comprising a low speed speech codec and a high speed channel codec, the input of which is configured to communicate with a low speed speech codec, and a bit redistribution unit configured to convert low speed is installed at the input speech parameters in accordance with their sensitivity, the processor cyclic control using redundant code to process ki of the first part of the converted speech parameters and determination of cyclic control using the redundant code using the low-speed method and a convolutional codec for high-speed coding of at least the first part and the second part of the speech parameter conversion, with the possibility of generating coded bits.  2. The device according to claim 1, in which the redistribution module, bit conversion contains the redistribution module parameter - sensitivity or sensitivity - parameter.  3. A method for providing a combined high / low speed mode of operation in a communication system having a low speed speech codec and a high speed channel codec, the method comprising the steps of: forming low speed speech parameters, converting low speed speech parameters in the form of low speed ordering of sensitivity, processing by cyclic control using the redundant code of the first part of the converted speech parameters, determine the cyclic control using the redundant code using the low-speed method, high-speed convolutional coding of at least the first part and the second part of the converted speech parameters is carried out, coded bits are generated, and at least coded bits are sent to the high-speed channel codec.  4. A method for providing a combined high / low speed mode of operation in a communication system having a low speed speech codec, a high speed channel codec, wherein high speed channel decoding of the received high speed non-intermittent output signal is performed, decoded bits are generated, cyclic control is performed using the redundant code, at least at least the first part of the decoded bits is checked by cyclic checking using redundant code using Using the low-speed method, they transform at least the decoded and processed by the cyclic control using the excess code of the bits in the form of low-speed speech parameters and send at least low-speed speech parameters to the low-speed channel codec.

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