RU2099719C1 - Meter of parameters of linear frequency-modulated signals - Google Patents

Abstract

FIELD: radio measurement technology. SUBSTANCE: device which has forming unit, two reciprocal counters and subtraction unit is additionally provided with control and synchronization unit, driven multivibrator unit, two digital delay lines, 2N+1 and gates, subtracting unit, summing unit, scaling unit, and digital Integrator consisting of multidigit adder and multidigit digital delay line. EFFECT: higher measurement accuracy. 1 dwg

Description

 The present invention relates to the field of digital radio measurement technology and can be used to measure the initial value of the carrier frequency and its rate of change within a pulse with linear frequency modulation in the processing mode of single or rarely repeated signals.

 A device is known, which is an analogue, and described in the book by Pavlenko Yu.F. Spanion P.A. Measurement of parameters of frequency-modulated oscillations. M. Radio and Communications, 1986, p. 95-101, fig. 2.30, which contains a modulating voltage generator, the first output of which through a frequency divider is connected to the input X of the oscilloscope, the second output of the modulating voltage generator is connected to one of the inputs of the FM generator, the output of which is connected to a mixer, the other input of which is connected to the output of the search generator, and the output the mixer is connected through a low-pass filter to the input Y of the oscilloscope, the other output of the FM generator is connected to the first input of the electronically counted frequency meter, the second input of which is connected to the search output th generator.

 This device allows you to measure the center frequency of a frequency-modulated signal, however, its drawback is the requirement of a sufficiently long measurement time, which with a finite duration of the chirp signal cannot always be achieved.

 A device is known, which is an analogue and described in the book by V. Likharev. Digital methods and devices in radar. M. Soviet Radio, 1973, p. 108, fig. 2.12 and p. 100, fig. 2.8 and which consists of a two-level quantizer connected at the input to the input signal bus, and its output through the former is connected to the input of the digital delay line and connected to the summing input of the reversing counter, the output of the digital delay line is connected to the subtracting input of the reversing counter, and the synchronizing the input is connected to the output of the control and synchronization unit, the outputs of the reversible counter are connected via output devices to the output buses.

 This device allows you to evaluate the current value of the frequency of filling the signal with intrapulse frequency modulation (chirp signal), but its disadvantage is the low accuracy of the measurement.

 A device is known which is a prototype and described in the USSR copyright certificate N 1449924, cl. G 01 R 23/00, B.I. N 1 from 01/07/1989, and containing an input shaper whose output is connected to the counting inputs of the first and second counting channels containing a selector, a counter and a buffer register in series, the selecting inputs of both channels are connected to the corresponding outputs of the counting time shaper containing a series connected reference oscillator, ten-day frequency divider and strobe generator, the outputs of which are the first and second outputs of the counting time generator, respectively, a single-census code rewriter the input of which is connected to the second output of the counting time former, and the output is connected to the control input of the buffer register of the second channel, a one-shot reset pulse, the output of which is connected to the zeroing input of the counter of the second channel, a subtraction unit, the output of which is connected to the indicator, and there is also a second one-shot the census of the code, the second one-shot of the reset pulse, the trigger, two switches, the input of the second one-shot of the census of the code is connected to the first output of the counting time generator, and the output is connected to the input the second one-shot reset pulse, to the R-input of the trigger and to the control input of the buffer register of the first counting channel, the output of the second one-shot reset pulse is connected to the resetting input of the counter of the first counting channel, the output of the first one-shot census code is connected to the input of the first one-shot reset pulse and with S- trigger input, the direct output of the trigger is connected to the control input of the first switch, the first information input of which is connected to the direct output of the first buffer register, and the second with the inverse by the output of the second buffer register, the inverse trigger output is connected to the control input of the second switch, the first information input of which is connected to the direct output of the second buffer register, the second information input with the inverse output of the first buffer register, the outputs of the switches are connected respectively to the first and second outputs of the subtraction block.

However, this device has the disadvantage that it has low accuracy in measuring the frequency of the carrier wave f _{x of the} chirp signal, regardless of the channel in which this measurement is made.

The inventor was faced with the task of creating a signal parameter meter with linear frequency modulation, which allows to increase the accuracy of measuring the initial value of the carrier frequency f _{x of the} chirp signal, while maintaining the accuracy of measuring the frequency change inside the pulse (the rate of change of the frequency inside the pulse μ _x ).

The technical result of the invention lies in the fact that the accuracy of measuring the initial value of the carrier frequency of the chirp signal increases while measuring the rate of its linear change and determine the sign of this change. In the considered analogues and in the prototype, in addition to measuring the rate of change of frequency, it is possible to measure the carrier frequency with some accuracy determined by the expression
2πf _x Δt + 0.5μ _x (Δt) ² ,
where Δt is the time interval determined by the blocks of its formation.

It can be seen that the frequency f _x is measured with an error of 0.5 μ _x (Δt) ² depending on both μ _x and Δt. The elimination of this measurement error f _x while maintaining the accuracy and sign of the measurement μ _x is the technical result of the proposed device.

 The technical result is achieved by the fact that in the device containing the forming unit, the information input of which is connected to the input signal bus, two reverse counters and the subtraction unit, a control and synchronization unit is introduced, the first output of which is connected to the control input of the forming unit, the multivibrator is waiting, and also two series-connected digital delay lines, the inputs and outputs of which are connected to the summing and subtracting inputs of the corresponding reversing counters, the input of the first digital line The delay is connected to the output of the forming unit, the output of the second digital delay line is connected to the input of the And element, the second input of which is connected to the synchronizing inputs of the digital delay lines and to the second synchronizing output of the control and synchronization unit, the outputs of the reversible counters are connected to the corresponding inputs of the subtraction unit, the outputs of which connected to the first inputs of the first group of input N elements AND, the second inputs of which are combined and connected to the output of the standby multivibrator unit, the information input to which is connected to the output of the And element, and the control output is connected to the third output of the control and synchronization unit, a second group of N And elements, a subtraction unit, a summing unit, a scaling unit and a digital integrator consisting of a multi-bit adder and a multi-bit digital delay line unit, are also introduced moreover, the first inputs of the introduced second group of N elements And are connected to the outputs of the second reversible counter, their second inputs are combined and connected to the output of the standby multivibrator, and their outputs are connected to the first inputs of the input subtraction block, the outputs of which are the first outputs of the device, the second inputs of the input subtraction block are connected to the outputs of the input summation block, the first inputs of which are connected to the outputs of the digital integrator, the second inputs of the input summation block are connected to the outputs of the first group of N elements AND, which also connected to the corresponding inputs of the scaling unit, the outputs of which are connected to the second outputs of the device and to the inputs of the digital integrator, to which are connected the outputs of a multi-bit adder, the outputs of which are connected to the inputs of the multi-bit digital delay line unit, the synchronizing input of which is connected to the second output of the control and synchronization unit, the fourth output of which is connected to the zero-setting inputs of the digital delay lines, reverse counters and the multi-bit digital delay line unit, output block multi-bit digital delay line connected to the output buses of the digital integrator and the second inputs of the multi-bit adder.

Achieving a positive effect will be shown as follows. If you use the device described in ed. N 1449924, a code proportional to the algebraic quantity μ _x Δt is generated at its output. A code located at the time 2Δt in the second counter will be proportional to 2πf _x Δt + 0.5μ _x (Δt) ² , and therefore, its direct reading will give the value carrier code with error. In addition, the time shift of the measuring interval is accompanied by an increase in this error. Introduced additional nodes in the selected prototype provides a measurement of f _x without these systematic errors, which achieves a positive effect, namely, it increases the accuracy of measuring the initial value of the carrier frequency of the pulse f _x with a linearly varying modulation frequency inside it while maintaining this accuracy throughout the measurement interval and while maintaining the accuracy of changing the magnitude and sign of the rate of linear change of frequency μ _x (see also the book Pavlenko Yu.F. Spanion PA "Measurement of the parameters of frequency-modulators these vibrations ". M. Radio and communication, 1986, S. 65 72).

 The drawing shows a structural diagram of a meter of signal parameters with linear frequency modulation.

 The linear frequency modulation signal parameter meter shown in the drawing contains a forming unit 1, the information input of which is connected to the input signal bus, the control input is connected to the first output of the control and synchronization unit 2, and its output is connected through two series-connected digital delay lines 3 and 4 with the first input of AND element 5, the second input of which is connected to the synchronizing second output of the control and synchronization unit 2 and to the synchronizing inputs of two digital delay lines 3 and 4, and the output of element And 5 is connected to the input of the standby multivibrator 6, the control input of which is connected to the third output of the control and synchronization unit 2, the inputs and outputs of digital delay lines 3 and 4 are connected respectively to the summing and subtracting inputs of the first 7 and second 8 reversible counters, which connected at the inputs of the zero setting with the fourth output of the control and synchronization unit 2, to which the first 3 and second 4 digital delay lines are also connected at the inputs of the zero setting, the outputs of the reversible counters 7 and 8 are connected s with the corresponding inputs of the subtraction unit 9, the outputs of which are connected to the first inputs of the N elements And 10, the second inputs of which are combined and connected to the output of the standby multivibrator 6, the first inputs of the N elements And 11 are connected to the outputs of the second reversible counter 8, their second inputs are combined and connected to the output of the standby multivibrator 6, and their outputs are connected to the first inputs of the subtraction unit 12, the outputs of which are the first outputs of the device, the second inputs of the subtraction unit 12 are connected to the outputs of the summing unit 13, the first inputs of which are connected to the outputs of the digital integrator 14, the second inputs of the summing unit 13 are connected to the outputs of the N elements And 10, which are also connected to the corresponding inputs of the scaling unit 15, the outputs of which are connected to the second outputs of the device and to the inputs of the digital integrator 14 to which are connected the first inputs of the multi-bit adder 16, the outputs of which are connected to the inputs of the multi-bit digital delay line 17, the synchronizing input of which is connected to the second output of the control and synchronization unit 2, the fourth output of which is connected to the zero-setting input of the multi-bit digital delay line 17, the output of which is connected to the output buses of the digital integrator 14 and to the second inputs of the multi-bit adder 16.

 The device operates as follows. Suppose that at time t 0 all digital nodes are set to zero by the signal from the fourth output of block 2, i.e. all digital delay lines (DLCs) have zeros and the reverse counters are reset to zero.

Отметим, что независимо от знака при величине 0,5μ_xt² работа устройства не изменяется. Необходимо будет только учитывать этот знак при проведении соответствующих выкладок. В дальнейшем будем полагать, что знак положителен.Suppose that at time t 0 on the device is input chirped signal with an unknown center frequency f _x, located within the range f _min f _max, and the unknown rate of change of μ _x signal duration time _and τ and can be written as

Note that regardless of the sign at a value of 0.5μ _x t ^{2 the} operation of the device does not change. It will only be necessary to consider this sign when carrying out the corresponding calculations. In the future, we will assume that the sign is positive.

This signal is fed through the output bus to the input of the forming unit 1, at the output of which signals appear as a sequence of zeros and ones. Suppose that the units correspond to the positive values of the real part of the exponent, and the zeros are negative. At the same time, in block 1, signals are generated, the instants of which in time at the output of block 1 are synchronized with the time instants of the clock pulses coming from block 2 to the control inputs of the digital delay line 3 with a frequency selected from the condition of Kotelnikov’s theorem, i.e. with a frequency of at least 2f _max . At the same time, the asynchronous input pulse arrival mode is synchronized with the digital nodes synchronous operation mode so that for each half-period of the carrier frequency of the input LFM signal, one pulse is generated, which is recorded simultaneously from the clock signal from block 2 to DLC 3 and the N-bit reverse counter 7 (RS 7). The maximum delay time in DLC 3 and 4 is Δt ≅ 0.5τ _{and the} signals arriving at the input of DLC 3 move along it under the action of clock pulses coming from the output of block 2.

At the same time, these same signals are fed to the summing input of the PC 7, which begins to count the number of periods of the input oscillation. At each current discrete time instant t = nθ where n 0,1,2. θ = Δt / 2 ^N 0≅ t≅ Δt, in PC 7 there will be a code proportional to the integer number of periods of high-frequency filling. At time t Dt, at the output of the DSC 3 there will be a signal delayed by the time Dt and which goes to the second DSC 4, to the subtracting input of the PC 7 and summing the input of the N-bit reversible counter 8 (PC 8). As in DLC 3, in DLC 4, the delay time is Dt, synchronizing pulses from the output of block 2, which shift the signal pulses along this DLC 4, arrive at its summing input at the same clock frequency. At times Dt ≅ t ≅ 2Δt at the outputs RS 8 will be a code proportional to the number of periods of high-frequency filling and which will be equal to the code that was in RS 7 at time 0 ≅ t ≅ Δt.

и величина которого нарастает с ростом времени t, что не позволяет точно измерить несущую частоту f_x на интервале времени Δt. Очевидно, что максимальное значение кода, которое может быть записано в РС 7, будет зависеть от значений величины f_макс и τ_и и будет определять требования к его разрядности.At the same time, in PC 7 there will be a code equal to the frequency difference of the signals at its inputs, that is, a code proportional to

and the value of which increases with increasing time t, which does not allow to accurately measure the carrier frequency f _x on the time interval Δt. Obviously, the maximum value of the code that can be stored in the PC 7 will depend on the values of τ and f _{max and} will determine the requirements for its bit depth.

Одновременно в РС 7 будет находиться код, равный разности частот сигналов на его входах, то есть код, пропорциональный величине

Полученные значения с выходов РС 7 и 8 в виде параллельных цифровых кодов поступают на входы блока вычитания 9. На выходах этого блока образуется код, величина которого пропорциональна разности кодов чисел, поступивших с выходов РС 7 и 8 и которая будет равна

Одновременно в момент времени t 2Δt сигнальный импульс совпадает с импульсом с выхода блока 2 на входах элемента И 5 и на его выходе появляется сигнал, который поступает на вход блока ждущего мультивибратора 6, на выходе которого появляется разрешающий сигнал с задержкой на Δτ, величина которой больше или равна времени переходных процессов в блоке вычитания 9 и которая определяется сигналом с третьего выхода блока управления и синхронизации 2. Этот сигнал поступает на соединенные вместе входы N элементов И 10, на вторых входах которых находится результат вычисления кода разности с выходов блока вычитания 9 и который появляется на выходах элементов И 10.At time t 2Δt, the signal pulse reaches the end of the CLL 4 and enters the subtracting input of PC 8 and the input of element And 5. At this time, the outputs of PC 8 display a code proportional to the frequency difference of the signals at its inputs, that is, a code proportional to

At the same time, in PC 7 there will be a code equal to the frequency difference of the signals at its inputs, that is, a code proportional to

The obtained values from the outputs of PC 7 and 8 in the form of parallel digital codes are fed to the inputs of the subtraction unit 9. At the outputs of this block, a code is generated whose value is proportional to the difference of the codes of the numbers received from the outputs of PC 7 and 8 and which will be equal to

At the same time, at a time t 2Δt, the signal pulse coincides with the pulse from the output of block 2 at the inputs of the And 5 element and a signal appears at its output, which is fed to the input of the block of the waiting multivibrator 6, the output of which is an enable signal with a delay by Δτ, the value of which is greater or equal to the transient time in the subtraction unit 9 and which is determined by the signal from the third output of the control and synchronization unit 2. This signal is fed to the inputs of N elements And 10 connected together, the second inputs of which are the calculation result of the difference output from the subtractor 9 and a code which appears on the outputs of the AND elements 10.

 At the same time, the code at the output of PC 7 will be located at the first inputs of N elements And 11, at the second inputs of which there is an enable signal from the output of the block of the waiting multivibrator 6.

This code in the form of a value equal to
2πf _x Δt + 0.5μ _x (Δt) ² ,
will go to the first inputs of the subtraction block 12.

At the same time, the code from the outputs of the N elements And 10, equal to the value of μ _x (Δt) ² , enters the inputs of the scaling unit 15, the output of which displays a code proportional to the value of μ _x Δt and which goes to the second outputs of the device. The magnitude and sign of the code corresponding to μ _x Δt determines the magnitude and sign of the frequency deviation of the chirp signal.

At the same time, the code μ _x (Δt) ² from the outputs of N elements And 10 enters the second inputs of the summing unit 13, which has a weight coefficient of 0.5 at these inputs.

At the same time, a code proportional to μ _x Δt, from the output of the scaling unit 15, is supplied to the inputs of the digital integrator 14, to which the first inputs are connected with the coefficient θ of the multi-bit adder 16, at the other inputs of which with a coefficient equal to one, a code equal to zero, and therefore, the code corresponding to m _x Dtθ is recorded in the block multi-bit digital delay line 17.

и который поступает на вычитающий вход блока вычитания 12.At the same time, the outputs of the multi-bit digital delay line 17 will have a code corresponding to zero and which, in addition to entering the second inputs with a coefficient equal to one, of the multi-bit adder 16, also goes to the first inputs of the summing unit 13, the output of which will display a code proportional to the value

and which is fed to the subtracting input of the subtraction unit 12.

что соответствует начальной несущей частоте ЛЧМ-сигнала.At the same time, the output corresponding to the value

which corresponds to the initial carrier frequency of the chirp signal.

Этот код через N элементов И 11 поступает на первые входы блока вычитания 12.At the next discrete time instant ^{t = 2Δt + θ,} at the output of PC 8 there will be a code corresponding to the value

This code through N elements And 11 goes to the first inputs of the subtraction block 12.

Коды с выходов РС 7 и РС 8 одновременно поступают на блок вычитания 9, на выходах которого появляется код, соответствующий величине

Этот код через N элементов И 10 поступает на блок масштабирования 15, на выходе которого появляется код, пропорциональный величине μ_xΔt и который поступает на вторые входы устройства. Этот же код μ_xΔt поступает на входы цифрового интегратора 14, к которым подключены первые входы с коэффициентом θ многоразрядного сумматора 16. На других входах многоразрядного сумматора 16 будет находиться код m_xDtθ который в этот момент времени появится на выходе блока многоразрядной цифровой линии задержки 17. Следовательно код, который будет равен сумме кодов на входах многоразрядного сумматора 16
^μx^{Δtθ + μ}x^{Δtθ = μ}x^Δt2θ,,
будет записан в блок цифровой многоразрядной линии задержки 17.At the same time, the output of PC 7 will be a code corresponding to the value

Codes from the outputs of PC 7 and PC 8 simultaneously arrive at the subtraction unit 9, at the outputs of which a code corresponding to the value

This code through N elements And 10 enters the scaling unit 15, the output of which appears a code proportional to the value of μ _x Δt and which goes to the second inputs of the device. The same code μ _x Δt is supplied to the inputs of the digital integrator 14, to which the first inputs are connected with the coefficient θ of the multi-bit adder 16. At the other inputs of the multi-bit adder 16 there will be a code m _x Dtθ that will appear at the output of the multi-bit digital delay line unit 17. Therefore, a code that will be equal to the sum of codes at the inputs of the multi-bit adder 16
^μ x ^{Δtθ + μ} x ^{Δtθ = μ} x ^Δt2θ,,
will be recorded in the block digital multi-bit delay line 17.

а следовательно, на выходах блока суммирования 13 будет код, пропорциональный величине
0,5μ_x(Δt)² + μ_xΔtθ.
Этот код поступает на вторые вычитающие входы блока вычитания 12, на других входах которого с выходов N элементов И 11 будет код, пропорциональный величине

Следовательно, на выходе блока вычитания 12 будет код, пропорциональный величине

и который поступает на первые выходы устройства.At the same time, the code μ _x (Δt) ² from the outputs of N elements And 10 enters the second inputs of the summing block 13 with a coefficient of 0.5, a code proportional to the value arrives at its first inputs from the output of block 17

and therefore, at the outputs of the summing unit 13 there will be a code proportional to the value
0.5 μ _x (Δt) ² + μ _x Δtθ.
This code is fed to the second subtracting inputs of the subtraction unit 12, at the other inputs of which from the outputs of N elements AND 11 there will be a code proportional to the value

Therefore, the output of the subtraction block 12 will be a code proportional to the value

and which goes to the first outputs of the device.

Этот код через N элементов И 11 поступает на первые входы блока вычитания 12. Одновременно на выходе РС 7 будет код, соответствующий величине

Коды с выходов РС 7 и РС 8 одновременно поступают на блок вычитания 9, на выходах которого появляется код, соответствующий величине

Этот код через N элементов И 10 поступает на блок масштабирования 15, на выходе которого появляется код, пропорциональный величине μ_xΔt и который поступает на вторые выходы устройства. Этот же код μ_xΔt поступает на входы цифрового интегратора 14, к которым подключены первые входы с коэффициентом θ многоразрядного сумматора 16, на других входах которого находится код m_xDt2θ который в этот момент времени появится на выходе блока многоразрядной цифровой линии задержки 17.Thus, at a discrete time instant t = 2Δt + θ, as well as at a discrete time instant t = 2Δt, at the first outputs of the device there will be a code corresponding to the carrier frequency and proportional to 2πf _x Δt and at the second outputs there will be a code corresponding to the sign and value of the deviation frequency and proportional to μ _x Δt
At the next discrete time instant t = 2Δt + 2θ, at the output of PC 8 there will be a code corresponding to the value

This code through N elements And 11 is supplied to the first inputs of the subtraction unit 12. At the same time, at the output of PC 7 there will be a code corresponding to the value

Codes from the outputs of PC 7 and PC 8 simultaneously arrive at the subtraction unit 9, at the outputs of which a code corresponding to the value

This code through N elements And 10 enters the scaling unit 15, the output of which appears a code proportional to the value of μ _x Δt and which goes to the second outputs of the device. The same code μ _x Δt is supplied to the inputs of the digital integrator 14, to which the first inputs are connected with the coefficient θ of the multi-bit adder 16, the other inputs of which contain the code m _x Dt2θ which at that moment of time will appear at the output of the multi-bit digital delay line 17.

Therefore, a code that will be equal to the sum of the codes located at the inputs of the multi-bit adder 16 in the form
μ _x Δt2θ + μ _x Δtθ = μ _x Δt3θ,
will be written to block 17.

с выходов N элементов И 10 поступает на вторые входы блока суммирования 13 с коэффициентом 0,5, на его первые входы с выхода блока 17 поступает код, пропорциональный величине μ_xΔt2θ а следовательно, на выходах блока суммирования 13 будет код, пропорциональный величине
0,5μ_x(Δt)² + μ_xΔt2θ.
Этот код поступает на вторые вычитающие входы блока вычитания 12, на других входах которого с выходов N элементов И 11 будет код, пропорциональный величине
2πf_xΔt + 0,5μ_x(Δt)² + μ_xΔt2θ
Следовательно, на выходе блока вычитания 12 будет код, пропорциональный величине

и который поступит на первые выходы устройства.Code at the same time

from the outputs of N elements AND 10 is supplied to the second inputs of the summing block 13 with a coefficient of 0.5, a code proportional to μ _x Δt2θ is supplied to its first inputs from the output of block 17 and, therefore, the outputs of the summing block 13 will have a code proportional to
0.5 μ _x (Δt) ² + μ _x Δt2θ.
This code is fed to the second subtracting inputs of the subtraction unit 12, at the other inputs of which from the outputs of N elements AND 11 there will be a code proportional to the value
2πf _x Δt + 0.5μ _x (Δt) ² + μ _x Δt2θ
Therefore, the output of the subtraction block 12 will be a code proportional to the value

and which will go to the first outputs of the device.

и этот код через N элементов И 11 поступает на первые входы схемы вычитания 12.Thus, at a discrete time instant t - 2Δt + 2θ, as well as at previous discrete time instants, at the first outputs of the device there will be a code proportional to 2πf _x Δt and at its second outputs a code proportional to μ _x Δt
At an arbitrary discrete time moment t = 2Δt + nθ where 2Δt <t <τ _and at the output of PC 8 there will be a code corresponding to the value

and this code through N elements And 11 goes to the first inputs of the subtraction circuit 12.

Коды с выходов РС 7 и РС 8 одновременно поступают на блок вычитания 9, на выходах которого появляется код, соответствующий величине

Этот код через N элементов И 10 поступает на блок масштабирования 15, на выходе которого появляется код, пропорциональный величине μ_xΔt и который поступает на вторые выходы устройства.At the same time, the output of PC 7 will be a code corresponding to the value

Codes from the outputs of PC 7 and PC 8 simultaneously arrive at the subtraction unit 9, at the outputs of which a code corresponding to the value

This code through N elements And 10 enters the scaling unit 15, the output of which appears a code proportional to the value of μ _x Δt and which goes to the second outputs of the device.

который в этот момент времени появится на выходе многоразрядной цифровой линии задержки 17.The same code ^μ x ^{Δt is} supplied to the inputs of the digital integrator 14, to which the first inputs are connected with a scaling factor θ of the multi-bit adder 16, at the other inputs of which there is a code

which at this point in time will appear at the output of a multi-bit digital delay line 17.

Therefore, a code that will be equal to the sum of the codes located at the inputs of the multi-bit adder 16 in the form
μ _x Δtnθ + μ _x Δtθ = μ _x Δt (n + 1) θ, will be written in block 17.

и который поступит на первые выходы устройства.At the same time, the code μ _x (Δt) ² from the outputs of N elements And 10 is supplied to the second inputs of the summing block 13 with a coefficient of 0.5, a code proportional to μ _x Δtnθ is received at its first inputs from the output of block 17.
Therefore, the outputs of the summing unit 13 will be a code proportional to the value
0.5 μ _x (Δt) ² + μ _x Δtnθ.
This code is fed to the second subtracting inputs of the subtraction unit 12, at the other inputs of which from the outputs of the elements AND 11 there will be a code proportional to the value
2πf _x Δt + 0.5μ _x (Δt) ² + μ _x Δtnθ
Therefore, the output of the subtraction block 12 will be a code proportional to the value

and which will go to the first outputs of the device.

Thus, at each discrete time moment t = 2Δt + nθ, as well as at any other time points, the first outputs of the device will have a code proportional to 2πf _x Δt and at its second outputs a code proportional to μ _x Δt
At time t = τ _{, the} enable signal coming from the output of the block of the waiting multivibrator 6 will end, which will lead to the fact that all the elements And 10 and 11 are closed and there will be codes corresponding to zero at their outputs. At the same time, the zero-setting signal from the fourth output of the control and synchronization unit 2 will set the CLZ 3 and 4, PC 7 and PC 8 to zero, as well as the multi-bit digital delay line unit 17. After the time interval determined by the recovery time of the standby multivibrator 6, the measurement device parameters of the linear frequency modulated signals are ready for use.

 Note that the second outputs of the device can be connected to the output of the And 10 element, however, in this case, when the Δt value changes (that is, the delay time in the DLC 3 and 4), the values of the carrier frequency and deviation codes change disproportionately, which complicates the measurement process in some cases .

The technical and economic efficiency of the proposed device can be evaluated as follows. Since instruments and devices, similar to those declared, are not manufactured by our industry, it is advisable to compare them with the prototype. In the case used for measurement of the carrier frequency f _x in the prototype obtained code value, the measurement accuracy depends on Δt analysis time and on the value of μ _x Even if these quantities are small relative to the pulse duration τ _{and the} and the carrier frequency f _x, respectively, in order not less accuracy f _x in the prototype is directly proportional to the ratio μ _x / f _x
In the proposed device due to the introduction of additional nodes in the measurement process, regardless of the Δt and μ _x values, an exact measurement of the carrier frequency f _{x is} performed simultaneously and without loss of accuracy of the value μ _x
Thus, this device allows you to measure the value of the initial value of the carrier frequency f _x with a given accuracy, determined by Δt and independent of the value of μ _x, as well as measure the magnitude and sign of the frequency deviation μ _x without loss of accuracy, which indicates a high technical and economic the effectiveness of the proposed device.

Claims (1)

 A linear frequency modulated signal parameter meter comprising a generating unit, the information input of which is connected to the input signal bus, two reversible counters and a subtraction unit, characterized in that a control and synchronization unit is introduced into it, the first output of which is connected to a control input of the generating unit, the multivibrator standby unit, as well as two series-connected digital delay lines, the inputs and outputs of which are connected to the summing and subtracting inputs of the corresponding reversible counters sensors, the input of the first digital delay line is connected to the output of the forming unit, the output of the second digital delay line with the input of the And element, the second input of which is connected to the synchronizing inputs of the digital delay lines and to the second synchronizing output of the control and synchronization unit, the outputs of the reversing counters are connected to the corresponding inputs a subtraction unit, the outputs of which are connected to the first inputs of the first group of input N elements AND, the second inputs of which are combined and connected to the output of the block of the waiting multivibra a torus, the information input of which is connected to the output of the And element, and the control output with the third output of the control and synchronization unit, a second group of N And elements, a subtraction unit, a summing unit, a scaling unit, and a digital integrator consisting of a multi-bit adder and a multi-bit digital block are also introduced delay lines, and the first inputs of the introduced second group of N elements And are connected to the outputs of the second reversible counter, their second inputs are combined and connected to the output of the standby multivibrator block, and their the outputs are connected to the first inputs of the input subtraction block, the outputs of which are the first outputs of the meter, the second inputs of the input subtraction block are connected to the outputs of the input summing block, the first inputs of which are connected to the outputs of the digital integrator, the second inputs to the outputs of the first group of N elements And, which are also connected with the corresponding inputs of the scaling unit, the outputs of which are connected to the second outputs of the meter and to the inputs of the digital integrator, to which the first inputs are connected the adder, the outputs of which are connected to the inputs of the multi-bit digital delay line unit, the synchronizing input of which is connected to the second output of the control and synchronization unit, the fourth output of which is connected to the zero-setting inputs of the digital delay lines, reversible counters and the multi-bit digital delay line unit, the output of the multi-bit block the digital delay line is connected to the output buses of the digital integrator and to the second inputs of the multi-bit adder.