RU197391U1 - DIGITAL FREQUENCY METER - Google Patents

Abstract

The digital frequency meter consists of an input signal receiving port, a receiving port for calculating highly stable microwave pulses, three groups of counters with a register at the output of the measuring counter, a trigger connected to a synchronization circuit, a measurement interval determination trigger, and two channel switching trigger, made in the form of two reversed input groups counters from the senior and junior digits, two multiplexers of the senior and junior digits, designed to change the display of output information from channels, a block of logical elements designed to control the production of the measuring interval, determine the frequency difference of the input and reference signals and switch channels and counting signs of the difference of these frequencies, the memory register of the whole part of the input signal, as well as from the corrector of the fractional part in the form of its divider by mantissa measured frequency, made on the basis of a chip programmable integrated logical structure. The technical result is to increase accuracy. 2 ill.

Description

The utility model relates to measuring technique and can be used in gyroscopes - magnetrons, radio engineering, in microcontrollers and other devices where precision measurement of high frequency signals up to tens of gigahertz and their small deviations from nominal values, as well as very short time intervals is required. At the same time, they are supposed to be used in orientation and navigation systems on moving objects — airplanes, ships, and others, in the form of sensors, which require continuous operation and a sufficient frequency of information output.

Digital frequency meters of various designs are known. For example, a frequency meter is known [RF Patent No. 2210785; 1], including an input signal receiving port, a measuring period pulse receiving port, a reference generator, three counters, three registers at their outputs, two synchronization circuits, an inverter, an error pulse shaper, a pulse stretching circuit, a processing and indication tool.

This frequency meter is not characterized by a wide range of measured frequencies. The limitation on this range is due to the fact that the duration of the extended pulse should not exceed the duration of the measuring interval.

Another frequency meter is known, characterized in that, in order to expand the range of measured frequencies, it is equipped with a second error pulse shaper, a second duration measurement channel (counter and register connected in series) and a mismatch selection circuit [RF Patent No. 2210785; 1]. This frequency counter is an analogue of the proposed frequency counter according to the number of similar features. A complex circuit has been introduced in this frequency meter: a second error pulse shaper, a second duration measurement channel, and a mismatch selection circuit. In this case, to measure the time interval between the end of the measurement period and the next edge of the measured frequency, this interval is divided into two intervals, one of which contains an integer number of periods of the reference frequency, and the other contains a fractional part of this period. Only the second interval is measured using a stretching circuit, and the first interval is measured in an additional channel for measuring duration based on a counter that counts the impulses of the reference frequency.

The disadvantage of this frequency meter is the complexity of its design.

The closest analogue adopted for the prototype is the invention according to the project [Pat. RF №2278390; 2].

The device contains a port for receiving an input signal, a port for receiving a pulse of a measuring period, a reference generator, three counters with registers at the outputs, two synchronization circuits, an inverter, an error pulse shaper, a pulse stretching circuit and a processing and indication means, a trigger. High accuracy of measurements is provided by the channel for determining the delay of the front, which makes it possible to specify the duration of the pulse arriving at its input. To accurately measure this duration, the generated signal is fed to a duration stretching circuit that generates a pulse whose duration is increased by a predetermined number of M times, for example, M-100. This pulse is supplied to the control input of the counter, and the signal of reference frequency F ₀ from the output of the reference generator is supplied to its counter input. The counter counting result during the existence of a pulse at its control input, proportional to this duration, is read into the register, and from it into the processing and indication means (computer), which makes it possible to clarify the arrival time of the measured signal front from which the error pulse was generated. Thus, the pulse counting channel calculates an integer number of periods of the measured frequency falling in the measuring interval τ specified by the pulses. Simultaneous counting of pulses from the output of the reference generator for these intervals by the counter makes it possible to calculate the time scale to which the results of reading the counter are linked. Channel B allows you to specify the time interval from the moment of formation of the last edge of the signal F ₁ within the measurement period to the moment of reading the counter codes into the registers, respectively. Reading control is carried out by the WR signal, which is synchronized by an inverted reference frequency pulse. Reading the code K _E from the counter into the register is carried out earlier, for which the pulse from the output port of the pulse receiving port of the measuring period serves. The connection of the output of the element with the control zeroing of the counter input may be absent, since the counter may be reset to zero or not reset. In the second case, the counting result in the measurement cycle is calculated as the difference between the received code and the previous one.

The disadvantage of the prototype is to work with continuous streams of pulses that are not divided into intervals in the channels of the input and reference signals, it does not provide operations and device circuits for calculating the difference in the number of pulses and their signs between the same intervals of the input and reference signals, as well as their accumulation.

The second disadvantage inherent in the prototype is the discontinuity and disconnection of the measurement and indication processes (digital input signal circuit), which makes it difficult to use them as sensors for information on frequency deviations that should work continuously.

These shortcomings are eliminated in the proposed technical solution.

The technical result of the utility model is not only to increase the accuracy of measuring the input signal, but also to determine the small difference frequency between the input f and the reference signals. This is achieved by introducing the channel control logic block into the circuit, increasing the number of counters to ensure the counting of high and low order signals, introducing two multiplexers and a programmable integrated logic microcircuit.

The purpose of the proposed utility model is to increase the speed in operations of counting the frequency of the input signal, as well as the determined difference signal between the frequencies of the input and reference signals, proportional, for example, to the measured angular velocity of a moving object.

This goal is achieved due to the fact that in a digital frequency meter, which includes an input signal receiving port, a receiving port for countable highly stable microwave pulses, three groups of counters with a register at the output of the measuring counter, a trigger connected to a synchronization circuit, is also a part of a digital frequency meter introduced an additional trigger for determining the measuring interval and a trigger for switching two channels, made in the form of introduced two groups of reverse counters from the older and younger series, also introduced two high and low order multiplexers designed to change the display of output information from the channels, a block of logic elements was introduced to control the generation of the measuring interval, determine the frequency difference of the input and reference signals and switch channels and counting signs of the difference of these frequencies the memory register of the integer part of the input signal, as well as the corrector of the fractional part in the form of its divider by the measured frequency mantissa, made on the basis of the microcircuit programmable integrated logic structure, while the outputs of the first multi-input circuit "and - not", the outputs of the trigger switch the first channel to the second, the outputs of the ports for receiving input and counting signals, with the outputs of the block of logic elements, are connected to the inputs of the block of logic elements with the corresponding inputs of the block of logic elements input counters, register control inputs for storing the integer value of the input signal, inputs of the low-order counters of the first and second channels, the outputs of two counters of the highest p discharges are connected to the inputs of the high-order output switching multiplexer, and the outputs of two low-order counters are connected to the inputs of the low-order switching multiplexer, the register outputs and the multiplexer unit are connected to the corresponding inputs of the programmable logic integrated circuit chip, the first output of which is the difference frequency, and the second output her and digital frequency meter - an integer number of pulses of the input signal for the measurement period.

A diagram of the proposed utility model is shown in FIG. 1. In the diagram of FIG. 1 the following notation is accepted:

1 - port for receiving input signals in the form of a shaper - an input Schmidt trigger;

2 - reception port - shaper of rectangular periodic pulses of increased quantization frequency f _c ;

здесь и далее для младших разрядов,3-group counters, bar sign

hereinafter for the lower digits,

4, 4 '- counters for the formation of the reference frequency f ₀ ;

5 - a group of n counters forming the frequency f of the counting intervals;

6 - a group of n input pulse counters measuring the integer part of the frequency / input signal;

7 - circuit "and - not", the first multi-input, (n + 2 inputs);

8 - trigger allocation of accumulations of the phase difference for frequencies f and f ₀ to form a window for counting pulses of high frequency f _c ;

9 - trigger switching the first channel to the second;

10 is a block of logical channel control elements based on two-input standard circuit elements "and - not" for highlighting the frequency difference of the accumulated phases corresponding to the difference of the input and reference frequencies Δf;

11 is a register for storing an integer value of the frequency of the input signal;

12 - counter MSB ^1st channel;

12 '- the counter of the least significant bit of the ^1st channel;

13 - MSB counter 2 ^Channel;

13 '' - counter of the least significant bit of the ^2nd channel;

14 - multiplexer switching from the ^1st channel to the ^2nd outputs of the senior discharge Δf;

14 '- switching multiplexer from the ^1st channel to the ^2nd outputs of the least significant bit Δf;

15 - programmable integrated logic structure (FPGA chip).

будут отсутствовать.For a rougher implementation of the scheme with one fraction of the fractional part, elements with a dash

will be absent.

The circuit elements of FIG. 1 are connected as follows: The output of the shaper 1 is connected to the counting input of the counter 6 ,. the output of the shaper 2 is connected to the counting input of the counter 3, namely to the least significant bit 4 ', and also to the counting input of the control unit 10. the output of the counter 3 is connected to the counting input of the counter 5, the overflow outputs of the counters 3.5 are connected to the inputs of the multi-input circuit “AND -NE "7, the output of which is connected to the synchronizing input of the control unit 10, as well as to the counting input of the channel switching trigger 9, the outputs of which are connected to the corresponding channel switching inputs of the control unit 10. The installation input is in" 1 ". The window 8 trigger is connected to the output of the AND-NOT circuit 7, and the reset input “0” is connected to the overflow output of the counter 6, the output of the trigger 8 is connected to the input of the window of the control unit 10. This input, together with the channel inputs from the trigger 9, distributes the counting pulses of the frequency f _c on the count inputs on “plus and minus” for the first channel on the counters 12, 12 'and for the second channel on the counters 13, 13 "respectively. The outputs of the counters of the first 12, 12' and the second channel 13, 13 'are connected through multiplexers 14, 14 'to the inputs of the output FPGA 15 chip, and the control inputs of the multiplexers 14, 14' are connected to the outputs I will give a trigger for switching channels 9. The outputs of the counter 6 are connected to the inputs of the register 11, the control input of which is connected to the output of the control unit 10, which inverts the signal from the microcircuit 7. The outputs from the register 11 are connected to the inputs of the FPGA 15 and then to the indication output, or directly to output in sensor mode.

, где K_м - коэффициент передачи гироскопа - магнетрона, ω - измеряемая угловая скорость подвижного объекта (ПО). Иначе формула записывается в виде f=f₀+Δf,

При этом частота эталонная f₀ может лежать в интервале частот (0.1-10), ГГц.The digital frequency meter operates as follows. When connecting sources of supply voltage, when starting the input f and counting f _c signals, the following processes occur in the system. Using group 3 of counters 4, 4 ', the signal of the counting frequency is divided by an integer at which the reference signal of frequency f _{0 is} obtained, which is equal to the initial frequency of the input signal: f ₀ = f (0) = f. The frequency of the input signal f varies due to the properties of its carrier. For example, if the input source of the gyroscope is the magnetron [3], then its frequency changes due to the angular velocity of the moving object

, where K _m is the transfer coefficient of the gyroscope - magnetron, ω is the measured angular velocity of the moving object (PO). Otherwise, the formula is written in the form f = f ₀ + Δf,

In this case, the reference frequency f ₀ may lie in the frequency range (0.1-10), GHz.

. С помощью триггера 8, схемы 7 и блока логики 10 измерительный интервал в определенные отрезки времени ΔТ₀ ^* заполняется счетными импульсами f_c. Данное решение поясняется графиками сигналов фиг. 2 и формулами (алгоритмами).It is easy to see that when the sign of the angular velocity of the software changes, the sign of the increment of the input frequency changes, which should be recorded by a digital frequency meter. Using group 5 of n counters, f _{0 is} divided into frequency intervals f ^* , and the signal f ^{* is} converted to the pulse period of the measuring interval

. Using trigger 8, circuit 7 and logic block 10, the measurement interval at certain time intervals ΔТ ₀ ^{* is} filled with counting pulses f _c . This solution is illustrated by the waveforms of the signals of FIG. 2 and formulas (algorithms).

In addition to the given frequencies f ₀ and f, in FIG. 2 shows a graph of the signal of the counting frequency f _c , while

For the example of FIG. 2, for one clock cycle of the reference frequency f ₀ there are four clock cycles of the counted frequency f _c , which gives the accuracy of digitizing the difference frequency the same as for the reference frequency f _0.

For a conventional circuit, the period T ₀ ^* is formed by a single counter from the reference frequency f _{0 in a} natural way from the overflow signal, which rewrites the data from the counter 6 of the input frequency f to register 11 with a rising edge, and transfers the group of counters to the initial zero state on the falling edge.

Using the register allows you to avoid "blinking" of the output code for the whole part of the frequency f, allows you to access this information continuously, which is an advantage for using the device as a sensor, and greatly simplifies the correction for the fractional part in the device 15, which can be implemented here on the FPGA instead of a microcontroller, as in the prototype.

For the proposed circuit, the input frequency counter is reset at the trailing edge of the pulse of the same frequency f, subject to a preliminary reset of the reference frequency counter. The difference of these reset times gives the first component of the LT quantization _. The difference for the overflow times of both counters forms the second component of the quantization ΔТ ₂ .

The indicated time parameters are related by the ratio:

Element 5 (a group of counters) from the reference frequency f ₀ forms the repetition frequency of the measurement intervals f ^* and must contain the necessary number of cascades n ₀

For the given implementation of the circuit, the above algorithm (5) simplifies the logic of counting, namely, with counting pulses f _{c it} is measured continuously, after each interval with frequency f ^* , the accumulated phase for the difference frequency Δf, which changes by ΔT ₀ ^* with each interval, proportional to the difference frequency ff ₀ . Since in our case Δf> 0, the excess of the accumulated phase will decrease with each interval. To fix this change, two measurement channels are used from two-stage reversible counters 12, 12 'and 13, 13' on which, in the first interval after a reset, an “addition” count occurs and the result displays the current accumulated phase, and in the next interval, an “subtract” count occurs ", The result is a phase difference or an increment for one interval ΔT ₀ ^* . After that, the cycle can be repeated indefinitely. The count occurs within the time for zero readings of counters 5 and 6, which is ensured by their synchronization. The counting time is allocated using trigger 8, set to “1” by a reset sign from counter 5, and reset to “0” by a reset sign from counter 6. State “1” of the trigger allows pulse counting f _c at the output counters 12 ... 13 'and the sign counting is determined by the state of trigger 9, the counting input of which at the beginning of each interval receives a pulse that translates it into the opposite state.

First, the operation of one channel is described, which gives the definition of the difference phase and frequency on only one interval of two. Exactly the same channel, on the counters 13, 13 'controlled by the opposite output of trigger 9, gives a measurement on the interval of fixing the accumulated phase for the second channel, and the measurement process becomes continuous, since the outputs of the counters 12, 12' and their duplicates 13, 13 'are combined through multiplexers 14, 14 "with control from the same trigger.

All these algorithms are implemented by logic on typical elements of the “AND-NOT” control circuit 10. A continuous decrease in the accumulated phase leads to a transition through zero, but at the same time there is a one-time additional delay in the other state of counter 6, and the accumulated phase is adjusted to the maximum. This happens at the moment of subtraction, the counter gives a negative result, the sign of which blocks the change in the readings at the output. For the next interval, this score will be added, and it will give the correct result at the end of the interval. And then everything is restored.

Thus, an almost continuous measurement of the low-frequency difference ω = 2πΔf takes place with a sufficiently frequent measurement, the interval of which is determined by the counting time of whole units for the fundamental frequency f. At the same time, the integer number of pulses of the input signal of the input signal for the measurement period is determined at the output of the FPGA and the digital frequency meter as a whole.

Sources of information

1. Goncharenko A.M. et al. Digital frequency meter. RF patent No. 2210785. IPC GO1R 23/02. 2003, Bull. Number 23.

2. Goncharenko A.M., Zhmud V.A. Pat. RF №2278390. Digital frequency meter. IPC GO1R 23/10. 2006, Bull. Number 17.

3. Plotnikov P.K. A single resonator gyroscope is a magnetron. RF patent for utility model No. 163266. IPC G01C 19/00. 2016, Bull. Number 19

Claims (1)

A digital frequency meter, which includes an input signal receiving port, a receiving port for calculating highly stable microwave pulses, three groups of meters with a register at the output of the measuring counter, a trigger connected to a synchronization circuit, characterized in that an additional trigger for determining the measuring interval is included in the digital frequency meter and a trigger for switching two channels made in the form of introduced two groups of reversible counters from the senior and lower digits, two multi the lexor of the senior and junior digits, designed to change the display of output information from the channels, a block of logical elements has been introduced, designed to control the generation of the measuring interval, determine the frequency difference of the input and reference signals and switch channels and count signs of the difference of these frequencies, a memory register of the integer part of the input signal, as well as the corrector of the fractional part in the form of its divider by the measured frequency mantissa, made on the basis of a programmable integrated log chip in this case, the outputs of the first multi-input circuit “and - not”, the outputs of the trigger for switching the first channel to the second, the outputs of the ports for receiving input and counting signals, the outputs of the block of logic elements, the inputs of n input counters are connected to the corresponding inputs of the block of logic elements, register control inputs for storing the integer value of the input signal, inputs of the low-order counters of the first and second channels, and the outputs of two high-order counters are connected to the inputs of the multiplexer switching the outputs of the senior bit, and the outputs of two counters of the least significant bits are connected to the inputs of the multiplexer for switching the outputs of the least significant bit, the outputs of the register and the block of multiplexers are connected to the corresponding inputs of the microcircuit programmable logic integrated structure, the first output of which is the difference frequency between the input and reference signals, and the second output it and the digital frequency meter as a whole - an integer number of input pulses of the input signal for the measurement period.

Images