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KR970060458A - Multilayer film for circuit board formation and multi-layer circuit board and package for semiconductor device using same - Google Patents

Multilayer film for circuit board formation and multi-layer circuit board and package for semiconductor device using same Download PDF

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Publication number
KR970060458A
KR970060458A KR1019970000993A KR19970000993A KR970060458A KR 970060458 A KR970060458 A KR 970060458A KR 1019970000993 A KR1019970000993 A KR 1019970000993A KR 19970000993 A KR19970000993 A KR 19970000993A KR 970060458 A KR970060458 A KR 970060458A
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South Korea
Prior art keywords
circuit board
layer
multilayer film
multilayer
vias
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Application number
KR1019970000993A
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Korean (ko)
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KR100257926B1 (en
Inventor
토시까즈 타께노우찌
Original Assignee
모기 쥰이찌
신꼬오덴기 고오교오 가부시끼가이샤
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Publication of KR970060458A publication Critical patent/KR970060458A/en
Application granted granted Critical
Publication of KR100257926B1 publication Critical patent/KR100257926B1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/49105—Connecting at different heights
    • H01L2224/49109—Connecting at different heights outside the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

본 발명은 간단한 공정으로 제조가 가능한 다층회로기판 및 이것에 사용하기 적합한 회로기판형성용 다층필름을 제공한다. 해결수단은 도체층(16)이 소요 배선패턴(16a)으로 형성되고, 열경화성수지층(12) 및 그 양면에 설비한 접착층(14)에 비아홀(18)이 형성되고, 배선패턴(16a)에 접속하는 도전성물질이 비아홀(18)에 충전된 비아(20)를 갖는 회로기판형성용다층필름(10)이 도전성 물질이 비아홀에 충전되어 형성된 비아(20)를 갖는 코어기판(24)의 한면 또는 양면에 다층필름(10) 표면의 접착층(14)을 거쳐서 소요매수 적층되어 열압착되고, 또 다층필름(10) 및 코어기판(24)에 설비한 비아(20)를 거쳐서 배선패턴(16a) 사이가 전기적으로 접속되어 있는 것을 특징으로 한다.The present invention provides a multilayer circuit board which can be manufactured in a simple process and a multilayer film for forming a circuit board suitable for use therein. The solution means is that the conductor layer 16 is formed of the required wiring pattern 16a, the via hole 18 is formed in the thermosetting resin layer 12 and the adhesive layer 14 provided on both sides thereof, and the wiring pattern 16a is formed. One side of the core substrate 24 having the vias 20 formed by filling the via holes in the circuit board forming multilayer film 10 having the vias 20 filled with the conductive materials to be connected to the via holes 18 or The required number of layers are laminated on both sides via the adhesive layer 14 on the surface of the multilayer film 10 and thermally compressed, and between the wiring patterns 16a through the vias 20 provided on the multilayer film 10 and the core substrate 24. Is electrically connected.

Description

회로기판형성용다층필름 및 이를 사용한 다층회로기판 및 반도체장치용패키지Multilayer film for circuit board formation and multi-layer circuit board and package for semiconductor device using same

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제5도는 다층회로기판의 단면도.5 is a cross-sectional view of a multilayer circuit board.

Claims (13)

열경화성수지층의 양면에 열가소성수지로 되는 접착층이 형성되고, 상기 접착층의 한쪽 접착층상에 도체층이 형성되는 것이 특징인 회로기판형성용 다층필름.An adhesive layer made of thermoplastic resin is formed on both sides of the thermosetting resin layer, and a conductor layer is formed on one adhesive layer of the adhesive layer. 제1항에 있어서, 상기 열경화성수지층이 열경화성(비열가소성)의 폴리이미드수지로 되고, 상기 접착층이 열가소성의 폴리이미드수지로 되는 것이 특징인 회로기판형성용다층필름.2. The multilayer film for forming a circuit board according to claim 1, wherein the thermosetting resin layer is a thermosetting (non-thermoplastic) polyimide resin, and the adhesive layer is a thermoplastic polyimide resin. 제1항 또는 제2항에 있어서, 상기 도체층이, 스퍼터링층과 스퍼터링층상에 형성된 도금층으로 되는 것이 특징인 회로기판형성용다층필름.The multilayer film for forming a circuit board according to claim 1 or 2, wherein the conductor layer is a plating layer formed on the sputtering layer and the sputtering layer. 제3항에 있어서, 상기 도체층의 도금층이 동인 것이 특징인 회로기판형성용다층필름.4. The multilayer film for forming a circuit board according to claim 3, wherein the plating layer of the conductor layer is copper. 도체층이 소요의 배선패턴으로 형성되고, 열경화성수지층 및 그 양면에 구비한 접착층에 비아홀이 형성되고, 상기 배선패턴에 접속하는 도전성물질이 비아홀에 충전된 비아를 갖는 청구항 1, 2 또는 3 기재의 회로기판 형성용다층 필름이, 상기 다층필름표면의 접착층을 거쳐서 복수매적층되어 열압착 되고, 또 상기 비아를 거쳐서 상기 배선패턴 사이가 전기적으로 접속된 것이 특징인 다층회로기판.Claim 1, 2, or 3, wherein the conductor layer is formed of a desired wiring pattern, a via hole is formed in the thermosetting resin layer and the adhesive layers provided on both sides thereof, and the conductive material connected to the wiring pattern has vias filled in the via holes. And a plurality of multilayer films for forming a circuit board are laminated and thermally compressed through an adhesive layer on the surface of the multilayer film, and electrically connected between the wiring patterns via the vias. 도체층이 소요의 배선패턴으로 형성되고, 열경화성수지층 및 그 양면에 설비한 접착층에 비아홀이 형성되고, 상기 배선패턴에 접속하는 도전성물질이 비아홀에 충전된 비아를 갖는 청구항 1, 2 또는 3 기재의 회로기판 형성용다층 필름이, 도전성물질이 비아홀에 충전되어 형성된 비아를 갖는 코어기판의 한면 또는 양면에 상기 다층필름표면의 접착층을 거쳐서 소요매수 적층되어 열압착되고, 또 상기 다층필름 및 코어기판에 구비한 비아를 거쳐서 상기 배선패턴 사이가 전기적으로 접속된 것이 특징인 다층회로기판.Claim 1, 2, or 3, wherein the conductor layer is formed of a desired wiring pattern, a via hole is formed in the thermosetting resin layer and the adhesive layers provided on both sides thereof, and the conductive material connected to the wiring pattern has vias filled in the via holes. The multilayer film for forming a circuit board is laminated on the one or both surfaces of a core substrate having vias filled with a conductive material in a via hole through an adhesive layer on the surface of the multilayer film, and thermally compressed. A multilayer circuit board, wherein the wiring patterns are electrically connected to each other via vias provided in the vias. 제6항에 있어서, 상기 도전성물질이 동페이스트를 사용하여 형성된 것이 특징인 다층회로기판.The multilayer circuit board of claim 6, wherein the conductive material is formed using a copper paste. 제6항 또는 제7항에 있어서, 상기 코어기판이 세라믹기판인 것이 특징인 다층회로기판.8. The multilayer circuit board of claim 6 or 7, wherein the core board is a ceramic board. 제6항 또는 제7항에 있어서, 상기 코어기판이 수지기판인 것이 특징인 다층회로기판.The multilayer circuit board according to claim 6 or 7, wherein the core substrate is a resin substrate. 제6항 내지 제9항 중 어느 한 항에 있어서, 상기 코어기판이 표면 또는 그 내부에, 상기 다층필름이 배선패턴에 비아를 거쳐서 전기적으로 접속하는 배선패턴이 형성된 것이 특징인 다층회로기판.The multilayer circuit board according to any one of claims 6 to 9, wherein a wiring pattern is formed on the surface of or inside the core board to electrically connect the multilayer film to the wiring pattern via vias. 청구항 6, 7, 8, 9 또는 10 기재의 다층회로기판의 한쪽 면에 상기 배선패턴과 전기적으로 접속하는 외부접속단자가 형성되고, 다른쪽 면에 반도체소자의 탑재부가 형성된 것이 특징인 반도체장치용패키지.An external connection terminal for electrically connecting the wiring pattern is formed on one side of the multilayer circuit board according to claim 6, 7, 8, 9 or 10, and the mounting portion of the semiconductor element is formed on the other side. package. 제11항에 있어서, 상기 코어기판에 적층된 상기 회로기판형성용다층 필름이 틀상으로 형성됨으로서, 상기 반도체소자의 탑재부가 캐비티로 형성된 것이 특징인 반도체장치용패키지.12. The package according to claim 11, wherein the circuit board forming multilayer film laminated on the core board is formed in a frame shape so that the mounting portion of the semiconductor element is formed as a cavity. 제11항 또는 제12항에 있어서, 상기 외부접속단자가 땜납범프인 것이 특징인 반도체장치용패키지.The package for semiconductor device according to claim 11 or 12, wherein the external connection terminal is a solder bump. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019970000993A 1996-01-19 1997-01-15 Multi-layer film for circuit board and multi-layer circuit board using the same and pakage for semiconductor device KR100257926B1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP7594 1996-01-19
JP007594 1996-01-19
JP8007594A JPH09199635A (en) 1996-01-19 1996-01-19 Multilayer film for forming circuit substrate, multilayer circuit substrate using it, and package for semiconductor device

Publications (2)

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KR970060458A true KR970060458A (en) 1997-08-12
KR100257926B1 KR100257926B1 (en) 2000-06-01

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TW478089B (en) 1999-10-29 2002-03-01 Hitachi Ltd Semiconductor device and the manufacturing method thereof
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JP3407737B2 (en) * 2000-12-14 2003-05-19 株式会社デンソー Multilayer substrate manufacturing method and multilayer substrate formed by the manufacturing method
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JP3840921B2 (en) 2001-06-13 2006-11-01 株式会社デンソー Printed circuit board and manufacturing method thereof
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JP2004335934A (en) * 2003-05-12 2004-11-25 North:Kk Flexible circuit board and its producing process, flexible multilaler wiring circuit board and its producing process
KR100568767B1 (en) * 2003-06-23 2006-04-07 앰코 테크놀로지 코리아 주식회사 Delamination-less Multi-Layer Film Adhesive
JP4265607B2 (en) 2004-01-27 2009-05-20 株式会社村田製作所 Laminated electronic component and mounting structure of laminated electronic component
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JP5926898B2 (en) * 2011-06-24 2016-05-25 日本特殊陶業株式会社 Wiring board manufacturing method
JP6250309B2 (en) * 2013-06-14 2017-12-20 日本特殊陶業株式会社 Manufacturing method of multilayer wiring board
JP6324669B2 (en) * 2013-06-14 2018-05-16 日本特殊陶業株式会社 Multilayer wiring board and manufacturing method thereof
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Also Published As

Publication number Publication date
JPH09199635A (en) 1997-07-31
KR100257926B1 (en) 2000-06-01

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