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KR970008512A - Chip size semiconductor package and manufacturing method thereof - Google Patents

Chip size semiconductor package and manufacturing method thereof Download PDF

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Publication number
KR970008512A
KR970008512A KR1019950023104A KR19950023104A KR970008512A KR 970008512 A KR970008512 A KR 970008512A KR 1019950023104 A KR1019950023104 A KR 1019950023104A KR 19950023104 A KR19950023104 A KR 19950023104A KR 970008512 A KR970008512 A KR 970008512A
Authority
KR
South Korea
Prior art keywords
lead
semiconductor chip
tape
sides
chip
Prior art date
Application number
KR1019950023104A
Other languages
Korean (ko)
Other versions
KR0157892B1 (en
Inventor
조재원
Original Assignee
문정환
Lg 반도체주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 문정환, Lg 반도체주식회사 filed Critical 문정환
Priority to KR1019950023104A priority Critical patent/KR0157892B1/en
Publication of KR970008512A publication Critical patent/KR970008512A/en
Application granted granted Critical
Publication of KR0157892B1 publication Critical patent/KR0157892B1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/4826—Connecting between the body and an opposite side of the item with respect to the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73215—Layer and wire connectors

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

본 발명은 칩 사이즈 반도체 패키지 및 그 제조방법에 관한 것으로, 종래에는 반도체 칩의 칩패드에 금범프를 부착하고그 금범프가 외부 단자가 되어 피시비 기판의 패드 단자에 실장되는 것으로 금범프의 부착 및 피시비 기판에 실장하는 기술이 복잡하고 까다롭기 때문에 생산성이 저하되는 문제점이 있었다. 본 발명은 피시비 기판의 패드 단자에 단위 패키지의 상면에 노출된 아웃 리드를 솔더 페이스트를 이용하여 실장 시켜서, 종래와 같이 제조 방법이 복잡하고 까다로운 금범프를 형성하는 공정을 배제함으로써 공정의 단순화에 따른 생상성이 향상되는 효과가 있는 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a chip size semiconductor package and a method for manufacturing the same. In the related art, a gold bump is attached to a chip pad of a semiconductor chip, and the gold bump is an external terminal and is mounted on a pad terminal of a PCB. Since the technology to mount on the PCB substrate is complicated and difficult, there is a problem that the productivity is lowered. The present invention mounts the out lead exposed to the upper surface of the unit package to the pad terminal of the PCB substrate by using solder paste, thereby eliminating the process of forming a complicated and difficult gold bump as in the prior art, thereby simplifying the process. It has the effect of improving productivity.

Description

칩 사이즈 반도체 패키지 및 그 제조방법Chip size semiconductor package and manufacturing method thereof

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명 칩 사이즈 반도체 패키지가 피시비 기판에 실장된 상태를 보인 종단면도, 제4도는 본 발명 칩 사이즈 반도체 패키지의 리드프레임에 칩을 부착한 상태를 보인 사시도.2 is a longitudinal sectional view showing a state in which a chip size semiconductor package of the present invention is mounted on a PCB substrate, and FIG. 4 is a perspective view showing a state in which a chip is attached to a lead frame of a chip size semiconductor package of the present invention.

Claims (2)

양면 테이프인 베이스 테이프와, 그 베이스 테이프의 상면 양측에 부착되어 있는 지지 테이프와 그 지지테이프의 상부 양측에 나열 부착되는 수개의 리드와, 상기 베이스 테이프의 하부에 부착되는 반도체 칩과, 상기 리드의인너 리드와 반도체 칩의 칩패드를 연결하는 금속와이어와, 상기 금속 와이어와 인너 리드를 포함하는 일정면적을 코팅한내부 코팅부와, 상기 리드의 아웃 리드와 피시비 기판의 패드 단자를 연결하는 솔더 페이스트 및 상기 아웃 리드와 솔더페이스트를 포함하는 반도체 칩의 측부를 코팅한 외부 코팅부로 구성된 것을 특징으로 하는 칩 사이즈 반도체 패키지.A base tape that is a double-sided tape, a support tape attached to both sides of an upper surface of the base tape, several leads arranged on both sides of an upper portion of the support tape, a semiconductor chip attached to a lower portion of the base tape, and A metal wire connecting the inner lead and the chip pad of the semiconductor chip, an inner coating part coated with a predetermined area including the metal wire and the inner lead, and a solder paste connecting the out lead of the lead and the pad terminal of the PCB. And an outer coating part coated on a side of the semiconductor chip including the out lead and the solder paste. 베이스 테이프의 상면 양측에 지지 테이프를 부착하고 그 지지 테이프의 상부 양측에 수개의 리드를 부착하여 리드 프레임을 형성하는 공정을 수행하는 단계와, 상기 베이스 테이프의 하부에 반도체 칩을 부착하는 공정을 수행하는 단계와, 상기 리드의 인너 리드와 반도체 칩의 칩패드를 금속 와이어로 연결하는 와이어 본딩 공정을 수행하는 단계와, 상기 인너 리드와 금속 와이어를 포함하는 일정부분을 코팅하는 내부 코팅부 형성공정을 수행하는 단계와, 상기 베이스 테이프의 하부에 부착 되어 있는 반도체 칩의 양측 소정부위를 절단하여 개개의 단위 패키지로 구분하는 절단공정을수행하는 단계와, 상기 리드의 아웃 리드와 피시비 기판의 패드 단자를 솔더 페이스트로 각각 부착하는 리플로우 공정을수행하는 단계와, 상기 아웃 리드와 솔더 페이스트를 포함하는 반도체 칩의 측부를 코팅액으로 코팅하는 외부 코팅부 형성 공정을 수행하는 단계의 순서로 제조되는 것을 특징으로 하는 칩 사이즈 반도체 패키지의 제조방법.Attaching the supporting tape to both sides of the upper surface of the base tape and attaching several leads to both sides of the upper portion of the supporting tape to form a lead frame; and attaching a semiconductor chip to the lower portion of the base tape. And a wire bonding process of connecting the inner lead of the lead and the chip pad of the semiconductor chip with a metal wire, and an internal coating part forming process of coating a portion including the inner lead and the metal wire. Performing a cutting step of cutting the predetermined portions of both sides of the semiconductor chip attached to the lower portion of the base tape and dividing them into individual unit packages, and separating the lead leads and pad terminals of the PCB substrate. Performing a reflow process of attaching each of the solder pastes; Method of manufacturing a chip size semiconductor packages, characterized in that the side is made of a semiconductor chip that includes a host in the order of performing the outer coating portion forming step of coating a coating liquid. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950023104A 1995-07-29 1995-07-29 Chip size semiconductor package and method of making the same KR0157892B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950023104A KR0157892B1 (en) 1995-07-29 1995-07-29 Chip size semiconductor package and method of making the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950023104A KR0157892B1 (en) 1995-07-29 1995-07-29 Chip size semiconductor package and method of making the same

Publications (2)

Publication Number Publication Date
KR970008512A true KR970008512A (en) 1997-02-24
KR0157892B1 KR0157892B1 (en) 1998-12-01

Family

ID=19422205

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950023104A KR0157892B1 (en) 1995-07-29 1995-07-29 Chip size semiconductor package and method of making the same

Country Status (1)

Country Link
KR (1) KR0157892B1 (en)

Also Published As

Publication number Publication date
KR0157892B1 (en) 1998-12-01

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