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KR950015650A - 반도체 장치 제조방법 - Google Patents

반도체 장치 제조방법

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Publication number
KR950015650A
KR950015650A KR1019940031261A KR19940031261A KR950015650A KR 950015650 A KR950015650 A KR 950015650A KR 1019940031261 A KR1019940031261 A KR 1019940031261A KR 19940031261 A KR19940031261 A KR 19940031261A KR 950015650 A KR950015650 A KR 950015650A
Authority
KR
South Korea
Prior art keywords
gas
film
forming
semiconductor device
metallic film
Prior art date
Application number
KR1019940031261A
Other languages
English (en)
Other versions
KR0185227B1 (ko
Inventor
가즈미 사이또
Original Assignee
가네꼬 히사시
닛뽕 덴끼 가부시끼 가이샤
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 가네꼬 히사시, 닛뽕 덴끼 가부시끼 가이샤 filed Critical 가네꼬 히사시
Publication of KR950015650A publication Critical patent/KR950015650A/ko
Application granted granted Critical
Publication of KR0185227B1 publication Critical patent/KR0185227B1/ko

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only

Landscapes

  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • General Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Chemical & Material Sciences (AREA)
  • Drying Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

본 발명은 측면 에칭없이 용융점이 높은 금속을 포함하는 금속성 필름을 에칭하여 선 제조 방법을 제공한다. SF6및 N2를 포함하는 혼합 가스에 의하여 텅스텐 필름(4c)이 에칭될때, 질화 텅스텐 필름(14)이 에칭되는 텅스텐 필름(4c)의 측벽상에 형성되고, 상기 질화 텅스텐 필름(14)은 에칭을 막는 역활을 한다. 선택된 도면은 제5도이다.

Description

반도체 장치 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제2도는 본 발명의 바람직한 제1 실시예를 설명하는 반도체 장치의 단면도,
제3A-3D도는 본 발명의 바람직한 제1 실시예를 설명하는 반도체 장치의 단면도,
제4도는 본 발명의 바람직한 제1 실시예의 텅스텐 필름 에칭율을 나타내는 그래프.

Claims (2)

  1. 반도체 장치의 제조 방법에 있어서, 반도체 표면상에 절연체 필름을 형성하는 단계와, 상기 절연체 필름의 표면상에 주요 구성 요소로서 용융점이 높은 금속을 포함하는 금속성 필름을 형성하고, 상기 금속성 필름의 표면상에 소정의 패턴으로 레지스트 필름을 형성하는 단계와, 상기 레지스트 필름을 마이크로 사용하여, 염화물 가스 및 질소 또는 암모니아가스를 포함하는 혼합가스로 상기 금속성 필름을 에칭하는 단계를 구비함을 특징으로 하는 반도체 장치의 제조 방법.
  2. 반도체 장치의 제조 방법에 있어서, 반도체 표면상에 절연체 필름을 형성하는 단계와, 상기 절연체 필름의 표면상에 주요 구성 요소로서 용융점이 높은 금속을 포함하는 금속성 필름을 형성하고, 상기 금속성 필름의 표면상에 소정의 패턴으로 레지스트 필름을 형성하는 단계와, 상기 레지스트 필름을 마이크로 사용하여, 소정의 유속을 갖는 제1 가스 및 제2 가스 즉, 염화물 가스로 구성된 제1 가스와, 질소 또는 암모니아 가스로 구성된 제2 가스를 포함하는 혼합 가스로 상기 금속성 필름을 에칭하는 단계와, 그리고 상기 소정의 유속과 비교하여 상기 제1 및 제2 가스의 유속이 증가된, 상기 제1 가스 및 제2 가스를 포함하는 혼합 가스로 잔존하는 금속을 과에칭하는 단계를 구비함을 특징으로 하는 반도체 장치 제조 방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019940031261A 1993-11-26 1994-11-25 반도체 장치 제조 방법 KR0185227B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP5296495A JPH07147271A (ja) 1993-11-26 1993-11-26 半導体装置の製造方法
JP93-296495 1993-11-26

Publications (2)

Publication Number Publication Date
KR950015650A true KR950015650A (ko) 1995-06-17
KR0185227B1 KR0185227B1 (ko) 1999-04-15

Family

ID=17834296

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019940031261A KR0185227B1 (ko) 1993-11-26 1994-11-25 반도체 장치 제조 방법

Country Status (3)

Country Link
US (1) US5753533A (ko)
JP (1) JPH07147271A (ko)
KR (1) KR0185227B1 (ko)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2924723B2 (ja) * 1995-08-16 1999-07-26 日本電気株式会社 ドライエッチング方法
JP3123914B2 (ja) * 1995-12-27 2001-01-15 日本電気株式会社 半導体装置の製造方法
EP0849806A3 (en) * 1996-12-19 1999-08-25 Texas Instruments Incorporated Improvements in or relating to semiconductor devices having tungsten nitride sidewalls
US6797188B1 (en) 1997-11-12 2004-09-28 Meihua Shen Self-cleaning process for etching silicon-containing material
US6322714B1 (en) 1997-11-12 2001-11-27 Applied Materials Inc. Process for etching silicon-containing material on substrates
US6136211A (en) * 1997-11-12 2000-10-24 Applied Materials, Inc. Self-cleaning etch process
US6872322B1 (en) 1997-11-12 2005-03-29 Applied Materials, Inc. Multiple stage process for cleaning process chambers
US6037263A (en) * 1998-11-05 2000-03-14 Vanguard International Semiconductor Corporation Plasma enhanced CVD deposition of tungsten and tungsten compounds
US6613682B1 (en) 1999-10-21 2003-09-02 Applied Materials Inc. Method for in situ removal of a dielectric antireflective coating during a gate etch process
US6527968B1 (en) * 2000-03-27 2003-03-04 Applied Materials Inc. Two-stage self-cleaning silicon etch process
US6440870B1 (en) * 2000-07-12 2002-08-27 Applied Materials, Inc. Method of etching tungsten or tungsten nitride electrode gates in semiconductor structures
US6905800B1 (en) 2000-11-21 2005-06-14 Stephen Yuen Etching a substrate in a process zone
US6852242B2 (en) 2001-02-23 2005-02-08 Zhi-Wen Sun Cleaning of multicompositional etchant residues
JP3872069B2 (ja) * 2004-04-07 2007-01-24 エルピーダメモリ株式会社 半導体装置の製造方法
US8118946B2 (en) * 2007-11-30 2012-02-21 Wesley George Lau Cleaning process residues from substrate processing chamber components

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6065533A (ja) * 1983-09-21 1985-04-15 Hitachi Ltd ドライエッチング方法
JPS6148924A (ja) * 1984-08-15 1986-03-10 Nippon Telegr & Teleph Corp <Ntt> 高融点金属のドライエツチング法
JP2754578B2 (ja) * 1988-07-25 1998-05-20 ソニー株式会社 エッチング方法
US4948462A (en) * 1989-10-20 1990-08-14 Applied Materials, Inc. Tungsten etch process with high selectivity to photoresist
JPH03201529A (ja) * 1989-12-28 1991-09-03 Sharp Corp 半導体装置の製造方法
US5024722A (en) * 1990-06-12 1991-06-18 Micron Technology, Inc. Process for fabricating conductors used for integrated circuit connections and the like
US5273609A (en) * 1990-09-12 1993-12-28 Texas Instruments Incorporated Method and apparatus for time-division plasma chopping in a multi-channel plasma processing equipment
FR2680276B1 (fr) * 1991-08-05 1997-04-25 Matra Mhs Procede de controle du profil de gravure d'une couche d'un circuit integre.
US5376585A (en) * 1992-09-25 1994-12-27 Texas Instruments Incorporated Method for forming titanium tungsten local interconnect for integrated circuits
DE4300808C1 (de) * 1993-01-14 1994-03-17 Siemens Ag Verfahren zur Herstellung eines Vielschichtkondensators

Also Published As

Publication number Publication date
JPH07147271A (ja) 1995-06-06
KR0185227B1 (ko) 1999-04-15
US5753533A (en) 1998-05-19

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