KR930004231B1 - Channel control device for electrophonic instrument - Google Patents

Abstract

The apparatus equally disperses process-delay time of each channel equivalent to each keyboard to prevent the delay of sound generation when multiple keyboards are pressed simultaneously and frequently. It includes an overlapped value calculator (1) for calculating the process-delay time of each channel, a priority discriminator (2) for selecting the channel of the highest priority, a latching section (3) for latching the signal from the priority discriminator (2), and a timing controller (4) for supplying timing control signal to the priority discriminator (2) and the overlapped value calculator (1).

Description

Channel controller for electronic instruments

1 is a block diagram of a conventional time division processing apparatus.

2 is a block diagram of an electronic musical instrument sound source according to FIG.

3 is a circuit diagram of a conventional channel control apparatus.

4 is a timing diagram of FIG.

5 is a circuit diagram of a channel control apparatus of the present invention.

6 is a block diagram of the present invention weight calculator.

7 is a circuit diagram of a priority discriminator of the present invention.

8 is a block diagram of a comparative selector of the present invention.

9 is a timing diagram according to the present invention.

* Explanation of symbols for main parts of the drawings

1: weight calculator 2: priority discriminator

3, 6: latch 4: timing controller

5: M divider and counter 7-10: R / S flip-flop

11-14: Andgate 15: Oagate

16-20: Selector 21: Request Memory

22: comparator binary tree 23: comparator

24, 25: multiplexer

The present invention relates to an electronic musical instrument channel control apparatus capable of time-divisionally processing a plurality of channels in an electronic musical instrument sound source device. The service request of the channel is adequately handled to delay the delay.

In the conventional time sharing processing apparatus, as shown in FIG. 1, N channel request sources 31 are connected to the channel control device 32, and are shared by the channel control device 32 according to the channel request source inputted thereto. It is configured to control the device 33.

2 shows an example in which the time division processing device is applied to a sound source device for electronic musical instruments. The keyboard 34 and the keyboard interface 35 correspond to the channel request source 31 of FIG. 36 corresponds to the common apparatus 33 of FIG. 1, and the channel control apparatus 32 is comprised so that the sound generating circuit 36 may be time-divisionally allocated to each pressed key between them. 3 shows a conventional channel control apparatus. The channel having the highest priority is connected to the request storage unit 37 to which a device use request signal is input, and the data inputted by being connected to the output side of the request memory unit 37. Selects a priority encoder 38 for outputting the channel as a binary number, a latch 39 for receiving the output of the priority encoder 38 and outputting the output to a channel address, and the priority encoder ( 38) and a controller 40 for receiving the output of the latch 39 and outputting a control signal to the request memory 37 and the latch 39.

Hereinafter, the operation of the channel control apparatus as shown in FIG. 3 will be described with reference to the timing diagram of FIG.

First, the request memory unit 37 is configured as an R / S flip-flop, and when N channel request signals SR ₀ -SR _N-1 are input to the set input terminals S ₀ -S _N-1 , the memory is stored. do. At this time, the controller 40 receives the channel request and generates a control signal RES ₀ -RES _N-1 when the corresponding channel address is output from the latch 39 to reset the input terminal of the request memory unit 37 ( R ₀ -R _N-1 ).

Then, the request storage unit 37 inputs outputs Q ₀ -Q _N-1 to the priority encoder 38 according to the requested result, and the priority encoder 38 has the highest priority based on the input data. Selects a channel with a high value and outputs the channel as a binary number. When the latch 39 receives the binary number and a latch enable control signal LCK is input from the controller 40, the channel 40 outputs a channel address. .

The controller 40 also controls the control signals RES _{0 to} RES _N-1 LCK based on the signal E input from the priority encoder 38 and the channel address input from the latch 39. output sikineunde the priority encoder 38, the signal (E) which is input from the first input (D ₀ -D _N-1) of the priority encoder 38, all become "0" when low state input (D ₀ - D _N-1 ) goes high when any one of them is “1”.

4 shows two channel request signals SR ₀ -SR _N-1 (for example, SR ₀ -SR ₁ ), if two keys are pressed at the moment "A", the channel request signal SR ₀ ) And (SR ₁ ) become active, the output Q ₀ (Q ₁ ) from the request memory unit 37 is all high (" 1 " state).

In addition, the priority encoder 38 outputs all of the output values as "0" when the priority is highest (D ₀ ) and the lowest (D _N-1 ), and at the same time, the output (E) Goes high.

Therefore, the controller 40 sends the control signal LCK to the latch 39 as the high state is input, causing the latch 39 to have a value of the channel address "0" and also the control signal RES ₀ . Activate to clear the request memory. At this time, if the processing period (time in which one channel occupies the common device 33 in FIG. 1) allocated to one channel is M period, after the M period after the first control signal LCK is output from the controller 40, The second control signal LCK is issued to cause the latch 39 to output new data as the channel address.

In this case, since the memory corresponding to the activation of the channel request signal SR ₀ is released when the control signal RES ₀ is activated, the output Q ₀ (Q ₁ ) of the request memory unit 37 is " 0 " Since it becomes "1", the channel address becomes "1".

On the other hand, when the request signal as at time "A" is input at time "B", the same processing operation as above is repeated.

However, in the prior art as described above, since the priority is determined for each channel and the priority cannot be changed, for example, when a plurality of channels frequently send request signals at the same time, a channel having a low priority is requested to use. The difference between the time and the time actually being processed is that some of the keys of the electronic musical instrument continue to be delayed, resulting in a longer time to sound generation.

The present invention is to solve the drawbacks of the prior art as described above, when a plurality of keys are pressed frequently at the same time, a specific channel is continuously delayed by uniformly distributing the processing delay time of a channel corresponding to each key. The purpose is to prevent the occurrence of delay.

In order to achieve the above object, the present invention provides a weight calculator for calculating a time for delaying a request of each channel by receiving N channel request signals, and receiving a calculated weight output value from the weight calculator. In addition, a priority discriminator that receives a channel request signal and selects and outputs a channel determined to have the highest priority, receives an output signal from the priority discriminator, and receives a control signal from a timing controller to receive a channel address. And a timing controller for receiving the output of the priority discriminator and the output of the priority discriminator and the channel address from the latch and supplying a timing control signal necessary for the priority discriminator and the weight calculator.

Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

5 is a diagram illustrating a channel control apparatus according to the present invention. A weight calculator unit 1 for receiving _N channel request signals SR _{0 to} SR _N-1 and calculating a time for delaying a request of each channel is shown. And a channel that is determined to have the highest priority by receiving the calculated weighted value from the weight calculator 1 and the channel request signals SR ₀ -SR _N-1 . A priority discriminator 2 which selects and outputs a channel having the highest weight among the selected channels, receives a signal input from the priority discriminator 2, and receives a control signal from the timing controller 4 ( LCK) receives and outputs a channel address as a channel address, an output E of the priority discriminator 2 and a channel address from the latch 3, and a priority discriminator 2 and a weight calculator. Control signal (RES ₀ -RES _N-1 ) and (LE _0- ) And a timing controller 4 for supplying LE _N-1 ).

6 shows a detailed configuration of the weight calculator 1, in which a channel request signal SRi (where i is 0-N-) is input to the CLEAR terminal, and the main clock MCLK is clocked. When input to (CLK) terminal, M divider and counter (5) divides and counts this main clock, and counted outputs from M divider and counter (5) are input, and are output when reset. It consists of a latch 6 which makes (Wi) become "0" and latches an incoming input according to the signal LEi, and outputs the output Wi.

7 shows a detailed configuration diagram of the priority discriminator 2, which comprises a request memory 21 composed of N blocks and a comparison selector binary tree 22. As shown in FIG. In addition, the request memory 21 is composed of each of the R / S flip-flop (7-10) and the end gate (11-14) to the set (S) terminal of the R / S flip-flop (7-10) The channel request signal SR ₀ -SR _N-1 is input, and the control signal RES ₀ -RES _N-1 from the timing controller 4 is input to the reset terminal R, and the AND gate 11-14 is input. In order to input the output (W ₀ -W _N-1 ) from the weight calculator (1) to one input terminal of the input terminal and the output (Q) of the R / S flip-flop (7-10) to the other input terminal. It is composed.

The comparison selector binary tree section 22 (having a plurality of comparison selectors (for example, 16-20)) receives the output of the end gate 11-14 of the request memory section 21 and the terminal. The state from "0", "1" to "N-2", and "N-1" is applied to (D _A ) (D _B ), where N channel request signals are ^{multiplied by} 2 (N = 2 ⁿ , n is a positive integer) and uses only the output D ₀ of the final selector 20 and outputs it to the output SQ. The number of these selectors takes N-1. do. On the other hand, the outputs Q ₀ -Q _N-1 of the R / S flip-flop 7-10 of the request memory 21 are sent to the timing controller 4 through the oragate 15 to the output E. Lose.

8 shows, in detail, a comparison selector of one of the comparison selector binary tree units 22. The comparator 23 has an input W among the inputs W _A and W _B from the request memory unit 21. _{When A} is equal to or larger than _A ), the output is supplied to the selection input S of the multiplexers 24 and 25 with the output "1".

And the multiplexer 24 are request storage section input from the (21) (W _A), (W _B), the selection input from the (S) set to "1" when the input (W _A) the select input (S) is When it is "0", it receives each input (W _B ) and sends it to output (W ₀ ).

Then, the multiplexer 25 is input (D _A) (D _B), a selection input (S) of "1" when in the input (D _A) the select input (S) is "0" when the input (D _B) Receive each and send it to the output (D ₀ ).

9 shows an overall timing diagram of the channel control apparatus according to the present invention. Hereinafter, the operation relationship of the present invention will be described in detail.

First, the channel request signals SR ₀ -SR _N-1 are input to the weight calculator 1 composed of N weight calculators to clear the weights of the weight calculators.

Referring to this with reference to the detailed view of FIG. 6, one weight calculator basically latches the counted output with an M divider and counter 5 for counting the M divided by the main clock MCLK. The latch 6 is latched by the signal LE and output to the output Wi. Therefore, if the channel request signal SRi connected to the M divider and the clear terminal of the counter 5 is activated, the count value is " 0 " Then, the main clock inputted thereafter is divided by M, and the counted signal is outputted to the output Wi by the signal LE input from the timing controller 4.

That is, if a channel is selected and the period in which the common device is used is M period, the channel request signal SR ₀ -SR _N-1 is generated, and the channel request is received within the M period, and the control signal is received from the timing controller 4. When (LE) occurs, the output Wi becomes "0". If the channel request is accepted after the M period has elapsed, the value counted up to that time is output to the output Wi, and the delayed time of processing the corresponding channel is displayed as the output Wi.

Meanwhile, the priority discriminator 2 includes a request memory unit 21 and a comparison selector binary tree unit 22 as shown in FIG. 7 so that the output Wi from the weight calculator unit 1 is an AND gate 11. -1) Since the output comes out only when the signal input to the other input terminal is 1 in the state input to one input terminal of -14), for example, the channel request signal input to the set (S) terminal of the R / S flip-flop (7). When SR ₀ is active, the output Q of the R / S flip-flop 7 becomes "1", and the output W ₀ from the weight calculator 1 inputted to the AND gate 11 becomes the comparison selector. It is output to the binary tree section 22.

And, R / S flip-flop 7 is reset (R) terminal, because generating a control signal (RES ₀₎ is connected if the corresponding channel service when the control signal (RES ₀₎ from a timing controller (4) R a The output Q of the / S flip-flop 7 is made " 0 " so that the output result of the weight calculator is inputted to " 0 "

In addition, the comparator selector binary tree 22 is composed of N-1 (when N is represented by powers of 2 as the number of channels). The comparator 23 is a request memory unit 21 as shown in FIG. ) input (W _a from a) (W _B) of the input (W _a) and the output to a greater or equal than the input (W _B) to "1" this time, the multiplexer 24 selects the input (S) In the state of "1", the input W _A is received and output to the output W ₀ , and the multiplexer 25 receives the input D _A and outputs it to the output D ₀ .

Otherwise, it receives input W ₀ (D _B ) and sends it to output W ₀ (D ₀ ). When the comparator having such a function is configured in a binary tree structure as shown in FIG. 7, the comparator selector binary tree unit 22 inputs the channel values of the channels corresponding to the inputs D _A and D _B , respectively. ) Outputs D ₀ by selecting the channel value of the channel having the largest output value among the output values of the weight calculator 1.

On the other hand, the output E of the priority determiner 2 is activated by the channel request signals SR ₀ -SR _N-1 by using the oragate 15 to output the Q ₀ − of the request memory unit 21. If any one of Q _N-1 is 1, the signal 1 is sent out to control the timing controller 4.

In addition, the timing controller 4 inputs the output E of the priority discriminator 2, the main clock from the weight calculator 1, and the channel address, which is the output of the latch 3, as a control signal LCK. (RES ₀ -RES _N-1 ) (LE ₀ -LE _N-1 ) and the latch 3 connects the control signal LCK of the timing controller 4 to the latch enable terminal LE to control the signal ( The output SQ of the priority discriminator 2 is output as a channel address at the time when the LCK rises.

This operation will be described with reference to the timing diagram of FIG. 9 when only the channel request signal SR ₀ (SR ₁ ) is active at the same time.

If the channel request signal SR ₀ (SR ₁ ) is simultaneously activated at time "C" after the reset signal is activated, the M period and the counter 5 of the corresponding block of the weight calculator 1 are cleared. The corresponding R / S flip-flop 7 in the request memory 21 in the priority determiner 2 is set.

At this time, since the input W ₀ (W ₁ ) from the request memory unit 21 becomes “0” after the reset signal is initially activated, both the weights of the channel 0 and the channel 1 are “0” in the comparison selector. Is entered.

In this case, since the input selector W _A (W _B ) is selected when the comparison selector is equal to the magnitude of the weight, the priority discriminator 2 outputs "0", and the timing controller 4 has the highest priority. As the output E of the discriminator 2 is activated, the control signal LCK is output to cause the latch 3 to output the channel address " 0 ".

Since then the channel services the channel 0 as the request signal (SR ₀₎ is the active control signals based on the channel address are treated in order to release the channel request memory according to the channel request signal (SR ₀₎ (RES ₀₎ Activate to make the weight of channel 0 W ₀ zero.

On the other hand, after the M period, the timing controller 4 activates the control signal LCK again to process the channel request signal SR _{1 which} has not been processed at time "C" as in the case of the channel request signal SR ₀ . Process.

In this case, when the control signal RES ₁ is activated (time " D "), since there is no set R / S flip-flop in the request memory 21, the output E of the priority discriminator 2 is " 0 "and the timing controller 4 does not output any more control signal LCK and the weight W ₁ of the channel 1 becomes 1 as the signal LE ₁ is generated.

When the channel request signals SR ₀ and SR ₁ are generated again at time "E", the channel address becomes "1" because the weight of channel 1 is larger as W ₁ among the weights of the two channels, and thus the channel request signal SR _1. ) Is processed first, and then after M cycles, the channel request signal (SR ₀ ) is processed so that the channel address becomes "0" so that the time required to process the channel after the request of each channel is averaged evenly. Can be.

As described above, the present invention solves the problem of delayed generation of sound by delaying a specific channel by uniformly distributing the processing delay time of a channel corresponding to each key evenly when a plurality of keys are simultaneously pressed frequently. Of course, the circuit configuration is simple and easy to integrate.

Claims (5)

A weight calculator for calculating the time for delaying the request of each channel by receiving N channel request signals, a calculated weighted output value from the weight calculator, and the channel request signal A priority discriminator which selects and outputs a channel determined to be the highest and receives an output signal from the priority discriminator and receives a control signal from a timing controller to determine the priority at the time when the control signal rises. And a timing controller for supplying a timing output signal for the priority discriminator and the weight calculator to receive the output of the odd output as a channel address, and to receive the output of the priority discriminator and the channel address from the latch. Channel controller for electronic musical instruments. 2. The apparatus of claim 1, wherein the weight calculator unit divides the channel request signal and the main clock by M and counts the M divider and the counter, and receives the output of the M divider and the counter so that the output becomes "0" upon reset. And a latch for outputting the latched input signal. The weight estimator of claim 1, wherein the priority discriminator is configured to output a high level when the output of the weight calculator and the output of the channel request signal are activated, and receives the output of the request memory. A timing selector that outputs a high level when the binary selector of the comparator selector selects and outputs a channel value of a channel having an output value, and a channel request signal is activated and at least one signal output from the flip-flop output from the request memory unit becomes high level Electronic channel control device for an electronic instrument, characterized in that it comprises an oragate for operating. 4. The channel controller of claim 3, wherein the request memory unit comprises a flip-flop for storing the channel request and an end gate for outputting the stored coefficient value only when the channel request is stored. 4. The channel control apparatus for an electronic musical instrument as set forth in claim 3, wherein the comparator selector binary tree unit comprises a comparator for comparing the coefficient values of the request storage unit and outputting a channel value equal to or greater than that of the request storage unit.