KR920005294B1 - Chip enable signal control circuit of dual port memory device - Google Patents

Abstract

The circuit controls the enable signal for operating a chip when data are transmitted between a RAM (random access memory) port and a SAM (serial access memory) port and comprises a switching means (NO1) for receiving a chip enable signal (RAS) at one input terminal and a latch means (NO2,NO3) for receiving the output of the switching means (NO1) through inverters (I1,I2) at one input terminal and a first clock (CLK1) indicating completion of a data transmission at another input terminal to output a second clock (CLK2) as a mast clock inside the chip. The circuit enlarges an active region of the mast clock to stabilize the data transmitting operation.

Description

Chip enable signal control circuit of a dual port memory device.

1 is a chip enable signal control circuit of a conventional dual port memory device.

2 is an operational waveform diagram of FIG.

3 is a chip enable signal control circuit of a dual port memory device according to the present invention.

4 is an operational waveform diagram of FIG.

* Explanation of symbols for main parts of the drawings

10: latch part

NO1, NO2, NO3: first, second and third noah gates

I1, I2: first and second inverters

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a chip enable signal control circuit of a dual port memory device, and in particular, a signal for operating a chip during data transfer between a random access memory (RAM) port and a serial access memory (SAM) port. It relates to a chip enable control circuit of a dual port memory device for controlling.

The dual port memory device is a memory device developed for use as a VRAM (Video RAM) for a graphic display. Initially, VRAM was developed with 256K × 4 RAM ports and 256K × 4 SAM ports. Since then, the functions of 64K × 4VRAM have been improved to include the Write Per Bit function and the function of Real Time Data Transfer from memory to serial data. Currently, 1M bit of VRAM is classified into 256K × 4 or 128K × 8.

On the other hand, when a general DRAM transfers information from a processor to a peripheral device, it first passes the information to the memory and then accesses the information transferred to the memory. In this case, the processor cannot transmit information to the memory while the peripheral device is accessing. However, while the VRAM transfers information to the memory through the first port, the peripheral device can simultaneously access the memory through the second port. The first and second ports represent RAM and SAM ports, and since the SAM ports have a high speed access time, VRAMs are widely used for high resolution or high speed image display. The data transfer cycle of the SAM port includes a read transfer cycle, a write transfer cycle, and a real-time write transfer cycle. The read transfer cycle transfers the data written to the RAM port to the SAM port and sets it into a mode capable of reading this SAM port. The write transfer cycle transfers the data written to the SAM port from the peripheral device to the RAM port. It is a mode.

1 is a chip enable signal control circuit of a conventional dual port memory device. The control circuit of the chip enable signal includes first and second NOA gates NO1 and NO2 and first and second butters I1 and I2. 2 is an operation waveform diagram during data transmission of the chip enable signal control circuit.

를 입력시키고 타측 입력단을 접지시킨다. 그러므로 상기 제1노아케이트(NO1)는 상기

와 반전된 신호를 출력하며, 이 신호는 제1 및 제2인버터(I1), (I2)에 의해 소정시간 지연되어 제2노아케이트(NO2)의 일측 입력단에 입력된다. 또한, 상기 제2노아케이트(NO2)의 타측입력단은 접지되며, 따라서 이 제2노아케이트(NO2)는 상기 제2인버터(I2)의 출력을 반잔시킨 클럭(CLK)을 출력한다. 상기 제2노아케이트(NO2)에서 출력되는 클럭(CLK)은 칩내부의 마스터 클럭(Master Clock)으로 듀얼포트 사이의 데이타전송을 제어한다. 상기 듀얼포트 사이의 데이타전송은 상기 클럭(CLK)의 액티브 영역, 즉

의 액티브 영역에서만 이루어지게 된다. 그러므로 종래에는 듀얼포트사이의 데이타전송시간이

의 액티브영역으로 제한되므로 데이타전송의 마진(margin)이 작으며, 또한 데이타전송시간이

의 비액티브영역까지 확대되면 데이타전송이 완료되기전에 칩이 프리차아지(Precharge)상태가 되어 오동작을 하는 문제점이 있었다. 따라서 이 발명의 목적은 듀얼포트사이에서 데이타전송시 전송시간을 보상하여 전송마진을 크게하고 오동작을 방지할 수 있는 듀얼포트 메모리 소자의 칩인에이블신호제어회로를 제공함에 있다.In the data transfer mode, a chip enable signal that is externally applied to one input terminal of the first NO?

Input and ground the other input terminal. Therefore, the first no-arcade NO1 is

And a signal inverted, and the signal is delayed for a predetermined time by the first and second inverters I1 and I2 and is input to one input terminal of the second no-arcade NO2. In addition, the other input terminal of the second no-take NO2 is grounded, and therefore, the second no-take NO2 outputs a clock CLK which half the output of the second inverter I2. The clock CLK output from the second no-quest NO2 is a master clock inside the chip and controls data transmission between the dual ports. The data transfer between the dual ports is an active region of the clock CLK, that is,

Only in the active region of the. Therefore, conventionally, data transfer time between dual ports

The margin of data transmission is small, and the data transmission time is limited because it is limited to the active area of

When the inactive area of the chip is expanded, the chip is in a precharge state before the data transfer is completed, causing a malfunction. Accordingly, an object of the present invention is to provide a chip enable signal control circuit of a dual port memory device capable of compensating transmission time during data transmission between dual ports to increase transmission margin and prevent malfunction.

In order to achieve the above object, the present invention provides a first enable signal that is input to a chip enable signal at one input terminal and the other input terminal is grounded, and the first gate is connected to the one input terminal via inverters and indicates completion of data transmission. And a latch circuit input to the other input terminal and outputting a second clock which is a master clock inside the chip.

가 입력되고 타측 입력단이 접지된 제1노아게이트(NO1)와, 상기 제1노아게이트(NO1)와 제1 및 제2인버터(I 1), (I 2)를 개재시켜 접속되는 래치부(10)로 이루어진다. 상기 노아게이트(NO1)은 상기

를 반전시키는 스위치(Switch) 동작을 한다. 또한, 상기의 래치부(10)는 제2 및 제3노아게이트(NO2), (NO3)로 이루어지며, 이 제2 및 제3노아게이트(NO2), (NO3)의 일측 입력단들에 제2인버터(I 2)의 출력과 데이타 전송의 완료를 나타내는 제1클럭(CLK1)이 각각 입력되고, 타측입력단에는 타측의 노아게이트(NO3), (NO2)의 출력단이 각각 접속된다. 상기 제1클럭(CLK1)은 상기

의 액티브영역에서 제1에지(edge)를 가지며, 제2에지에 의해 데이타전송의 완료를 나타낸다. 상기 제1클럭(CLK1)이 '로우'액티브일 때 상기 제1에지는 하강에지이고, 상기 제2에지는 상승에지이다. 상기 제2노아게이트(NO2)는 칩내부의 마스터 클럭(Master Clock)인 제2클럭(CLK2)을 출력한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings. 3 illustrates a chip enable signal control circuit of a dual port memory device according to the present invention. The chip enable signal control circuit is connected to an egg input terminal.

10 is connected and the other input terminal is grounded, the latch unit 10 connected via the first NOA gate NO1 and the first NOA gate NO1 and the first and second inverters I 1 and I 2. ) The NOA gate NO1 is

Switch operation to reverse. In addition, the latch unit 10 is composed of second and third NOA gates NO2 and NO3, and a second input terminal of one side of the second and third NOA gates NO2 and NO3. The first clock CLK1 indicating the output of the inverter I 2 and the completion of data transfer is input, respectively, and the output terminals of the other gates NO3 and NO2 are connected to the other input terminal, respectively. The first clock CLK1 is the

Has an first edge in the active area of, indicating completion of data transfer by the second edge. When the first clock CLK1 is 'low' active, the first edge is a falling edge, and the second edge is a rising edge. The second NOR gate NO2 outputs a second clock CLK2 which is a master clock inside the chip.

를 입력시킨다. 상기 제1노아게이트(NO1)는 상기

와 반전된 신호를 출력하며, 이 신호는 제1 및 제2인버터(I 1), (I 2)에의해 소정시간 지연되어 제2노아게이트(NO2)의 일측입력단에 입력된다. 또한, 상기 제3노아게이트(NO3)의 일측입력단에 칩의 내부에서 발생되며 제2에지에 의해 데이타 전송의 완료를 나타내는 제1클럭(CLK1)을 입력한다. 상기에서 제1클럭(CLK1)의 제1에지가

의 액티브구간에, 제2에지가

의 비액티브구간에 있다하자, 상기 제1클럭(CLK1)이 '하이'일때 상기 제3노아게이트(NO3)는 '로우'를 출력하므로 상기 제2노아게이트 (NO2)에서 출력되는 제2클럭(CLK2)은 상기 제2인버터(I 2)의 출력을 반전시킨 것이다. 그 후 상기 제1클럭(CLK1)이 '로우'로 천이되어 상기 제3노아게이트(NO3)의 일측입력단에 입력하면 타측입력단에 입력되는 상기 '로우'상태의 제2클럭(CLK2)에 의해 상기 제3노아게이트(NO3)의 출력은 '하이'상태가 되어 상기 제2노아게이트(NO2)는

에 관계없이 제2클럭(CLK2)은 '로우'를 유지한다. 즉, 상기

가 '하이'의 비액티브가 되어도 제2클럭(CLK2)은 '로우'로 출력하게 되어 액티브 구간이 길어진다. 그후, 상기 제1클럭(CLK1)이 '하이'상태로 천이하면 상기 제3노아게이트(NO3)의 출력이 '로우'상태가 된다. 따라서 상기 제2노아게이트(NO2)에서 출력되는 제2클럭(CLK2)은 상기 제2인버터(I 2)의 출력을 반전시킨 '하이'상태가 된다.4 shows an operation waveform diagram of data transfer of the chip enable signal control circuit of the dual port memory device. The operation of FIG. 3 will be described with reference to FIG. In the data transfer mode, a chip enable signal that is externally applied to the input terminal of the first NOR gate NO1.

Enter. The first NOR gate NO1 is the

And a signal inverted, and the signal is delayed for a predetermined time by the first and second inverters I 1 and I 2 and input to one input terminal of the second NOR gate NO 2. In addition, a first clock CLK1 generated inside the chip and inputting the first clock CLK1 by the second edge is input to one input terminal of the third NOA gate NO3. In the above, the first edge of the first clock CLK1

The second edge of the

When the first clock CLK1 is 'high', the third NOR gate NO3 outputs 'low', so that the second clock output from the second NOR gate NO2 is inactive. CLK2 is inverting the output of the second inverter I 2. After that, when the first clock CLK1 transitions to 'low' and inputs to one input terminal of the third NOA gate NO3, the first clock CLK1 is inputted by the second clock CLK2 of the 'low' state input to the other input terminal. The output of the third NOA gate NO3 is 'high' state so that the second NOA gate NO2 is

Regardless, the second clock CLK2 remains 'low'. That is

Even if the 'high' is inactive, the second clock CLK2 outputs a 'low' so that the active period becomes long. Thereafter, when the first clock CLK1 transitions to the 'high' state, the output of the third NOR gate NO3 is 'low'. Therefore, the second clock CLK2 output from the second NOA gate NO2 is in a 'high' state in which the output of the second inverter I 2 is inverted.

의 액티브구간에 있는 경우 상기 제2클럭(CLK2)은

가 비액티브되는 것에 동기되어 '하이'가 되는것을 유의하여야 한다.In addition, the second edge of the first clock CLK1

The second clock CLK2 is in the active section of

It should be noted that is motivated by being inactive.

의 비액티브영역까지 확대되어도 칩이 프리차아지되지않고 소정시간 동안 정상 데이타 전송 동작을 한다. 따라서 이 발명 듀얼 포트 사이에서 데이타 전송시간을 보상하여 전송 마진을 크게 할 뿐만아니라 안정된 데이타 전송동작을 할 수 있게 하는 잇점이 있다.As described above, the active area of the master clock is enlarged within the chip by a clock indicating completion of data transfer, thereby compensating for data transfer time between the dual ports, increasing transmission margin, and increasing data transfer time.

Even if it extends to the inactive area of the chip, the chip does not precharge and performs normal data transfer operation for a predetermined time. Therefore, there is an advantage in that the data transfer time is compensated for between the dual ports of the present invention to not only increase the transmission margin but also to enable stable data transfer operation.

Claims (3)

In a dual port memory device, a switch means for inputting a chip enable signal to one input terminal and a switch connected to one input terminal via inverters and a first clock indicating completion of data transmission are input to the other input terminal and the master in the chip. And a latch means for outputting a second clock that is a clock. The chip enable signal control circuit of claim 1, wherein the first clock has a first edge in an active region of the chip enable signal and has a second edge when data transfer is completed. 3. The chip enable signal control circuit of claim 2, wherein the second clock becomes inactive at a later time when the second edge of the first clock and the chip enable signal are inactive. .

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