Nothing Special   »   [go: up one dir, main page]

KR910010623A - 건식 식각 및 습식 식각의 특성을 이용한 접촉 식각 방법 - Google Patents

건식 식각 및 습식 식각의 특성을 이용한 접촉 식각 방법 Download PDF

Info

Publication number
KR910010623A
KR910010623A KR1019890016745A KR890016745A KR910010623A KR 910010623 A KR910010623 A KR 910010623A KR 1019890016745 A KR1019890016745 A KR 1019890016745A KR 890016745 A KR890016745 A KR 890016745A KR 910010623 A KR910010623 A KR 910010623A
Authority
KR
South Korea
Prior art keywords
etching
oxide film
dry
wet
contact
Prior art date
Application number
KR1019890016745A
Other languages
English (en)
Inventor
서현환
Original Assignee
문정환
금성일렉트론 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 문정환, 금성일렉트론 주식회사 filed Critical 문정환
Priority to KR1019890016745A priority Critical patent/KR910010623A/ko
Publication of KR910010623A publication Critical patent/KR910010623A/ko

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76804—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics by forming tapered via holes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Weting (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

내용 없음

Description

건식 식간 및 습식 식각의 특성을 이용한 접촉 식각 방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명의 접촉식각 공정에 따른 접촉홀 단면도.

Claims (1)

  1. 실리콘 기판(4) 및 저온증착 산화막(1) 위에 산화막(2)을 증착하고 이 산화막(2)에 감광막(3)을 도포 및 식각하여서된 것에 있어서, 상기 산화막(2)의 30%를 건식 식각하고 이 30%건식 식각후 남은 산화막(2)의 50%를 등방형 습식식각한 다음에 남은 산화막(2)을 건식 식각으로 접촉홀을 형성함을 특징으로 하는 건식 식각 및 습식 식각의 특성을 이용한 접촉식각방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임
KR1019890016745A 1989-11-18 1989-11-18 건식 식각 및 습식 식각의 특성을 이용한 접촉 식각 방법 KR910010623A (ko)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019890016745A KR910010623A (ko) 1989-11-18 1989-11-18 건식 식각 및 습식 식각의 특성을 이용한 접촉 식각 방법

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019890016745A KR910010623A (ko) 1989-11-18 1989-11-18 건식 식각 및 습식 식각의 특성을 이용한 접촉 식각 방법

Publications (1)

Publication Number Publication Date
KR910010623A true KR910010623A (ko) 1991-06-29

Family

ID=67661016

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019890016745A KR910010623A (ko) 1989-11-18 1989-11-18 건식 식각 및 습식 식각의 특성을 이용한 접촉 식각 방법

Country Status (1)

Country Link
KR (1) KR910010623A (ko)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100242434B1 (ko) * 1992-06-27 2000-03-02 윤종용 반도체 장치의 콘택 형성방법
KR20000019959A (ko) * 1998-09-16 2000-04-15 김영환 반도체 소자의 플러그 형성방법
US6284558B1 (en) 1997-11-25 2001-09-04 Nec Corporation Active matrix liquid-crystal display device and method for making the same

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100242434B1 (ko) * 1992-06-27 2000-03-02 윤종용 반도체 장치의 콘택 형성방법
US6284558B1 (en) 1997-11-25 2001-09-04 Nec Corporation Active matrix liquid-crystal display device and method for making the same
KR100329094B1 (ko) * 1997-11-25 2002-10-25 닛폰 덴키(주) 액티브매트릭스형액정표시장치및그제조방법
KR20000019959A (ko) * 1998-09-16 2000-04-15 김영환 반도체 소자의 플러그 형성방법

Similar Documents

Publication Publication Date Title
KR910010623A (ko) 건식 식각 및 습식 식각의 특성을 이용한 접촉 식각 방법
KR910013463A (ko) 반도체 소자의 개구형성방법
KR910008802A (ko) 반도체장치의 제조방법
KR910013526A (ko) 배선용 콘택홀 형성방법
KR970023633A (ko) 네가티브 포토레지스트를 이용한 반도체장치의 패턴형성방법
KR890005851A (ko) 반도체 장치의 소자분리 방법
KR920007068A (ko) 반도체 금속박막의 스텝 커버리지 측정용 표준웨이퍼 제조방법
KR890008956A (ko) Lpcvd의 질화막을 이용한 실리콘의 부분산화 제조방법
KR970018080A (ko) 반도체장치의 콘택형성방법
KR920003467A (ko) 필드산화막 형성방법
KR910005099A (ko) 접촉상 형성방법
KR880004555A (ko) 이중 절연막의 립 제거 공정방법
KR970054071A (ko) 이중 스페이서를 이용한 반도체장치의 셀 커패시터 형성방법
KR970023756A (ko) 반도체장치의 스페이서 형성방법
KR910010632A (ko) 식각과 열화산화 기술에 의한 에스오아이(soi)의 제조방법
KR920017173A (ko) 필드산화막 제조방법
KR970052599A (ko) 반도체장치의 식각방법
KR970003656A (ko) 반도체 소자의 필드 산화막의 형성방법
KR940016694A (ko) 반도체 소자의 콘택홀 형성방법
KR960042842A (ko) 산화 마그네슘(MgO)이 코팅된 팁을 이용한 필드 에미터 제조방법
KR970053410A (ko) 반도체소자의 소자분리막 제조방법
KR930001353A (ko) 바이모스 제조방법
KR970054059A (ko) 커패시터 제조방법
KR970052415A (ko) 이중 절연막을 사용하는 반도체 장치의 콘택 형성 방법
KR970030643A (ko) 반도체소자의 소자분리막 형성방법

Legal Events

Date Code Title Description
PA0109 Patent application

Patent event code: PA01091R01D

Comment text: Patent Application

Patent event date: 19891118

PG1501 Laying open of application
A201 Request for examination
PA0201 Request for examination

Patent event code: PA02012R01D

Patent event date: 19941102

Comment text: Request for Examination of Application

Patent event code: PA02011R01I

Patent event date: 19891118

Comment text: Patent Application

E902 Notification of reason for refusal
PE0902 Notice of grounds for rejection

Comment text: Notification of reason for refusal

Patent event date: 19980130

Patent event code: PE09021S01D

E601 Decision to refuse application
PE0601 Decision on rejection of patent

Patent event date: 19980420

Comment text: Decision to Refuse Application

Patent event code: PE06012S01D

Patent event date: 19980130

Comment text: Notification of reason for refusal

Patent event code: PE06011S01I