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KR900005565A - 개선된 패턴 형성방법 - Google Patents

개선된 패턴 형성방법 Download PDF

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KR900005565A
KR900005565A KR1019890013017A KR890013017A KR900005565A KR 900005565 A KR900005565 A KR 900005565A KR 1019890013017 A KR1019890013017 A KR 1019890013017A KR 890013017 A KR890013017 A KR 890013017A KR 900005565 A KR900005565 A KR 900005565A
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film
layer
substrate
pattern forming
forming method
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KR1019890013017A
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KR930005943B1 (ko
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가츠야 오쿠무라
도오루 와타나베
마사미 와타세
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아오이 죠이치
가부시키가이샤 도시바
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    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02282—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process liquid deposition, e.g. spin-coating, sol-gel techniques, spray coating
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    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
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    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0332—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their composition, e.g. multilayer masks, materials
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    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/32—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers using masks
    • H—ELECTRICITY
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
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    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Drying Of Semiconductors (AREA)
  • Liquid Deposition Of Substances Of Which Semiconductor Devices Are Composed (AREA)
  • Weting (AREA)

Abstract

내용 없음

Description

개선된 패턴 형성방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제3도(a) 내지 제3도(d)는 본 발명의 제1실시예를 설명하기 위한 단면도,
제4도(a) 내지 제4도(d)는 본 발명의 제2실시예를 설명하기 위한 단면도.

Claims (10)

  1. 제1주표면을 갖는 기판(30)의 상기 제1주표면상에 제1막(31)을 형성하는 단계, 이 제1막(31)상에 제2막(33)을 형성하는 단계, 제1패턴화막(33a,33b)을 형성시키기 위해 상기 제2막(33)을 선택적으로 제거하는 단계, 상기 제1막(31)의 감광부상에 제3막(35)을 선택적으로 형성시키기 위해 제1패턴화막(33a,33b)을 갖는 기판(30)을 선택적으로 형성시키기 위해 제1패턴화막(33a,33b)을 갖는 기판(30)을 소정 용액 속에 담그어 주는 단계, 상기 제1패턴화막(33a,33b)을 제거하는 단계 및, 상기 제3막(35)을 마스크로 해서 상기 제1막(31)을 에칭하는 단계로 이루어진 것을 특징으로 하는 패턴형성방법.
  2. 제1항에 있어서, 단차부(34)를 갖는 상기 기판(30)상에 이단차부(34)가 덮여지게끔 제1막(31)을 형성하도록 된 것을 특징으로 하는 패턴형성방법.
  3. 제1항에 있어서, 상기 제1막(31)이 금속막이고, 상기 제2막(33)이 포토레지스트막인 것을 특징으로 하는 패턴형성방법.
  4. 제1항에 있어서, 상기 제3막(35)이 유리막인 것을 특징으로 하는 패턴형성방법.
  5. 제4항에 있어서, 상기 제3막(35)을 SOG법(Spin On Glass법)으로 형성하도록 된 것을 특징으로 하는 패턴형성방법.
  6. 제1항에 있어서, 상기 제2막(33)을 형성하기 전에 상기 제1막(31)이 덮여지도록 제4막(53)을 형성하는 단계와 상기 제3막(35)을 마스크로 해서 제4막(53)을 에칭하는 단계를 구비하여 이루어진 것을 특징으로 하는 패턴형성방법.
  7. 제1항에 있어서, 상기 제2막(33)을 친수성(親水性)을 갖는 물질로 형성하고, 상기 기판(30)을 담그기 전에 소수성(疎水性)을 갖는 물질로 상기 제2막(33)을 덮는 단계를 구비하여 이루어진 것을 특징을 하는 패턴형성방법.
  8. 제1주표면을 갖는 기판(30,31)을 준비하는 단계와, 이 제1주표면상에 제1막(33)을 형성하는 단계, 제1패턴화막(33a,33b)을 형성시키기 위해 상기 제1막(33)을 선택적으로 제거하는 단계, 상기 제1막(33)이 제거된 제1주표면상에 제2막(35)을 선택적으로 형성시키기 위해 제1패턴화막(33a,33b)를 갖는 기판(30,31)을 소정용액속에 담그어 주는 단계, 상기 제1패턴화막(33a,33b)을 제거하는 단계 및 상기 제2막(35)을 마스크로 해서 상기 기판(30,31)을 에칭하는 단계로 이루어진 것을 특징으로 하는 패턴형성방법.
  9. 제8항에 있어서, 상기 기판(30,31)이 반도체기판인 것을 특징으로 하는 패턴성형방법.
  10. 제8항에 있어서, 상기 제1막(33)을 친수성을 갖는 물질로 형성하고, 상기 기판(30,31)을 담그기 전에 소수성을 갖는 물질로 상기 제1막(33)을 덮는 단계를 구비하여 이루어진 것을 특징으로 하는 패턴형성방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019890013017A 1988-09-08 1989-09-08 개선된 패턴형성방법 KR930005943B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP88-223503 1988-09-08
JP63-223503 1988-09-08
JP63223503A JP2606900B2 (ja) 1988-09-08 1988-09-08 パターン形成方法

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KR900005565A true KR900005565A (ko) 1990-04-14
KR930005943B1 KR930005943B1 (ko) 1993-06-29

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US (1) US4954218A (ko)
EP (2) EP0630044B1 (ko)
JP (1) JP2606900B2 (ko)
KR (1) KR930005943B1 (ko)
DE (2) DE68925398T2 (ko)

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JPH01140629A (ja) * 1987-11-26 1989-06-01 Sharp Corp パターン形成方法

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DE68928856T2 (de) 1999-05-20
EP0358350A2 (en) 1990-03-14
EP0630044A2 (en) 1994-12-21
JP2606900B2 (ja) 1997-05-07
KR930005943B1 (ko) 1993-06-29
EP0358350A3 (en) 1991-10-16
EP0630044A3 (en) 1995-03-29
EP0358350B1 (en) 1996-01-10
US4954218A (en) 1990-09-04
EP0630044B1 (en) 1998-11-18
JPH0272624A (ja) 1990-03-12
DE68928856D1 (de) 1998-12-24
DE68925398T2 (de) 1996-07-25
DE68925398D1 (de) 1996-02-22

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