KR20220013871A - High-electron-mobility transistor device and method of manufacuring the same - Google Patents

Abstract

The present invention provides a method for fabricating a semiconductor device having the improved electrical characteristics and reliability. Specifically, the present invention relates to a method for improving performance of a semiconductor device by disposing a material having the high heat dissipation characteristics in a rear via hole. A via hole is made on the back side through an etching process, after fabricating the front part of the semiconductor device. A 2D material with the high heat dissipation characteristics and a metal layer are formed in the via hole. The 2D material layer with the high heat dissipation characteristics formed on the back effectively allows heat, which may be generated near a source, channel, or drain electrode, to escape, thereby minimizing the degradation of the characteristics of the device due to the heat.

Description

HIGH-ELECTRON-MOBILITY TRANSISTOR DEVICE AND METHOD OF MANUFACURING THE SAME

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a High-Electron-Mobility Transistor (HEMT).

A High-Electron-Mobility Transistor (HEMT, hereinafter, HEMT) uses a junction of heterogeneous semiconductors having different energy band gaps.

The polarization caused by the heterogeneous semiconductor junction and the band-discontinuity resulting from the band gap difference between the semiconductors form a 2-Dimensional Electron Gas (2-DEG) layer at the heterojunction interface, which used as the channel layer of

The concentration of electrons present in the 2-DEG layer is determined by the polarization and band-breaking between the heterojunction semiconductor materials, as well as the charge present in the interior and interface of the semiconductor layer, the barrier layer, and the dielectric films formed on the barrier layer. Also, the concentration of electrons affects the electrical properties of the device.

Electrons formed in the 2-DEG layer move between the source and drain electrodes, and are controlled by voltages applied to the source, drain, and gate electrodes. A HEMT device using a 2-DEG layer is spotlighted as a next-generation power device due to its high frequency characteristics, high power density, and large breakdown voltage characteristics. can lower

An object of the present invention to solve the above problems is to improve stability and reliability by effectively dissipating heat that may occur in a situation where a bias voltage is applied to a semiconductor device using various rear electrode processes in a rear via hole. An object of the present invention is to provide a high electron mobility transistor and a method for manufacturing the same.

Another object of the present invention is to provide a high electron mobility transistor that is structurally stable and has improved electrical properties and a method for manufacturing the same.

The above and other objects, advantages and features of the present invention, and a method for achieving them will become apparent with reference to the embodiments described below in detail in conjunction with the accompanying drawings.

A high electron mobility transistor device of the present invention for achieving the above object, the substrate; a transition layer laminated on the upper surface of the substrate; a semiconductor layer stacked on the transition layer; a barrier layer stacked on the semiconductor layer; a protective layer laminated on the barrier layer; a drain electrode and a source electrode passing through the protective layer and the barrier layer to be in contact with the barrier layer and the semiconductor layer; and a gate electrode disposed between the drain electrode and the source electrode and disposed on the barrier layer exposed upward by an opening penetrating the passivation layer, wherein heat generated during driving of a semiconductor device is dispersed and In order to emit the light, a via hole extending from a lower surface of the substrate to the upper surface is formed, and further comprising a rear electrode layer formed on the lower surface of the substrate and the inner surface and the bottom surface of the via hole.

In the HEMT device, a 2-DEG layer is naturally generated near the interface between the semiconductor layer and the barrier layer due to the difference in polarization and energy bandgap generated by the junction of the semiconductor layer and the barrier layer. Electrons present in the 2-DEG layer are moved by the voltage applied to the source, drain, and gate electrodes. Heat is generated in the semiconductor device by the movement of electrons by the voltage, which causes a decrease in drain current.

A semiconductor device (HEMT) according to embodiments of the present invention may have a via hole on the rear surface and a metal and two-dimensional material layer on the entire rear surface, and the metal and two-dimensional material layer may have high heat dissipation characteristics. Accordingly, it is possible to effectively disperse and radiate heat generated during driving of the semiconductor device to increase electrical characteristics, operational stability, and reliability of the device.

In addition, since the metal and the two-dimensional material layer formed on the via hole and the rear surface may serve as a ground, electrical stability of the device may be improved.

1 is a cross-sectional view for explaining a semiconductor device according to an embodiment of the present invention.
2A to 2N are cross-sectional views sequentially illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention.

Hereinafter, a high electron mobility transistor device and a method for manufacturing the same according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings. Widths and thicknesses of layers or regions shown in the accompanying drawings are exaggerated for clarity of specification. Like reference numerals refer to like elements throughout the detailed description.

1 is a cross-sectional view illustrating a semiconductor device according to an embodiment of the present invention.

Referring to FIG. 1 , a semiconductor device (or HEMT device) includes a substrate 100 , a transition layer 101 disposed on the substrate 100 , and a semiconductor layer 102 disposed on the transition layer 101 . , a barrier layer 103 disposed on the semiconductor layer 102 , and second and third protective layers 105 and 106 sequentially disposed on the barrier layer 103 .

In addition, the semiconductor device includes a drain electrode 202 positioned to penetrate the second and third protective layers 105 and 106 and the barrier layer 103 to be in contact with the barrier layer 103 and the semiconductor layer 102 . and a source electrode 203 , positioned between the drain electrode 202 and the source electrode 203 , and exposed upward by an opening penetrating the second and third protective layers 105 and 106 . and a gate electrode 204 disposed on the barrier layer 103 .

Hereinafter, a method of manufacturing the semiconductor device (or HEMT device) shown in FIG. 1 will be described in detail.

2A to 2N are cross-sectional views illustrating a method of manufacturing a semiconductor device according to an exemplary embodiment of the present invention.

First, referring to FIG. 2A , the substrate 100 is prepared. The material of the substrate 100 may be, for example, silicon carbide (SiC), silicon (Si), gallium nitride (GaN), sapphire, diamond, or the like for manufacturing a semiconductor device. not limited

A transition layer 101 may be stacked on the substrate 100 .

The transition layer 101 may be a layer serving as a kind of buffer for alleviating the difference in lattice constant and thermal expansion coefficient between the substrate 100 and the semiconductor layer 102 to be described later. Although FIG. 2A shows the transition layer 101 having a single-layer structure, it may have a multi-layer structure.

A semiconductor layer 102 may be stacked on the upper surface of the transition layer 101 .

The semiconductor layer 102 may have a thickness of several tens of micrometers or less, and may be, for example, a group III-V compound semiconductor including AlN, InN, GaN, AlGaN, InGaN, AlInN, AlGaInN, GaAs, etc. , but is not limited thereto, and as long as the 2-DEG layer can be formed inside the semiconductor layer 102 , it may be another material layer.

The 2-DEG layer formed in the semiconductor layer 102 may be a layer having a channel electrically connecting the drain electrode 202 and the source electrode 203 . The semiconductor layer 102 may be an undoped layer, but may be a layer to which a small amount of impurities is added in some cases.

A barrier layer 103 may be stacked on the upper surface of the semiconductor layer 102 .

The barrier layer 103 forms a heterojunction with the semiconductor layer 102 .

The barrier layer 103 may include, for example, at least one of Al, Ga, In, and B among nitrides, and may have a single-layer or multi-layer structure for increasing the electron concentration of the 2-DEG layer. For example, the barrier layer 103 may be formed in a single-layer or multi-layer structure including at least one of various nitrides including InGaN, AlGaN, AlInGaN, AlInN, AlN, and the like.

The thickness of the barrier layer 103 may be several tens of nanometers or less, and may be a layer to which a small amount of impurities is added or a layer to which a small amount of impurities is not added.

The semiconductor layer 102 and the barrier layer 103 may include semiconductor materials having different lattice constants, and the barrier layer 103 has a wider band gap than the semiconductor layer 102 .

A 2-DEG layer is formed in the semiconductor layer 102 by band-cutting generated from the difference in polarization and energy band gap occurring at the interface during the heterojunction of the semiconductor layer 102 and the barrier layer 103 .

The 2-DEG layer electrically connects the source electrode and the drain electrode in the HEMT device and is used as a channel through which electrons move.

Although not shown in the drawings, an interfacial layer may be further disposed between the semiconductor layer 102 and the barrier layer 103 .

The interfacial layer may improve the interfacial properties of the semiconductor layer 102 and the barrier layer 103 to improve electron concentration and electron mobility of the 2-DEG layer. The interfacial layer may be a material such as AlN or the like having a thickness of several nanometers or less.

Next, referring to FIG. 2B , conductive metal patterns 201 are formed (patterned or deposited) on the barrier layer 103 through a deposition process.

The metal patterns 201 are used as the drain electrode 202 and the source electrode 203 shown in FIG. 1 according to their positions.

The metal patterns 201 may be, for example, one or more of Ti, Al, Ni, Au, Pd, Cu, Co, Pt, or an alloy thereof. The deposited metal patterns 201 may have a thickness of several nanometers to several micrometers or less.

The metal patterns 201 are diffused into the barrier layer 103 and the semiconductor layer 102 by rapid heat treatment, which will be described later, so that electrons are transferred from the source electrode 203 through the 2-DEG layer of the semiconductor layer 102 to the drain electrode ( 202) to move it.

Next, referring to FIG. 2C , a first protective layer 104 covering the barrier layer 103 and the metal patterns 201 is formed through a deposition process. The deposition process is, for example, any one of a plasma enhanced chemical vapor deposition (PECVD) process, a physical vapor deposition (PVD) process, a pulsed laser deposition (PLD) process, a chemical vapor deposition (CVD) process, and an ALD process, or these may be a combination of

The first protective layer 104 may have, for example, a single-layer or multi-layer structure including at least one of SiO, SiN, and a dielectric having a high dielectric constant.

The first passivation layer 104 may be used to prevent oxidation of the metal patterns 201 that may occur during rapid heat treatment, which will be described later, and to minimize damage to the barrier layer 103 .

Next, referring to FIG. 2D , the metal pattern 201 formed on the barrier layer 103 through a rapid heat treatment process is diffused into the barrier layer 103 and the semiconductor layer 102 to form a drain electrode 202 (drain region) and a source. electrode 203 (source region).

As a rapid heat treatment method, any method in which the metal patterns 201 can form an alloy and diffuse into the semiconductor layer 102 and the barrier layer 103 may be used without particular limitation. In this case, the temperature of the heat treatment may be 1100 degrees or less.

As an example, as a method of forming the drain electrode 202 and the source electrode 203 , the patterns of the drain and source electrodes 202 and 203 may be formed using a photolithography process, and the drain and source electrodes 202 and 203 may be formed using a photolithography process. 203), ohmic metal Ti/Al/Ni/Au may be deposited using an electron beam evaporator, and a lift-off process may be performed.

The drain and source electrodes 202 and 203 may form an ohmic contact through a rapid heat treatment process, and the rapid heat treatment process may be performed at 1100 degrees or less, for example, 850 degrees or less, in a vacuum atmosphere for 30 seconds. Although not shown in the drawings, device isolation may be performed using an ion implantation or etching process after the drain and source electrodes 202 and 203 are formed.

Next, referring to FIG. 2E , after the rapid heat treatment process is completed, the first passivation layer 104 is removed through an etching process. The etching process may be, for example, dry etching, wet etching, or a mixture of dry and wet etching methods.

Next, referring to FIG. 2F , a second passivation layer 105 is formed on the barrier layer 103 , the drain electrode 202 , and the source electrode 203 exposed to the upper portion according to the removal of the first passivation layer 104 . to deposit The deposition process may be, for example, any one of a physical vapor deposition (PVD) process, a pulsed laser deposition (PLD) process, a chemical vapor deposition (CVD) process, and an ALD process, or a combination thereof.

The second protective layer 105 may have a single-layer or multi-layer structure including at least one of SiO, SiN, and a dielectric having a high dielectric constant.

Next, referring to FIG. 2G , in order to apply a bias voltage to the source electrode 203 and the drain electrode 202 , a second protective layer ( 105) is removed through an etching process. The etching process may be, for example, dry etching, wet etching, or a mixture of dry and wet etching methods.

Next, referring to FIG. 2H , in order to dispose the gate electrode, the second protective layer 105 deposited on the barrier layer 103 is etched at an appropriate position between the source electrode 203 and the drain electrode 202 . and removed to form an opening OP1.

The etching process may be, for example, dry etching, wet etching, or a mixture of dry and wet etching methods. The etched area and thickness of the second passivation layer 105 for disposing the gate electrode may be several hundred micrometers or less.

Next, referring to FIG. 2I , a gate electrode 204 is formed on the barrier layer 103 exposed upwardly by the opening OP1 . The gate electrode 204 may be made of Ti, Al, Ni, Au, Pd, Cu, Co, Pt, or an alloy thereof.

In order to reduce resistance, the gate electrode 204 may be provided in a T-shape or a Г-shape in which the width of the upper part is greater than the width of the lower part.

The wiring pattern of the gate electrode 204 may be formed using photolithography and electron beam lithography processes. After the wiring pattern is formed, a multilayer metal including Ni or Pt is deposited using an electron beam evaporator and lift-off ) process can be carried out.

Next, referring to FIG. 2J , a third passivation layer 106 covering the second passivation layer 105 , the gate electrode 204 , the source electrode 203 , and the drain electrode 202 is formed through a deposition process. The deposition process may be, for example, any one of a physical vapor deposition (PVD) process, a pulsed laser deposition (PLD) process, a chemical vapor deposition (CVD) process, and an ALD process, or a combination thereof.

The third protective layer 106 serves to protect the manufactured semiconductor device and is formed by depositing SiO, SiN, or a dielectric having a high dielectric constant. The thickness of the third passivation layer 106 may be several hundred nanometers or less.

Next, referring to FIG. 2K , in order to apply a bias voltage to the source electrode 203 , the drain electrode 202 , and the gate electrode 204 , a third protective layer 106 is formed on the upper surface of each electrode. is removed through an etching process. The etching process may be, for example, dry etching, wet etching, or a mixture of dry and wet etching methods.

When selective etching is difficult due to the small area of the upper surface of each electrode, other portions electrically connected to each electrode may be etched.

Next, referring to FIG. 2L , a via hole H extending vertically in the direction of the source electrode 203 from the rear surface of the semiconductor device completed up to the manufacturing process of FIG. 2K is formed through an etching process. The etching process may be dry etching, wet etching, or a mixture of dry and wet etching methods.

2L shows an example in which the depth (or height) of the via hole H penetrates the substrate 100 and the transition layer 101 and extends to a portion of the semiconductor layer 102 , but up to the barrier layer 103 . In addition, the depth and width (width) of the via hole (H) can be changed in various designs by adjusting the process parameters.

Next, referring to FIG. 2M , a first rear electrode layer 205 is formed on the rear surface of the substrate 100 and the inner surface and bottom surface of the via hole H through a deposition process. The deposition process may be, for example, any one of a physical vapor deposition (PVD) process, a pulsed laser deposition (PLD) process, a chemical vapor deposition (CVD) process, and an ALD process, or a combination thereof.

The first back electrode layer 205 may be made of a metal or a two-dimensional material. The two-dimensional material is, for example, a material made of a monoatomic layer such as graphene and molybdenum disulfide (MoS ₂ ), and may be a material having high conductivity and heat dissipation characteristics.

Next, referring to FIG. 2N , a second rear electrode layer 206 is formed over the entire surface of the first rear electrode layer 205 formed on the rear surface of the substrate 100 through a deposition process.

Like the first back electrode layer 205 , the second back electrode layer 206 may be a metal or a two-dimensional material. The back electrode layer may be provided in a single-layer or multi-layer structure as well as the first back electrode layer 205 and the second back electrode layer 206 .

The first back electrode layer 205 and the second back electrode layer 206 may be made of the same or different materials. When made of another material, the first rear electrode layer 205 may be a metal material, and the second rear electrode layer 206 may be a two-dimensional material. Conversely, when the first rear electrode layer 205 is a two-dimensional material, the second rear electrode layer 206 may be formed of a metal material.

The rear electrode layers 205 and 206 having such high conductivity and heat dissipation characteristics are formed on the rear surface of the semiconductor device, thereby dispersing and dissipating heat generated during driving of the semiconductor device. At this time, by forming a via hole (H) extending from the rear surface to the upper surface of the semiconductor device, and forming the rear electrode layers (205, 206) on the side and bottom surfaces constituting the via hole (H), when driving the semiconductor device It is possible to dissipate and dissipate heat generated in the semiconductor device, thereby further improving electrical characteristics, operational stability, and reliability of the semiconductor device.

In addition, since the back electrode layers 205 and 206 may serve as a grounding layer of a metal and a two-dimensional material, electrical stability of the device may be improved.

The manufacturing method of FIGS. 2A to 2N may be variously modified.

The above description is merely illustrative of the technical idea of the present invention, and various modifications and variations are possible by those skilled in the art to which the present invention pertains without departing from the essential characteristics of the present invention.

Accordingly, the embodiments expressed in the present invention are not intended to limit the technical spirit of the present invention, but to explain, and the scope of the present invention is not limited by these embodiments. The protection scope of the present invention should be construed by the following claims, and all technical ideas that are equivalent to or within the equivalent range should be construed as being included in the scope of the present invention.

100: substrate 101: transition layer
102: semiconductor layer 103: barrier layer
104: first protective layer 105: second protective layer
106: third protective layer 201: conductive metal
202: source electrode 203: drain electrode
204: gate electrode 205: first rear electrode
206: second rear electrode

Claims (1)

Board;
a transition layer laminated on the upper surface of the substrate;
a semiconductor layer stacked on the transition layer;
a barrier layer stacked on the semiconductor layer;
a protective layer laminated on the barrier layer;
a drain electrode and a source electrode passing through the protective layer and the barrier layer to be in contact with the barrier layer and the semiconductor layer; and
a gate electrode disposed between the drain electrode and the source electrode and disposed on the barrier layer exposed upward by an opening penetrating the passivation layer;
A via hole extending from the lower surface of the substrate to the upper surface is formed in order to dissipate and dissipate heat generated when the semiconductor device is driven, and on the lower surface of the substrate, the inner surface and the bottom surface of the via hole. The high electron mobility transistor device further comprising the formed back electrode layer.

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