JP5396784B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof.

  When an electronic device such as a field effect transistor (FET) is manufactured using a nitride semiconductor such as gallium nitride (GaN) or aluminum gallium nitride (AlGaN), high voltage operation effective for high output becomes possible. This is because a nitride semiconductor has a wider energy band gap and a higher dielectric breakdown voltage than an arsenide semiconductor (eg, gallium arsenide (GaAs)) or a phosphide semiconductor (eg, indium phosphide (InP)). For these reasons, FETs using nitride semiconductors have been actively developed in recent years.

  Many nitride semiconductor field-effect transistors (FETs) such as GaN-FETs that have been grown mainly on sapphire substrates or SiC substrates have been produced so far. Many reports such as Non-Patent Document 1 have been made on the structure and characteristics of GaN-FETs on these substrates. Actually, a large output is obtained by using a multi-finger structure in which transistors are arranged in the horizontal direction. Such a multi-finger structure layout is described in Non-Patent Document 2, for example. As a result, GaN-FETs using SiC have been reported to have a large output exceeding several hundred W in the 2 GHz band. The SiC substrate has the advantages of high thermal conductivity and excellent insulating properties. However, the SiC substrate is generally expensive in terms of practical use, and it is difficult to obtain a large-diameter SiC substrate with higher quality. For this reason, when a SiC substrate is used, it is a problem how the manufacturing cost can be reduced.

  Under such circumstances, a nitride semiconductor device on a Si substrate has attracted attention. The reason for this is that the Si substrate is inexpensive and can be easily reduced in size because the diameter can be easily increased. Furthermore, it is possible to achieve high functionality by integrating a device manufactured on Si (for example, CMOS (Complementary Metal Oxide Semiconductor)) and a device manufactured by a compound semiconductor (for example, a laser diode or a field effect transistor). .

  Until now, many researches and developments have been made to fabricate devices using compound semiconductors other than nitride formed on a Si substrate. However, it has not been put into practical use due to difficulties in controlling crystal growth caused by the difference in lattice constant, characteristic deterioration due to crystal defects, and problems of substrate warpage caused by differences in thermal expansion coefficients. In that respect, it has been found that nitride semiconductors can form nitride semiconductor layers with good crystallinity relatively easily compared to GaAs. In recent years, reports on devices using nitride semiconductors on Si substrates have been made. Is increasing. Non-Patent Document 3 and Non-Patent Document 4 show the structure and characteristics of such a GaN-FET on the Si substrate.

  Here, the GaN-FET formed on the Si substrate described in Non-Patent Document 3 will be described. FIG. 7 is a schematic cross-sectional view showing the configuration of a GaN-FET formed on a Si substrate. A buffer layer 11 is formed on the conductive Si substrate 10 by growing an AlN layer, an AlGaN layer, and a GaN / AlN superlattice structure in this order. On top of this, a GaN layer 12 and an AlGaN layer 13 are grown in this order. The surface of the AlGaN layer 13 is covered with a SiN film 23. The SiN film 23 has a partial opening.

On the SiN film 23, a source electrode 20, a drain electrode 22, and a gate electrode 21 are formed. These electrodes are embedded in the opening of the SiN film 23 and are in contact with the AlGaN layer 13. The source electrode 20 and the drain electrode 22 that are ohmic electrodes are formed using a Ti / Au-based metal material. The gate electrode 21 which is a Schottky electrode is formed between the source electrode 20 and the drain electrode 22 using Pd / Si. The SiN film 23 and the gate electrode 21 are covered with the SiN film 24. The source electrode 20 is connected to the conductive Si substrate 10 through the source wiring 25. The drain electrode 22 is connected to the drain wiring 26. Further, a back metal 30 is formed on the back surface of the conductive Si substrate 10. A detailed device manufacturing method is described in Non-Patent Document 3, and will be omitted. With such a structure, it has been reported that a GaN-FET on a Si substrate has an output exceeding 100 W.
JP 2007-273649 A Japanese Patent Laid-Open No. 5-147464 JP-A-9-266215 JP-T-2004-532513 JP 2006-40932 A Y. Ando, Y. Okamoto, H. Miyamoto, T. Nakayama, T. Inoue, and M. Kuzuhara, "10-W / mm AlGaN-GaN HFET With a Field Modulating Plate", IEEE Electron Device Letters, vol. 24 , No. 5, May 2003, pp. 289-291. Takashi Inoue, Yuji Ando, Hironobu Miyamoto, Tatsuo Nakayama, Yasuhiro Okamoto, Kohji Hataya, and Masaaki Kuzuhara, "30-GHz-Band Over 5-W Power Performance of Short-Channel AlGaN / GaN Heterojunction FETs", IEEE Transaction on Microwave Theory And Techniques, vol. 53, No. 1, January 2005, pp. 74-80. Masahiro Hikita, Manabu Yanagihara, Kazushi Nakazawa, Hiroaki Ueno, Yutaka Hirose, Tetsuzo Ueda, Yasuhiro Uemoto, Tsuyoshi Tanaka, Daisuke Ueda, and Takashi Egawa, "AlGaN / GaN Power HFETs on Silicon substrate With Source-Via Grounding (SVG) Structure" , IEEE Transaction On Electron Devices, Vol. 52, No. 9, September 2005, pp.1963-1968. R. Therrien, S. Singhal, A. Chaudhari, W. Nagy, J. Marquart, JW Johnson, AW Hanson, J. Riddle, P. Rajagopal, B. Preskenis, O. Zhitova, J. Willamson, IC Kizilyalli, KJ Linthicum, "AlGaNGaN HFETs on Si Substrates for WiMAX Applications", 2006 IEEE MTT-S International Microwave Symposium Digest, June 2006, pp. 710-713.

As described above, a high output has been realized with a GaN-FET fabricated on a Si substrate, but problems still remain. The problem will be described below.
There is a problem that a conductive layer is formed near the interface between the Si substrate and the nitride semiconductor. In Patent Document 1, in a nitride semiconductor grown on a Si substrate, a p-type diffusion layer is formed by diffusing Ga or Al at the interface between the Si substrate and the nitride semiconductor. When a wiring such as an FET or a microstrip line is formed on a nitride semiconductor layer structure in which such a conductive layer exists, the withstand voltage characteristic of the FET is deteriorated and high voltage operation is hindered. In addition, high-frequency characteristics such as line loss and gain are deteriorated.

  In Patent Document 1, the current through the conductive layer is suppressed by ion-implanting the Si substrate so as to compensate the p-type diffusion layer, and as a result, a high breakdown voltage characteristic is obtained. However, in this method, it is necessary to pay close attention to the dose amount of ion implantation into Si for compensating the diffusion layer, and there remains a problem in controlling the diffusion of Ga and Al.

  Patent Document 2 describes a semiconductor device in which GaAs, which is a group III-V compound semiconductor, is grown on a Si substrate. In such a semiconductor device, crystal defects are introduced at the initial stage of growth on the Si substrate, and Si in the Si substrate diffuses into the GaAs layer. Thus, it is pointed out in Patent Document 2 that the resistivity between the Si substrate and the compound semiconductor interface decreases. Nitride semiconductors have also grown on Group IV Si substrates and SiC substrates. For this reason, there are crystal defects that occur at the early stage of growth of the buffer layer by the nitride semiconductor on the substrate, diffusion of Si from the Si substrate to the nitride semiconductor layer, and the like. Thereby, it can be easily estimated that an unintended conductive layer is formed at the interface between the substrate and the semiconductor even in the case of a nitride semiconductor.

  Such crystal defects and Si diffusion vary depending on the growth conditions of the buffer layer. Therefore, it is necessary to pay close attention to growth. In general, it is difficult to obtain a Si substrate having good insulating properties, and the conductivity of the Si substrate itself can also deteriorate the high-frequency characteristics. The deterioration of the high frequency characteristics is not limited to only the transistor portion, but also appears as a loss of wiring or the like when a monolithic microwave integrated circuit (MMIC) is manufactured, and desired characteristics cannot be obtained. Sometimes.

  In addition, the Si substrate has a problem that the thermal conductivity is lower than that of a conventionally used SiC substrate and the heat dissipation is inferior. Therefore, when a GaN-FET having a high output density is formed on a Si substrate, device characteristics such as high-frequency gain and output characteristics are likely to deteriorate due to temperature. As described above, the actual device has a multi-finger structure. For this reason, in addition to heat generation at each gate finger portion, an influence of thermal interference between adjacent fingers appears. Therefore, the characteristics of the multi-finger structure are further deteriorated as compared with a single finger structure. For this reason, it is important how to efficiently release heat generated in the FET portion and prevent thermal interference with the adjacent device.

  In order to improve heat dissipation, Patent Document 3 removes the substrate directly under the heat generating portion (portion where the transistor is formed) until it reaches the semiconductor layer. And the heat conductor by a metal is provided in the part. According to this structure, heat dissipation is improved. However, since the compound semiconductor layer and the metal heat conductive layer are in contact, when a high voltage is applied, the withstand voltage characteristic is deteriorated compared to the case where there is a substrate directly under the heat generating portion, and high voltage operation becomes difficult.

  In general, the thickness of a compound semiconductor layer used in an FET is about several microns and is very brittle. Therefore, in the structure as in Patent Document 3 in which the metal heat conductive layer is provided in such a thin place, it is conceivable that the yield decreases due to cracking during the production. For this reason, it is necessary to pay close attention to its production. Furthermore, since the metal heat conductor is provided by removing the substrate under the heat generating part, the parasitic capacitance generated between the electrodes of the heat generating part is increased. And it causes deterioration of high frequency characteristics. In this structure, since only the substrate is removed, the conductive layer in the vicinity of the interface between the Si substrate and the nitride semiconductor layer remains as it is. For this reason, there exists a possibility that a pressure | voltage resistant characteristic and a high frequency characteristic may deteriorate.

  In order to improve heat dissipation, Patent Document 4 adopts a technique of introducing a heat dissipating layer and dispersing heat over a wide area. However, in a multi-finger structure having a plurality of gate fingers, heat propagates to other adjacent finger portions depending on the material selected, resulting in deterioration of characteristics due to thermal interference. Furthermore, in the case of this structure, the conductive layer in the vicinity of the interface between the Si substrate and the nitride semiconductor layer remains as it is, and there is a possibility that the breakdown voltage characteristics and the high frequency characteristics are deteriorated.

  Moreover, in order to improve heat dissipation, in patent document 5, the high heat conductive insulator layer is provided in Si substrate. However, in the case of this structure, the conductive layer in the vicinity of the interface between the Si substrate and the nitride semiconductor layer remains as it is, and there is a possibility that the breakdown voltage characteristic and the high frequency characteristic are deteriorated. In addition, since an insulator is provided on the entire surface of the Si substrate, thermal interference is unavoidable when a plurality of transistors are arranged. Furthermore, it becomes difficult to produce a through electrode for securing the grounding property of a back surface metal and a transistor on the front surface, which are necessary when producing an MMIC using a microstrip line.

  The present invention has been made in view of the above problems, and an object of the present invention is to provide a semiconductor device that easily obtains a high output and a method for manufacturing the same.

  The semiconductor device according to the present embodiment includes a substrate, a compound semiconductor layer formed on the substrate, a transistor manufactured using the compound semiconductor layer, and a thickness of the compound semiconductor layer from the back surface of the substrate. A removal region removed halfway in the direction and a high thermal conductivity insulator embedded in the removal region and having a higher thermal conductivity than the substrate.

  The method for manufacturing a semiconductor device according to the present embodiment includes a step of forming a compound semiconductor layer on a substrate, a step of manufacturing a transistor having the compound semiconductor layer, and a thickness of the compound semiconductor layer from the back surface of the substrate. The method includes a step of forming a removal region removed partway in a direction and a step of embedding a high thermal conductivity insulator having a higher thermal conductivity than the substrate in the removal region.

  According to the present invention, it is possible to provide a semiconductor device that easily obtains a high output and a method for manufacturing the same.

Embodiment 1 FIG.
First, a semiconductor device according to the present embodiment will be described with reference to FIG. FIG. 1 is a schematic cross-sectional view illustrating a configuration of a main part of a semiconductor device. The semiconductor device includes a transistor. Here, a field effect transistor (FET) will be described as a transistor.

  The semiconductor device has a structure in which a compound semiconductor layer 110 is formed on a substrate 100. As the substrate 100, for example, a Si substrate can be used. As the compound semiconductor layer 110, a nitride semiconductor layer can be used. The compound semiconductor layer 110 has a configuration in which a buffer layer 111, a channel layer 112, and an electron supply layer 113 are sequentially formed from the substrate 100 side. The buffer layer 111 is an initial growth layer of the compound semiconductor layer 110, and is formed to alleviate lattice mismatch. The buffer layer 111 includes a region exhibiting p-type or n-type conductivity. In the channel layer 112, a two-dimensional electron gas is induced in the vicinity of the interface with the electron supply layer 113, and electrons travel in the vicinity of the interface. Here, gallium nitride (GaN) is used for the channel layer 112. The electron supply layer 113 has an electron affinity smaller than that of the channel layer 112 and supplies electrons to the channel layer 112. Here, aluminum gallium nitride (AlGaN) is used for the electron supply layer 113.

  The transistor 120 is manufactured using the compound semiconductor layer 110. That is, the transistor 120 including the compound semiconductor layer 110 in part is formed over the substrate 100. In addition to the compound semiconductor layer 110, the transistor 120 includes a source electrode 121, a gate electrode 122, a drain electrode 123, a first surface protective film 124, and a second surface protective film 125. Although not shown in the drawing, isolation may be performed in a region other than the region from the source electrode 121 to the drain electrode 123 with the gate electrode 122 interposed therebetween. For example, oxidation treatment or the like is performed in the vicinity of the interface between the electron supply layer 113 and the channel layer 112 with the electron supply layer 113. As a result, the two-dimensional electron gas is not generated near the interface between the channel layer 112 and the electron supply layer 113, and isolation is achieved.

  The source electrode 121 and the drain electrode 123 are formed on the electron supply layer 113 of the compound semiconductor layer 110. The source electrode 121 and the drain electrode 123 are in ohmic contact (ohmic contact) with the electron supply layer 113. The surface of the electron supply layer 113 other than the region where the source electrode 121 and the drain electrode 123 are formed is covered with the first surface protective film 124. Here, a silicon nitride (SiN) film that is an insulating film is used as the first surface protective film 124.

  A gate electrode 122 is formed on the first surface protective film 124. Carriers traveling near the interface of the electron supply layer 113 in the channel layer 112 can be controlled by the voltage applied to the gate electrode 122. In addition, an opening is formed in the first surface protective film 124, and the gate electrode 122 is embedded in the opening. As a result, the gate electrode 122 and the electron supply layer 113 are in Schottky contact. The gate electrode 122 is sandwiched between the source electrode 121 and the drain electrode 123. Here, the gate electrode 122 has a field plate structure in order to prevent deterioration of breakdown voltage characteristics due to electric field concentration at the drain end of the gate electrode 122. Specifically, the gate electrode 122 on the first surface protective film 124 is extended to the drain electrode 123 side. That is, the gate electrode 122 has a shape protruding from the source electrode 121 side to the drain electrode 123 side.

  A second surface protective film 125 is formed on the first surface protective film 124 so as to cover the gate electrode 122. Here, a silicon nitride (SiN) film which is an insulating film is used as the second surface protective film 125. Further, the source electrode 121 and the drain electrode 123 are not covered with the first surface protective film 124 and the second surface protective film 125 and are exposed.

  Under the transistor 120, a portion from the back surface of the substrate 100 to the middle of the compound semiconductor layer 110 in the thickness direction is removed. At least a region including the interface between the substrate 100 and the buffer layer 111 immediately below the transistor 120 is removed. As a result, the conductive layer near the interface between the substrate 100 and the compound semiconductor layer 110 is removed. Then, the breakdown voltage characteristics of the transistor 120 are improved, and high voltage operation is possible. In FIG. 1, the substrate 100 and the compound semiconductor layer 110 are removed under the transistor 120 until the channel layer 112 is reached. Specifically, the compound semiconductor layer 110 is removed up to a little above the buffer layer 111. As a range to be removed, at least the buffer layer 111 is preferably removed. Further, it is preferable to remove the two-dimensional electron gas so that it does not decrease.

  A region where the substrate 100 and the compound semiconductor layer 110 are removed is referred to as a removal region 130. The removal region 130 may not be formed over the entire region immediately below the transistor 120. That is, the region including the interface between the substrate 100 and the buffer layer 111 may not be removed in the entire region immediately below the transistor 120. For example, a region including this interface may be removed within a certain range around the gate electrode 122 inside the source electrode 121 and the drain electrode 123 with the gate electrode 122 interposed therebetween. In FIG. 1, the region including the interface is removed from the vicinity of the gate electrode 122 side of the source electrode 121 to the vicinity of the gate electrode 122 side of the drain electrode 123. In FIG. 1, the removal region 130 is formed in an isosceles trapezoidal shape. That is, the removal region 130 has a shape that widens toward the back side of the substrate 100. This facilitates heat dissipation from the back surface of the substrate 100. In the present embodiment, the removal region 130 is formed in the shape of an isosceles trapezoid, but the shape is not limited to this shape. If the removal region 130 is removed from the back surface of the substrate 100 to the middle of the compound semiconductor layer 110 in the thickness direction, the heat dissipation effect is obtained. Is obtained.

  A high thermal conductive insulator 131 is embedded in the removal region 130. As the high thermal conductivity insulator 131, a material having higher thermal conductivity than that of the substrate 100 and exhibiting good insulation is used. Thus, heat generated in the transistor 120 is radiated through the high thermal conductivity insulator 131 having higher thermal conductivity than the substrate 100. For example, when Si is used as the substrate 100, aluminum nitride, boron nitride, diamond, SiC, or the like can be used as the high thermal conductive insulator 131. Here, aluminum nitride (AlN) is used as the high thermal conductive insulator 131. In addition, the high thermal conductive insulator 131 is preferably formed so as to be in contact with the entire surface of the substrate 100 inside the removal region 130. Thereby, heat dissipation efficiency can be improved. The semiconductor device according to the present embodiment has the above configuration.

  Thus, the compound semiconductor layer 110 is removed together with the substrate 100. For this reason, the diffusion layer in the substrate 100 under the transistor 120 and the conductive layer formed unintentionally in the semiconductor layer are eliminated, and the withstand voltage characteristics are improved. Then, a high voltage operation becomes possible, and a semiconductor device with higher output than ever is realized.

  Further, a high thermal conductive insulator 131 is embedded in the removal region 130 instead of a conductive material such as metal. For this reason, a parasitic capacitance is reduced, a semiconductor that operates at a higher frequency without deterioration of high-frequency characteristics is realized. Further, the substrate 100 and a part of the compound semiconductor layer 110 are removed, and a high thermal conductivity insulator 131 is embedded in the region. That is, by embedding the high thermal conductivity insulator 131 near the transistor 120, heat generated in the transistor 120 can be efficiently released. For this reason, deterioration of device characteristics such as high-frequency gain and output characteristics due to temperature hardly occurs. Further, since heat generated in the transistor 120 is radiated through the high thermal conductivity insulator 131, the influence of thermal interference with other elements can be suppressed even when the semiconductor device includes a plurality of elements.

  In FIG. 1, the compound semiconductor layer 110 is removed to a little above the buffer layer 111, but the present invention is not limited to this. The compound semiconductor layer 110 may be removed to such an extent that the two-dimensional electron gas used as the transistor 120 does not decrease. Further, it is preferable that at least a region having a low resistivity is removed from the buffer layer 111 which is an initial growth layer. That is, it is preferably removed from the back surface of the substrate 100 at least halfway in the thickness direction of the buffer layer 111.

  Next, with reference to FIGS. 2 and 3, a method of manufacturing the semiconductor device according to the present embodiment will be described. 2 and 3 are schematic cross-sectional views illustrating a method for manufacturing a semiconductor device.

  First, the compound semiconductor layer 110 is grown on the substrate 100 using a nitride semiconductor material by a metal organic vapor phase epitaxy (MOVPE) growth method. Specifically, a buffer layer 111, a channel layer 112, and an electron supply layer 113 are sequentially grown on the substrate 100. Here, a Si substrate is used as the substrate 100, a GaN layer is used as the channel layer 112, and an AlGaN layer is used as the electron supply layer 113. By the above process, the configuration shown in FIG.

  Next, the source electrode 121 and the drain electrode 123 are formed on the electron supply layer 113. As the source electrode 121 and the drain electrode 123, a metal such as Ti / Al is used. Then, the first surface protective film 124 is deposited on the electron supply layer 113 between the source electrode 121 and the drain electrode 123 by plasma CVD (Chemical Vapor Deposition). That is, the source electrode 121 and the drain electrode 123 are not covered with the first surface protective film 124 and are exposed. Here, a SiN film is used as the first surface protective film 124. Then, a SiN film is deposited to about 100 nm. With the above process, the configuration shown in FIG.

  Then, a part of the first surface protective film 124 between the source electrode 121 and the drain electrode 123 is removed by dry etching using a fluorine-based gas. That is, a part of the first surface protective film 124 corresponding to a region where the gate electrode 122 is formed later is opened. Thereby, a part of the electron supply layer 113 is exposed. Then, the gate electrode 122 is formed on the first surface protective film 124 by electron beam evaporation. The gate electrode 122 is embedded in the opening of the first surface protective film 124. Thereby, the gate electrode 122 and the electron supply layer 113 are in contact with each other. A metal such as Ni / Au can be used for the gate electrode 122.

  Next, a second surface protective film 125 is formed on the first surface protective film 124 between the source electrode 121 and the drain electrode 123 by plasma CVD. That is, the source electrode 121 and the drain electrode 123 are not covered with the second surface protective film 125 and are exposed. The first surface protection film 124 is covered with the second surface protection film 125 between the source electrode 121 and the gate electrode 122 and between the gate electrode 122 and the drain electrode 123. The gate electrode 122 is covered with the second surface protective film 125. Here, a SiN film is used as the second surface protective film 125. Then, a SiN film is formed to a thickness of about 100 nm. Thereby, the transistor 120 is formed, and the structure shown in FIG.

  Then, the back side of the substrate 100 is thinned to about 100 μm by grinding or polishing. After that, the region other than the region immediately below the transistor 120 is covered with a photoresist on the back surface of the substrate 100. That is, the back surface of the substrate 100 is exposed only in a region directly below the transistor 120. Then, the substrate 100 and the compound semiconductor layer 110 are removed by dry etching using a chlorine-based gas until the channel layer 112 of the compound semiconductor layer 110 is reached from the back surface of the substrate 100. Thereby, the buffer layer 111 is removed from the compound semiconductor layer 110. Further, a part of the channel layer 112 in the thickness direction of the compound semiconductor layer 110 is also removed. Through the above steps, the removal region 130 is formed, and the configuration shown in FIG.

  Thereafter, a high thermal conductivity insulator 131 is deposited on the removal region 130 by sputtering. In addition, a high thermal conductivity insulator 131 is embedded in the removal region 130 so that the back surface side of the substrate 100 is planar. Here, AlN is used as the high thermal conductive insulator 131. Through the above steps, the semiconductor device is manufactured as shown in FIG.

  As described above, the substrate 100 and the buffer layer 111 are removed in a region corresponding to the transistor 120. Thereby, the diffusion layer and the conductive layer formed unintentionally are removed. Accordingly, a high breakdown voltage can be realized, and operation at a higher frequency is possible. Then, the high thermal conductive insulator 131 is embedded in the removal region 130. Thus, heat generated in the transistor 120 can be effectively radiated through the high thermal conductivity insulator 131. As described above, according to the semiconductor device of the present embodiment, it is possible to realize a semiconductor device with improved heat dissipation, excellent high breakdown voltage characteristics and high frequency characteristics, and easy to obtain high output.

Embodiment 2. FIG.
The semiconductor device according to the present embodiment has a configuration in which a low thermal conductivity insulator is added to the semiconductor device according to the first embodiment. Here, the semiconductor device according to the present embodiment will be described with reference to FIG. FIG. 4 is a schematic cross-sectional view illustrating a configuration of a main part of the semiconductor device. Note that the basic configuration, manufacturing method, and the like are the same as those in the first embodiment, and thus description thereof will be simplified or omitted as appropriate.

A high thermal conductivity insulator 131 and a low thermal conductivity insulator 132 are embedded in the removal region 130 of the semiconductor device. As the low thermal conductivity insulator 132, a material having a thermal conductivity lower than that of the high thermal conductivity insulator 131 and exhibiting good insulation is used. In addition, it is preferable to use a material having lower thermal conductivity than the substrate 100 as the low thermal conductive insulator 132. Thereby, the conduction of heat to the substrate 100 can be further suppressed. As the low thermal conductive insulator 132, silicon oxide, silicon nitride, a resin material, or the like can be used. Here, AlN is used as the high thermal conductivity insulator 131, and SiO ₂ is used as the low thermal conductivity insulator 132.

  The low thermal conductivity insulator 132 is formed on the surface in contact with the substrate 100 in the removal region 130. That is, the low thermal conductivity insulator 132 is formed on the side surface of the removal region 130. The low thermal conductive insulator 132 is preferably formed thin if heat conduction to the substrate 100 can be suppressed. Thereby, heat can be sufficiently radiated without enlarging the removal region 130. Then, the high thermal conductivity insulator 131 is formed inside the low thermal conductivity insulator 132. That is, the side surface of the high thermal conductivity insulator 131 is completely surrounded by the low thermal conductivity insulator 132. In other words, the low thermal conductivity insulator 132 is provided between the high thermal conductivity insulator 131 and the substrate 100. The high thermal conductivity insulator 131 is in contact with the channel layer 112 and the low thermal conductivity insulator 132. Further, the high thermal conductive insulator 131 does not contact the substrate 100.

  Heat from the transistor 120 is dissipated through the high thermal conductivity insulator 131. In this embodiment mode, the low thermal conductivity insulator 132 is provided between the substrate 100 and the high thermal conductivity insulator 131. For this reason, the heat conducted to the high thermal conductivity insulator 131 can be prevented from being conducted from the high thermal conductivity insulator 131 to the substrate 100. That is, even when the semiconductor device has a plurality of elements, the influence of thermal interference with other elements can be suppressed. Further, the low thermal conductivity insulator 132 is formed so as not to prevent heat dissipation from the transistor 120 to the high thermal conductivity insulator 131. Thereby, heat dissipation efficiency can be kept sufficiently.

Next, a method for manufacturing the semiconductor device according to the present embodiment will be described. First, the same process as in the first embodiment is performed until the removal region 130 is formed. That is, the steps shown in FIGS. 2A to 3D are sequentially performed. Thereafter, a low thermal conductivity insulator 132 is formed from the back side of the substrate 100 by plasma CVD. An oxide film can be used as the low thermal conductive insulator 132. Here, SiO ₂ is used as the low thermal conductive insulator 132. Then, the low thermal conductivity insulator 132 in contact with the channel layer 112 and the low thermal conductivity insulator 132 in contact with the substrate 100 other than the removal region 130 are removed using the patterned resist. As a result, the low thermal conductivity insulator 132 remains on the side surface of the removal region 130. Finally, a high thermal conductivity insulator 131 is deposited on the removal region 130 by sputtering. Thereby, the semiconductor device according to this embodiment is manufactured.

  In this manner, the high thermal conductivity insulator 131 or the low thermal conductivity insulator 132 having a lower thermal conductivity than the substrate 100 is disposed between the high thermal conductivity insulator 131 and the substrate 100. Here, silicon oxide having a lower thermal conductivity than Si used as the substrate 100 is disposed between the Si and the high thermal conductive insulator 131. This realizes a semiconductor device that is less affected by heat interference and that can effectively release heat.

Embodiment 3 FIG.
In this embodiment, a multi-finger structure in which a plurality of transistors 120 are arranged in a horizontal direction is employed. Thereby, a large output can be obtained. In other words, the semiconductor device according to the first embodiment has a configuration in which a plurality of units are arranged adjacent to each other. Here, the semiconductor device according to the present embodiment will be described with reference to FIG. FIG. 5 is a schematic cross-sectional view illustrating a configuration of a main part of the semiconductor device. Here, a semiconductor device in which two units are arranged will be described, but three or more units may be arranged. Since the configuration of each unit is the same as that of the first embodiment, the description is simplified or omitted as appropriate.

  In the semiconductor device, a source electrode 121, a gate electrode 122, a drain electrode 123, a gate electrode 122, and a source electrode 121 are formed in order. That is, the two gate electrodes 122 are sandwiched between the source electrode 121 and the drain electrode 123, respectively. The drain electrode 123 is sandwiched between the two gate electrodes 122. The second surface protective film 125 is formed so as to cover the source electrode 121, the gate electrode 122, and the drain electrode 123. An opening is formed in the second surface protective film 125 on the source electrode 121 and the drain electrode 123.

  A removal region 130 is formed corresponding to each transistor 120. That is, the removal region 130 is formed in a region corresponding to between the source electrode 121 and the drain electrode 123 with one gate electrode 122 interposed therebetween. A high thermal conductive insulator 131 is embedded in each removal region 130. Thereby, the heat generated in each transistor 120 is dissipated through the corresponding high thermal conductive insulator 131.

  It is preferable that the substrate 100 remains at least partially between the high thermal conductivity insulators 131 corresponding to the adjacent transistors 120. In other words, the high thermal conductivity insulator 131 corresponding to the adjacent transistor 120 may be in contact with a part thereof. In addition, it is more preferable that the high thermal conductive insulators 131 corresponding to the adjacent transistors 120 are completely surrounded by the substrate 100, respectively. That is, it is more preferable that the high thermal conductive insulators 131 corresponding to the adjacent transistors 120 are provided apart from each other. As described above, since the substrate 100 remains between the high thermal conductivity insulators 131, thermal interference between adjacent transistors 120 can be more effectively prevented.

  As described above, when a semiconductor device having a multi-finger structure is configured to obtain a high output, thermal interference in the lateral direction is prevented and the heat dissipation is further improved. For this reason, it is possible to obtain a high output by arranging a plurality of transistors 120 in a planar manner as a multi-finger structure.

  In the above, only the main part of the semiconductor device has been described with reference to FIG. Next, the entire configuration of the semiconductor device including the main part shown in FIG. 5 will be described with reference to FIG. FIG. 6 is a schematic cross-sectional view showing the overall configuration of the semiconductor device.

  At least one of the back surface of the substrate 100 and the high thermal conductivity insulator 131 is covered with a back surface metal 140. Here, the back surface metal 140 is formed on the back surface of the substrate 100 and the high thermal conductivity insulator 131. The back metal 140 is grounded. On the outside of the transistor 120, a penetrating portion that leads to the back metal 140 is formed. That is, in the penetrating portion, the second surface protective film 125, the first surface protective film 124, the compound semiconductor layer 110, and the substrate 100 are removed. Further, as described above, since the high thermal conductivity insulator 131 is formed for each transistor 120, it is easy to form the through portion so as not to contact the high thermal conductivity insulator 131. The through portion is formed in the vicinity of the source electrode 121 on the side opposite to the gate electrode 122. In the penetrating portion, a penetrating electrode 141 is embedded in a portion penetrating the compound semiconductor layer 110 and the substrate 100. The through electrode 141 is formed so as to penetrate the substrate 100 and the compound semiconductor layer 110 in a region other than the high thermal conductivity insulator 131. That is, the through electrode 141 and the back metal 140 are in contact with each other.

  A source wiring 126 is formed on the second surface protective film 125. The source wiring 126 is embedded in the opening of the second surface protective film 125 on the source electrode 121. Further, the source wiring 126 and the through electrode 141 are connected by the through portion. As a result, the source electrode 121 is electrically connected to the back metal 140 and grounded. Further, the compound semiconductor layer 110 is provided with an isolation region 142 and is isolated as described in the first embodiment. The isolation region 142 is provided in the vicinity of the through electrode 141 on the side opposite to the transistor 120. The isolation region 142 is provided in the vicinity of the interface between the electron supply layer 113 and the channel layer 112 with the electron supply layer 113.

  With such a structure, it is possible to obtain good connectivity when the semiconductor device is cut into small pieces and mounted on a package or the like. That is, mounting on a package having the back surface as a ground surface is possible, and the degree of freedom in assembly is improved. Moreover, it is possible to dissipate heat through the back surface metal 140, and the heat dissipation efficiency is further improved. As a result, the output characteristics and the like of the semiconductor device are improved. Further, by providing the through electrode 141, grounding can be obtained from the substrate 100 side. Therefore, it is possible to manufacture a monolithic microwave integrated circuit (MMIC) using a microstrip line, and a small semiconductor device is realized.

  Further, a cooling device may be connected to the substrate 100 via the back metal 140. Thereby, the heat dissipation efficiency is further improved, and the output characteristics and the like are also improved. In the present embodiment, only the high thermal conductivity insulator 131 is formed in the removal region 130. However, as in the second embodiment, a low thermal conductivity insulator 132 may be further formed. Accordingly, thermal interference between the transistors 120 can be more effectively prevented, and a high output can be obtained using more transistors 120.

  The preferred embodiments of the present invention have been described above, but the present invention is not limited to the embodiments having such characteristics, and various modifications and changes can be made within the scope of the gist of the present invention described in the claims. Is possible.

1 is a schematic cross-sectional view showing a configuration of a main part of a semiconductor device according to a first embodiment; FIG. 6 is a schematic cross-sectional view showing the method for manufacturing the semiconductor device according to the first embodiment. FIG. 6 is a schematic cross-sectional view showing the method for manufacturing the semiconductor device according to the first embodiment. FIG. 6 is a schematic cross-sectional view showing a configuration of a main part of a semiconductor device according to a second embodiment. FIG. 6 is a schematic cross-sectional view illustrating a configuration of a main part of a semiconductor device according to a third embodiment. FIG. 6 is a schematic cross-sectional view showing an overall configuration of a semiconductor device according to a third embodiment. It is a cross-sectional schematic diagram which shows the structure of GaN-FET formed on Si substrate.

Explanation of symbols

10 conductive Si substrate, 11 buffer layer, 12 GaN layer, 13 AlGaN layer,
20 source electrode, 21 gate electrode, 22 drain electrode, 23 SiN film,
24 SiN film, 25 source wiring, 26 drain wiring, 30 back metal,
100 substrate, 110 compound semiconductor layer, 111 buffer layer, 112 channel layer,
113 electron supply layer, 120 transistor, 121 source electrode,
122 gate electrode, 123 drain electrode, 124 first surface protective film,
125 second surface protective film, 126 source wiring, 130 removal region,
131 High thermal conductivity insulator, 132 Low thermal conductivity insulator, 140 Back metal,
141 Through electrode, 142 Isolation region

Claims (9)

A substrate,
A compound semiconductor layer formed on the substrate;
A transistor manufactured using the compound semiconductor layer;
A removal region removed from the back surface of the substrate to the middle of the thickness direction of the compound semiconductor layer;
A high thermal conductivity insulator embedded in the removal region and having a higher thermal conductivity than the substrate ;
A semiconductor device , wherein a low thermal conductivity insulator having a thermal conductivity lower than that of the high thermal conductivity insulator is formed between the high thermal conductivity insulator and the substrate . The compound semiconductor layer has an initial growth layer with the substrate,
2. The semiconductor device according to claim 1, wherein in the removal region, the semiconductor device is removed from the back surface of the substrate at least partway in the thickness direction of the initial growth layer.   The semiconductor device according to claim 2, wherein the initial growth layer includes a region exhibiting p-type or n-type conductivity. The substrate is a Si substrate;
4. The semiconductor device according to claim 1, wherein the high thermal conductivity insulator is a material having a higher thermal conductivity than the Si substrate. 5. Arranging a plurality of the transistors in the plane, the semiconductor device according it to any one of claims 1 to 4, characterized in that there remains a Si substrate at least a portion between each of said high thermal conductivity insulating material . Among the substrate and the high thermal conductivity insulating material, at least one semiconductor device according to any one of claims 1 to 5, characterized in that is covered with metal. The semiconductor device according to any one of claims 1 to 6, characterized in that the through electrode is provided on the substrate and the compound semiconductor layer in the region other than the high thermal conductivity insulating material. The semiconductor device according to any one of claims 1 to 7, wherein the compound semiconductor layer is a nitride semiconductor layer. Forming a compound semiconductor layer on the substrate;
Producing a transistor having the compound semiconductor layer;
Forming a removal region removed from the back surface of the substrate halfway in the thickness direction of the compound semiconductor layer;
Forming a low thermal conductivity insulator on a side surface of the removal region;
Burying a high thermal conductivity insulator having higher thermal conductivity than the substrate and the low thermal conductivity insulator in the removal region where the low thermal conductivity insulator is formed on the side surface. .

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