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KR20160041581A - 적층형 반도체 패키지 및 이의 제조 방법 - Google Patents

적층형 반도체 패키지 및 이의 제조 방법 Download PDF

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Publication number
KR20160041581A
KR20160041581A KR1020140135819A KR20140135819A KR20160041581A KR 20160041581 A KR20160041581 A KR 20160041581A KR 1020140135819 A KR1020140135819 A KR 1020140135819A KR 20140135819 A KR20140135819 A KR 20140135819A KR 20160041581 A KR20160041581 A KR 20160041581A
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KR
South Korea
Prior art keywords
semiconductor package
interposer
lower semiconductor
adhesive member
output terminal
Prior art date
Application number
KR1020140135819A
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English (en)
Other versions
KR101640078B1 (ko
Inventor
박동주
박재성
김진성
윤주훈
Original Assignee
앰코 테크놀로지 코리아 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 앰코 테크놀로지 코리아 주식회사 filed Critical 앰코 테크놀로지 코리아 주식회사
Priority to KR1020140135819A priority Critical patent/KR101640078B1/ko
Priority to US14/877,373 priority patent/US9633966B2/en
Priority to TW104133175A priority patent/TWI619223B/zh
Publication of KR20160041581A publication Critical patent/KR20160041581A/ko
Application granted granted Critical
Publication of KR101640078B1 publication Critical patent/KR101640078B1/ko

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Abstract

본 발명은 적층형 반도체 패키지 및 이의 제조 방법에 관한 것으로서, 더욱 상세하게는 도전성 입자를 갖는 접착부재를 이용하여 하부 반도체 패키지와 인터포저 간의 본드라인 증대 및 접합력 향상을 도모할 수 있도록 한 적층형 반도체 패키지 및 이의 제조 방법에 관한 것이다.
즉, 본 발명은 도전성 입자를 포함하는 접착부재를 이용하여 하부 반도체 패키지와 인터포저 간을 도전 가능하게 연결하는 동시에 상호 접착시킬 수 있도록 함으로써, 하부 반도체 패키지와 인터포저 간의 전기적 신호 전달이 용이하게 이루어짐은 물론 하부 반도체 패키지와 인터포저 간의 본드라인 증대 및 접합력 향상을 도모할 수 있도록 한 적층형 반도체 패키지 및 이의 제조 방법을 제공하고자 한 것이다.

Description

적층형 반도체 패키지 및 이의 제조 방법{PACKAGE ON PACKAGE AND METHOD FOR MANUFACTURING THE SAME}
본 발명은 적층형 반도체 패키지 및 이의 제조 방법에 관한 것으로서, 더욱 상세하게는 도전성 입자를 갖는 접착부재를 이용하여 하부 반도체 패키지와 인터포저 간의 본드라인 증대 및 접합력 향상을 도모할 수 있도록 한 적층형 반도체 패키지 및 이의 제조 방법에 관한 것이다.
각종 전자기기 제품의 경량화, 소형화, 고속화, 다기능화, 고성능화 등 복합화 추세에 따라, 전자기기내 탑재되는 반도체 소자들에 대한 높은 신뢰성을 요구하고 있으며, 그에 따라 웨이퍼 레벨의 칩 스케일 패키지, 인터포저에 여러개의 칩을 한꺼번에 부착하여 기판에 탑재시킨 칩 적층형 패키지, 인터포저를 사이에 두고 상하로 적층되는 패키지 온 패키지(POP, Package On Package) 등 다양한 구조의 반도체 패키지가 개발되고 있다.
여기서, 종래의 팬-인 타입 패키지 온 패키지(Fan-in-POP)의 구성 및 그 제조 과정을 살펴보면 다음과 같다.
첨부한 도 5는 종래의 팬-인 타입 패키지 온 패키지를 나타낸 단면도이다.
도 5에서, 도면부호 100은 하부 반도체 패키지를 나타내고, 도면부호 300은 상부 반도체 패키지를 나타내며, 도면부호 200은 하부 반도체 패키지(100)와 상부 반도체 패키지(300)를 도전 가능하게 연결하는 인터포저를 나타낸다.
먼저, 상기 하부 반도체 패키지(100)를 제조하고자, 다수의 반도체 패키지 제조 영역이 가로 및 세로방향을 따라 등간격으로 형성된 스트립 기판(102)이 구비되고, 이 스트립 기판(102)의 각 반도체 패키지 제조영역의 중앙부에 반도체 칩(104)이 도전성 범프(106)를 매개로 전기적 신호 교환 가능하게 적층 부착된다.
연이어, 상기 반도체 칩(104)의 사방 주변 영역 즉, 기판(102)의 테두리 영역에 형성된 전도성패턴에 적층용 볼(108)이 융착되며, 이 적층용 볼(108)은 인터포저(200)와 전기적으로 연결하기 위한 수단이 된다.
이어서, 상기 기판(102)의 상면에 걸쳐 몰딩 컴파운드 수지(110)가 몰딩되는 단계가 진행되어, 반도체 칩(104)과 적층용 볼(108)이 외부로부터 보호 가능하게 봉지되는 상태가 되며, 바람직하게는 반도체 칩(104)에서 발생하는 열을 외부로 용이하게 방출시키기 위하여 몰딩 컴파운드 수지(110)의 상면과 반도체 칩(104)의 상면이 동일 평면을 이루도록 하여 반도체 칩(104)의 상면이 외부로 노출되도록 한다.
다음으로, 상기 몰딩 컴파운드 수지(110)의 상면에 레이저 가공에 의한 일정 깊이의 관통 몰드 비아(112: TMV, Through Mold Via)를 형성하는 단계가 진행되며, 이때 상기 적층용 볼(108)이 나타날 때까지의 깊이로 관통 몰드 비아(112)를 형성하게 된다.
이어서, 상기와 같이 제조된 하부 반도체 패키지(100)의 관통 몰드 비아(112)에 인터포저(200)를 도전 가능하게 적층하는 단계가 진행된다.
상기 인터포저(200)는 일반 인쇄회로기판(PCB)를 사용하거나, 반도체 칩과 동일한 실리콘 재질에 재배선 등의 회로배선이 형성된 구조로 구비되어, 하부 반도체 패키지(100)와 상부 반도체 패키지(300)를 도전 가능하게 연결하는 매개체 역할을 하고, 특히 원하는 방향으로 재배선 등을 형성하여 원하는 위치에 상부 반도체 패키지와의 접속을 위한 도전성 패드(202)가 형성된 구조로 구비된다.
즉, 도 4에 도시된 바와 같이, 상기 인터포저(200)는 그 상면에 상부 반도체 패키지(300)의 입출력단자(302)가 접속 연결되는 도전성 패드(202)가 노출되고, 저면에는 도전성 패드(202)와 비아홀(204) 또는 재배선(미도시됨)을 통하여 연결되는 볼랜드(206)가 형성된 구조로 구비된다.
이때, 상기 인터포저(200)의 볼랜드(206)에는 접속용 볼(208)이 융착되는 바, 이 접속용 볼(208)을 하부 반도체 패키지(100)의 관통 몰드 비아(112)내의 적층용 볼(108) 위에 적층하여 상호 융착시킴으로써, 하부 반도체 패키지(100)에 대한 인터포저(200)의 전기적 연결 및 적층이 이루어진다.
이어서, 상기 인터포저(200)의 도전성 패드(202) 위에 상부 반도체 패키지(300)의 입출력단자(302)를 융착시킴으로써, 상부 반도체 패키지(300)의 적층이 이루어진다.
참고로, 상기 인터포저(200)의 도전성 패드(202) 위에 상부 반도체 패키지(300)가 적층되지 않고, 복수의 반도체 칩이 적층 부착되기도 한다.
최종적으로, 상기 하부 반도체 패키지(100)의 기판(102) 저면에 노출된 볼랜드에 전자기기의 마더보드 등에 연결되는 솔더볼(109)을 융착시킴으로써, 인터포저(200)를 매개로 하부 및 상부 반도체 패키지(100,300)가 적층된 패키지 온 패키지가 완성된다.
그러나, 상기한 종래의 팬-인 타입 패키지 온 패키지는 다음과 같은 문제점이 있다.
첫째, 하부 반도체 패키지의 몰딩 컴파운드 수지의 상면과 인터포저의 저면 사이는 빈 공간으로 남게 되어, 하부 반도체 패키지와 인터포저 간의 접착력이 떨어지는 문제점이 있다.
둘째, 인터포저의 적층 전에 반도체 칩의 상면에 일종의 절연성 접착수단인 에폭시가 도포된 후, 인터포저의 적층시 가압력에 의하여 에폭시가 넓게 퍼지면서 반도체 칩과 인터포저를 상호 접착시키는 방법이 사용되기도 하지만, 반도체 칩과 동일 평면을 이루는 몰딩 컴파운드 수지의 상면과 인터포저의 저면 사이는 빈 공간으로 남게 되어, 하부 반도체 패키지와 인터포저 간의 접착력이 떨어지는 문제점이 있다.
셋째, 하부 반도체 패키지와 인터포저가 적층된 상태에서 접속용 볼과 적층용 볼을 서로 융착시키는 리플로우 공정 등에서 열이 발생되면, 하부 반도체 패키지와 인터포저 간을 잡아주는 별도의 수단이 없기 때문에 서로 다른 열팽창계수로 인하여 하부 반도체 패키지 및 인터포저의 각 에지부가 휘어지는 워피지 현상이 발생하고, 워피지 현상으로 인해 접속용 볼과 적층용 볼이 서로 떨어지는 단락 현상이 발생하는 문제점이 있다.
본 발명은 상기와 같은 점을 감안하여 안출한 것으로서, 도전성 입자를 포함하는 접착부재를 이용하여 하부 반도체 패키지와 인터포저 간을 도전 가능하게 연결하는 동시에 상호 접착시킬 수 있도록 함으로써, 하부 반도체 패키지와 인터포저 간의 전기적 신호 전달이 용이하게 이루어짐은 물론 하부 반도체 패키지와 인터포저 간의 본드라인 증대 및 접합력 향상을 도모할 수 있도록 한 적층형 반도체 패키지 및 이의 제조 방법을 제공하는데 그 목적이 있다.
상기한 목적을 달성하기 위하여 본 발명의 일 구현예는: 기판과, 기판의 상면 중앙부에 부착되는 반도체 칩과, 기판의 상면 테두리부에 부착되는 적층용 입출력단자와, 반도체 칩 및 적층용 입출력단자를 봉지하되 적층용 입출력단자의 상면이 노출되도록 기판 위에 몰딩되는 몰딩 컴파운드 수지로 구성되는 하부 반도체 패키지와; 상기 하부 반도체 패키지의 적층용 입출력단자와 도전 가능하게 연결되며 하부 반도체 패키지 위에 적층되는 인터포저를 포함하되, 상기 하부 반도체 패키지의 상면과 상기 인터포저의 저면 사이에 도전성 입자들을 함유한 접착부재를 부착하여, 접착부재내의 도전성 입자에 의하여 하부 반도체 패키지의 적층용 입출력단자와 인터포저의 도전성 패드가 도전 가능하게 연결되는 동시에 하부 반도체 패키지와 인터포저가 접착부재의 접착력에 의하여 접합되도록 한 것을 특징으로 하는 적층형 반도체 패키지를 제공한다.
바람직하게는, 상기 접착부재는 인터포저의 저면 전체에 걸쳐 미리 부착된 후, 하부 반도체 패키지에 대한 인터포저 적층시 하부 반도체 패키지의 상면에 접합되는 것을 특징으로 한다.
바람직하게는, 상기 접착부재는 도전성 입자가 함유된 일정 두께의 필름으로 채택된 것임을 특징으로 한다.
또는, 상기 접착부재는 도전성 입자가 함유된 페이스트로 채택된 것임을 특징으로 한다.
또한, 상기 적층용 입출력단자는 파인 피치가 가능한 구리 포스트 및 그 밖의 유사한 도전체로 채택된 것임을 특징으로 한다.
상기한 목적을 달성하기 위하여 본 발명의 다른 구현예는: 기판의 상면 중앙부에 반도체 칩을 도전 가능하게 부착하는 단계와; 상기 기판의 상면 테두리부에 적층용 입출력단자를 부착하는 단계와; 상기 반도체 칩 및 적층용 입출력단자가 봉지되도록 기판 위에 몰딩 컴파운드 수지를 오버 몰딩하는 단계와; 상기 적층용 입출력단자가 노출되도록 몰딩 컴파운드 수지의 상면을 균일하게 그라인딩하는 단계와; 인터포저의 저면에 도전성 입자를 함유하는 접착부재를 부착하는 단계와; 상기 인터포저에 부착된 접착부재를 하부 반도체 패키지의 상면에 걸쳐 도전 가능하게 부착하는 하부 반도체 패키지에 대한 인터포저 적층 단계; 를 포함하는 것을 특징으로 하는 적층형 반도체 패키지 제조 방법을 제공한다.
바람직하게는, 상기 적층용 입출력단자를 부착하는 단계에서, 파인 피치가 가능한 다수의 구리 포스트가 기판의 상면 테두리부에 형성된 도전성 패턴에 도전 가능하게 부착되는 것을 특징으로 한다.
특히, 상기 인터포저의 적층 단계에서, 상기 접착부재내의 도전성 입자에 의하여 하부 반도체 패키지의 적층용 입출력단자와 인터포저의 도전성 패드가 도전 가능하게 연결되는 동시에 하부 반도체 패키지와 인터포저가 접착부재의 접착력에 의하여 접합되는 것을 특징으로 한다.
또한, 상기 인터포저의 적층 단계에서, 하부 반도체 패키지와 인터포저 간의 접합이 이루어지도록 접착부재에 열을 가하는 과정과 압력을 가하는 과정이 동시에 진행되는 것을 특징으로 한다.
상기한 과제 해결 수단을 통하여, 본 발명은 다음과 같은 효과를 제공한다.
첫째, 도전성 입자를 포함하는 접착부재를 이용하여 하부 반도체 패키지와 인터포저 간을 도전 가능하게 연결하는 동시에 상호 접착시킬 수 있도록 함으로써, 하부 반도체 패키지와 인터포저 간의 전기적 신호 전달이 도전성 입자에 의하여 용이하게 이루어질 수 있다.
둘째, 도전성 입자를 포함하는 접착부재가 하부 반도체 패키지의 상면과 인터포저의 저면 전체에 걸쳐 부착됨에 따라, 하부 반도체 패키지와 인터포저 간의 본드라인 증대 및 접합력 향상을 도모할 수 있다.
셋째, 하부 반도체 패키지에 대한 인터포저의 본드라인 증대 및 접착력 향상에 따라, 인터포저와 하부 반도체 패키지 간을 접착부재가 잡아주는 상태가 되므로, 제조 공정 중 열에 의하여 인터포저 및 하부 반도체 패키지의 에지부 등이 휘어지는 워피지 현상을 방지할 수 있다.
넷째, 도전성 입자를 포함하는 접착부재를 적용할 때, 하부 반도체 패키지에 인터포저 적층을 위한 입출력단자를 파인 피치가 가능한 구리 포스트 및 그 밖의 유사한 도전체를 사용함에 따라, 적층용 입출력단자 간의 파인피치 구현이 가능한 잇점이 있다.
다섯째, 기존의 패키지 온 패키지의 경우, 하부 반도체 패키지에 적층용 볼을 부착하는 공정과, 인터포저에 접속용 볼을 부착하는 공정과, 적층용 볼을 노출시키도록 몰딩 컴파운드 수지에 레이저 가공에 의하여 관통 몰드 비아를 형성하는 공정 등 여러가지 공정이 진행되던 것과 달리, 본 발명은 몰딩 컴파운드 수지를 그라인딩하여 구리포스트를 노출시킨 다음, 구리 포스트 위에 접착부재를 매개로 인터포저를 도전 가능하게 연결하기만 하면 되므로 제조 공정수 축소가 가능한 잇점이 있다.
도 1은 본 발명의 일 실시예에 따른 적층형 반도체 패키지를 나타낸 단면도,
도 2는 본 발명의 일 실시예에 따른 적층형 반도체 패키지 제조 방법을 나타낸 단면도,
도 3은 본 발명에 따른 적층형 반도체 패키지의 도전성 입자가 함유된 접착부재에 의하여 하부 반도체 패키지와 인터포저가 도전 가능하게 연결되는 적층되는 원리를 나타낸 개략도,
도 4는 본 발명의 다른 실시예에 따른 적층형 반도체 패키지를 나타낸 단면도,
도 5는 종래의 적층형 반도체 패키지를 나타낸 단면도.
이하, 본 발명의 바람직한 실시예를 첨부도면을 참조로 상세하게 설명하기로 한다.
본 발명은 도전성 입자들을 함유한 접착부재를 이용하여 하부 반도체 패키지와 인터포저 간의 전기적 신호 전달이 용이하게 이루어짐은 물론 하부 반도체 패키지와 인터포저 간의 본드라인 증대 및 접합력을 향상시킬 수 있도록 한 점에 주안점이 있다.
참고로, 여기서는 도전성 입자들을 함유한 접착부재를 이용하여 하부 반도체 패키지와 인터포저 간을 적층하는 패키지 온 패키지 구조를 하나의 실시예로 설명하지만, 기판과 기판, 기판과 반도체 칩, 반도체 칩과 반도체 칩 등 하나의 패키지내에서 도전 가능하게 연결되는 구성요소들도 도전성 입자들을 함유한 접착부재를 사용하여 도전 가능하게 연결할 수 있음을 밝혀둔다.
첨부한 도 1은 본 발명의 일실시예에 따른 적층형 반도체 패키지를 나타낸 단면도이고, 도 2는 본 발명의 일 실시예에 따른 적층형 반도체 패키지 제조 방법을 나타낸 단면도이다.
도 1 및 도 2에서, 도면부호 100은 하부 반도체 패키지를 나타내고, 도면부호 200은 하부 반도체 패키지(100)와 상부 반도체 패키지를 도전 가능하게 연결하는 인터포저를 나타낸다.
먼저, 상기 하부 반도체 패키지(100)를 제조하고자, 다수의 반도체 패키지 제조 영역이 가로 및 세로방향을 따라 등간격으로 형성된 스트립 기판(102)이 구비되고, 이 스트립 기판(102)의 각 반도체 패키지 제조영역의 중앙부에 반도체 칩(104)이 도전성 범프(106)를 매개로 전기적 신호 교환 가능하게 적층 부착된다.
연이어, 상기 반도체 칩(104)의 사방 주변 영역 즉, 기판(102)의 테두리 영역에 형성된 전도성패턴에 적층용 입출력단자(120)가 융착되며, 이 적층용 입출력단자(120)는 인터포저(200)와 전기적으로 연결하기 위한 수단이 된다.
바람직하게는, 상기 적층용 입출력단자(120)는 파인 피치가 가능한 구리 포스트 및 이와 유사한 형상의 도전금속체로 채택된다.
이어서, 상기 기판(102)의 상면에 걸쳐 몰딩 컴파운드 수지(110)가 몰딩되는 단계가 진행되어, 반도체 칩(104)과 적층용 입출력단자(120)가 외부로부터 보호 가능하게 봉지되는 상태가 되며, 바람직하게는 반도체 칩(104)에서 발생하는 열을 외부로 용이하게 방출시키기 위하여 몰딩 컴파운드 수지(110)의 상면과 반도체 칩(104)의 상면이 동일 평면을 이루도록 하여 반도체 칩(104)의 상면이 외부로 노출되도록 한다.
연이어, 상기 인터포저(200)를 하부 반도체 패키지(100) 위에 적층할 때, 전기적 신호 교환을 위한 적층용 입출력단자(120)와 도전 가능하게 연결되어야 하며, 이를 위해 적층용 입출력단자(120)의 상면이 외부로 노출되도록 몰딩 컴파운드 수지(110)의 상면을 균일하게 그라인딩하는 단계가 진행된다.
한편, 기존의 패키지 온 패키지의 경우, 하부 반도체 패키지에 적층용 볼을 부착하는 공정과, 인터포저에 접속용 볼을 부착하는 공정과, 적층용 볼을 노출시키도록 몰딩 컴파운드 수지에 레이저 가공에 의하여 관통 몰드 비아를 형성하는 공정 등 여러가지 공정이 진행되던 것과 달리, 본 발명은 몰딩 컴파운드 수지를 그라인딩하여 구리포스트를 노출시킨 다음, 구리 포스트 위에 접착부재를 매개로 인터포저를 도전 가능하게 연결하기만 하면 되므로 제조 공정수 축소를 실현할 수 있다.
이를 위해, 상기 인터포저(200)의 저면에 도전성 입자(212)를 함유하는 접착부재(210)를 부착하는 단계가 진행된다.
즉, 상기 인터포저(200)의 저면에 하부 반도체 패키지(100) 위에 적층 부착은 물론 도전 가능하게 연결하기 위한 수단으로서, 도전성 입자(212)를 함유하는 접착부재(210)가 부착된다.
바람직하게는, 상기 접착부재(210)는 도전성 입자가 함유된 일정 두께의 고분자 필름으로 채택되거나, 또는 상기 접착부재(210)는 도전성 입자가 함유된 고분자 페이스트로 채택된다.
따라서, 상기 접착부재(210)는 인터포저(200)의 저면 전체에 걸쳐 미리 부착된 후, 하부 반도체 패키지(100)에 대한 인터포저(200)의 적층시 하부 반도체 패키지(100)의 상면에 접착된다.
보다 상세하게는, 상기 하부 반도체 패키지(100)의 상면 위에 접착부재(210)가 부착된 인터포저(200)를 적층 부착함으로써, 접착부재(210)내의 도전성 입자(212)에 의하여 하부 반도체 패키지(100)의 적층용 입출력단자(120)와 인터포저(200)의 볼랜드(206)가 도전 가능하게 연결되는 동시에 하부 반도체 패키지(100)와 인터포저(200)가 접착부재(210)의 접착력에 의하여 상호 접합된다.
이때, 상기 하부 반도체 패키지(100)에 대한 인터포저(200)의 적층 단계에서, 상기 하부 반도체 패키지(100)와 인터포저(200)가 접착부재(210)의 접착력에 의하여 상호 접합되는 상태가 됨은 물론, 첨부한 도 3에서 보듯이 상기 접착부재(210)내의 도전성 입자(212)에 의하여 하부 반도체 패키지(100)의 적층용 입출력단자(120)와 인터포저(200)의 볼랜드(206)가 도전 가능하게 연결되는 상태가 된다.
바람직하게는, 상기 인터포저(200)의 적층 단계에서, 하부 반도체 패키지(100)와 인터포저(200) 간의 접합이 이루어지도록 접착부재(210)에 열을 가하는 과정과 압력을 가하는 과정이 동시에 진행됨으로써, 열에 의하여 필름 또는 페이스트로 채택된 접착부재(210)가 녹으면서 하부 반도체 패키지(100)와 인터포저(200) 간을 접합시키게 되고, 이와 함께 첨부한 도 3에서 보듯이 압력에 의하여 접착부재(210)에 함유된 도전성 입자(212)가 하부 반도체 패키지(100)의 적층용 입출력단자(120)와 인터포저(200)의 볼랜드(206) 간을 도전 가능하게 연결하는 상태가 된다.
이와 같이, 도전성 입자(212)를 포함하는 접착부재(210)를 이용하여 하부 반도체 패키지(100)와 인터포저(200) 간을 도전 가능하게 연결하는 동시에 상호 접착시킬 수 있도록 함으로써, 하부 반도체 패키지(100)와 인터포저(200) 간의 전기적 신호 전달이 도전성 입자(212)에 의하여 용이하게 이루어질 수 있고, 또한 접착부재(210)가 하부 반도체 패키지(100)의 상면과 인터포저(200)의 저면 전체에 걸쳐 부착됨에 따라, 하부 반도체 패키지(100)와 인터포저(200) 간의 본드라인 증대 및 접합력 향상을 도모할 수 있으며, 그에 따라 인터포저 및 하부 반도체 패키지의 에지부 등이 휘어지는 워피지 현상을 방지할 수 있다.
한편, 첨부한 도 4에서 보듯이 상기한 하부 반도체 패키지(100) 위에 인터포저를 매개로 상부 반도체 패키지를 적층하지 않고, 도전성 입자(212)를 포함하는 접착부재(210)를 매개로 상부 반도체 패키지(300)를 바로 적층시킬 수 있다.
이를 위해, 먼저 기판(102)과, 기판(102)의 상면 중앙부에 부착되는 반도체 칩(104)과, 기판(102)의 상면 테두리부에 부착되는 적층용 입출력단자(120)와, 반도체 칩(104) 및 적층용 입출력단자(120)를 봉지하되 적층용 입출력단자(120)의 상면이 노출되도록 기판(102) 위에 몰딩되는 몰딩 컴파운드 수지(110)로 구성되는 하부 반도체 패키지(100)를 구비한 상태에서, 이 하부 반도체 패키지(100)의 상면에 걸쳐 도전성 입자(212)를 함유하는 접착부재(210)를 부착한다.
이어서, 상부 반도체 패키지(예를 들어, 볼랜드를 갖는 볼 그리드 어레이 패키지)를 접착부재(210) 위에 접합시켜 적층시킨다.
이때, 접착부재(210)내의 도전성 입자(212)에 의하여 하부 반도체 패키지(100)의 적층용 입출력단자(120)와 상부 반도체 패키지(300)의 볼랜드가 도전 가능하게 연결되는 동시에 하부 반도체 패키지(100)와 상부 반도체 패키지(300)가 접착부재(210)의 접착력에 의하여 상호 접합되는 상태가 된다.
이와 같이, 도전성 입자를 포함하는 접착부재를 이용하여 하부 반도체 패키지 위에 상부 반도체 패키지를 도전 가능하게 연결하는 동시에 상호 접착시킬 수 있도록 함으로써, 하부 반도체 패키지와 상부 반도체 패키지 간의 전기적 신호 전달이 도전성 입자에 의하여 용이하게 이루어질 수 있다.
100 : 하부 반도체 패키지 102 : 기판
104 : 반도체 칩 106 : 도전성 범프
108 : 적층용 볼 109 : 솔더볼
110 : 몰딩 컴파운드 수지 112 : 관통 몰드 비아
120 : 적층용 입출력단자 200 : 인터포저
202 : 도전성 패드 204 : 비아홀
206 : 볼랜드 208 : 접속용 볼
210 : 접착부재 212 : 도전성 입자
300 : 상부 반도체 패키지 302 : 입출력단자

Claims (10)

  1. 기판(102)과, 기판(102)의 상면 중앙부에 부착되는 반도체 칩(104)과, 기판(102)의 상면 테두리부에 부착되는 적층용 입출력단자(120)와, 반도체 칩(104) 및 적층용 입출력단자(120)를 봉지하되 적층용 입출력단자(120)의 상면이 노출되도록 기판(102) 위에 몰딩되는 몰딩 컴파운드 수지(110)로 구성되는 하부 반도체 패키지(100)와; 상기 하부 반도체 패키지(100)의 적층용 입출력단자(120)와 도전 가능하게 연결되며 하부 반도체 패키지(100) 위에 적층되는 인터포저(200)를 포함하되,
    상기 하부 반도체 패키지(100)의 상면과 상기 인터포저(200)의 저면 사이에 도전성 입자(212)들을 함유한 접착부재(210)를 부착하여, 접착부재(210)내의 도전성 입자(212)에 의하여 하부 반도체 패키지(100)의 적층용 입출력단자(120)와 인터포저(200)의 도전성 패드(202)가 도전 가능하게 연결되는 동시에 하부 반도체 패키지(100)와 인터포저(200)가 접착부재(210)의 접착력에 의하여 접합되도록 한 것을 특징으로 하는 적층형 반도체 패키지.
  2. 청구항 1에 있어서,
    상기 접착부재(210)는 인터포저(200)의 저면 전체에 걸쳐 미리 부착된 후, 하부 반도체 패키지(100)에 대한 인터포저(200)의 적층시 하부 반도체 패키지(100)의 상면에 접합되는 것을 특징으로 하는 적층형 반도체 패키지.
  3. 청구항 1 또는 청구항 2에 있어서,
    상기 접착부재(210)는 도전성 입자가 함유된 일정 두께의 필름으로 채택된 것임을 특징으로 하는 적층형 반도체 패키지.
  4. 청구항 1 또는 청구항 2에 있어서,
    상기 접착부재(210)는 도전성 입자가 함유된 페이스트로 채택된 것임을 특징으로 하는 적층형 반도체 패키지.
  5. 청구항 1에 있어서,
    상기 적층용 입출력단자(120)는 파인 피치가 가능한 구리 포스트 및 이와 유사한 형상의 도전금속체로 채택된 것임을 특징으로 하는 적층형 반도체 패키지.
  6. 청구항 1에 있어서,
    상기 하부 반도체 패키지(100) 위에 인터포저없이 상부 반도체 패키지(300)를 곧바로 적층되게 부착하여, 접착부재(210)내의 도전성 입자(212)에 의하여 하부 반도체 패키지(100)의 적층용 입출력단자(120)와 상부 반도체 패키지(300)의 볼랜드가 도전 가능하게 연결되는 동시에 하부 반도체 패키지(100)와 상부 반도체 패키지(300)가 접착부재(210)의 접착력에 의하여 접합되도록 한 것을 특징으로 하는 적층형 반도체 패키지.
  7. 기판(102)의 상면 중앙부에 반도체 칩(104)을 도전 가능하게 부착하는 단계와;
    상기 기판(102)의 상면 테두리부에 적층용 입출력단자(120)를 도전 가능하게 부착하는 단계와;
    상기 반도체 칩(104) 및 적층용 입출력단자(120)가 봉지되도록 기판(102) 위에 몰딩 컴파운드 수지(110)를 오버 몰딩하는 단계와;
    상기 적층용 입출력단자(120)가 노출되도록 몰딩 컴파운드 수지(110)의 상면을 균일하게 그라인딩하는 단계와;
    인터포저(200)의 저면에 도전성 입자(212)를 함유하는 접착부재(210)를 부착하는 단계와;
    상기 인터포저(200)에 부착된 접착부재(210)를 하부 반도체 패키지(100)의 상면에 걸쳐 도전 가능하게 부착하는 하부 반도체 패키지(100)에 대한 인터포저(200) 적층 단계;
    를 포함하는 것을 특징으로 하는 적층형 반도체 패키지 제조 방법.
  8. 청구항 7에 있어서,
    상기 적층용 입출력단자(120)를 부착하는 단계에서, 파인 피치가 가능한 다수의 구리 포스트가 기판(102)의 상면 테두리부에 형성된 도전성 패턴에 도전 가능하게 부착되는 것을 특징으로 하는 적층형 반도체 패키지 제조 방법.
  9. 청구항 7에 있어서,
    상기 인터포저(200)의 적층 단계에서, 상기 접착부재(210)내의 도전성 입자(212)에 의하여 하부 반도체 패키지(100)의 적층용 입출력단자(120)와 인터포저(200)의 도전성 패드(202)가 도전 가능하게 연결되는 동시에 하부 반도체 패키지(100)와 인터포저(200)가 접착부재(210)의 접착력에 의하여 접합되는 것을 특징으로 하는 적층형 반도체 패키지 제조 방법.
  10. 청구항 7에 있어서,
    상기 인터포저(200)의 적층 단계에서, 하부 반도체 패키지(100)와 인터포저(200) 간의 접합이 이루어지도록 접착부재(210)에 열을 가하는 과정과 압력을 가하는 과정이 동시에 진행되는 것을 특징으로 하는 적층형 반도체 패키지 제조 방법.
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