KR20140059132A - 패턴 형성 방법 및 블록 공중합체 - Google Patents
패턴 형성 방법 및 블록 공중합체 Download PDFInfo
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- KR20140059132A KR20140059132A KR1020130132756A KR20130132756A KR20140059132A KR 20140059132 A KR20140059132 A KR 20140059132A KR 1020130132756 A KR1020130132756 A KR 1020130132756A KR 20130132756 A KR20130132756 A KR 20130132756A KR 20140059132 A KR20140059132 A KR 20140059132A
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Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
- H01L21/3081—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their composition, e.g. multilayer masks, materials
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/0002—Lithographic processes using patterning methods other than those involving the exposure to radiation, e.g. by stamping
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
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Abstract
Description
도 2a 내지 도 2c는 상기 실시양태에 의한 패턴 형성 방법을 도시한 평면 개요도이며;
도 3a 내지 도 3d는 참고예에 의한 패턴 형성 방법을 도시한 횡단면 개요도이고;
도 4a 내지 도 4f는 상기 실시양태에 의한 패턴 형성을 도시한 횡단면 개요도이며;
도 5a 내지 도 5f는 상기 실시양태에 의한 패턴 형성을 도시한 평면 개요도이고;
도 6은 아크릴의 측쇄의 탄소 원자 수에 대한 물 접촉각을 나타낸 그래프이며;
도 7a 내지 도 7f는 상기 실시양태에 의한 패턴 형성 방법에서 상-분리를 도시한 AFM 이미지이고;
도 8은 상기 실시양태에 의한 폴리스티렌의 측쇄의 탄소 원자 수와 건식 에칭 내성 사이의 엄지손가락 원리를 나타낸 그래프이다.
20h, 200h: 개구부 30, 300: 블록 공중합체 층
31: 제1층 32: 제2층
40: 실린더 구조물 120: C 막
130: Si 옥시드 막 132: 금속 배선
200: 레지스트 물리적 가이드
Claims (13)
- 하지층상에 제공되는 레지스트 층의 개구부에 폴리스티렌 유도체 및 측쇄상에 6개 이상의 탄소 원자를 갖는 아크릴을 함유하는 블록 공중합체 층을 형성하는 단계;
상기 블록 공중합체 층을 상-분리시킴으로써 상기 개구부에 폴리스티렌 유도체를 함유하는 제1 층 및 아크릴을 함유하는 제2 층을 형성하는 단계; 및
상기 제2 층을 제거하는 단계를 포함하는, 패턴 형성 방법. - 제1항에 있어서 상기 제1 층 및 제2 층을 형성하는 단계가 상기 개구부에 상기 제1 층 및 상기 제2 층을 포함하는 실린더 구조물을 형성하는 것을 포함하는 방법.
- 제1항에 있어서, 상기 폴리스티렌 유도체가 폴리스티렌을 포함하고, 상기 아크릴이 폴리(헥실 메타크릴레이트)를 포함하는 것인 방법.
- 제1항에 있어서, 상기 폴리스티렌 유도체가 폴리스티렌, 폴리히드록시스티렌, 및 폴리(2-비닐피리딘) 중 하나인 방법.
- 제1항에 있어서, 상기 아크릴이 폴리(n-헥실 메타크릴레이트)(PnHMA), 폴리(n-헵틸 메타크릴레이트), 폴리(n-옥틸 메타크릴레이트), 폴리(n-노닐 메타크릴레이트), 폴리(n-데실 메타크릴레이트), 폴리(n-운데실 메타크릴레이트), 폴리(라우릴 메타크릴레이트)(PnLMA), 폴리(옥타데실 메타크릴레이트)(PnOMA), 폴리(n-헥실 아크릴레이트), 폴리(n-헵틸 아크릴레이트), 폴리(n-옥틸 아크릴레이트), 폴리(n-노닐 아크릴레이트), 폴리(n-데실 아크릴레이트), 폴리(n-운데실 아크릴레이트), 폴리(라우릴 아크릴레이트), 및 폴리(n-옥타데실 아크릴레이트) 중 하나인 방법.
- 제1항에 있어서, 상기 블록 공중합체 층을 형성하는 단계 이전에 상기 레지스트 층을 형성하는 단계를 더 포함하며,
상기 레지스트 층을 형성하는 단계는 상기 레지스트 층을 가교시켜서, 상기 레지스트 층을 상기 개구부가 상기 레지스트 층에 형성된 후에 상기 블록 공중합체 층을 용해하기 위한 용매에 불용화시키는 것을 포함하는 방법. - 제6항에 있어서, 상기 용매가 톨루엔, 크실렌, 메시틸렌, 시클로헥산온, 아세톤, 에틸 메틸 케톤, 메틸 이소부틸 케톤, 메틸 셀로솔브TM, 메틸 셀로솔브TM 아세테이트, 에틸 셀로솔브TM 아세테이트, 부틸 셀로솔브TM 아세테이트, 테트라히드로푸란, 및 클로로포름으로 이루어진 군 중에서 선택된 1종 이상인 방법.
- 제1항에 있어서, 상기 하지층은 실리콘 화합물을 함유하는 제3 층 및 상기 제3 층 하부에 제공된 가공하고자 하는 막을 포함하고,
상기 방법은 상기 레지스트 층 및 상기 제1 층을 마스크로서 사용함으로써 상기 제3 층을 에칭하는 단계; 및 상기 에칭된 제3 층을 마스크로서 사용함으로써 상기 제3층 하부에 제공된 가공하고자 하는 막을 에칭하여, 상기 가공하고자 하는 에칭된 막의 패턴을 형성하는 단계를 더 포함하는 방법. - 제1항에 있어서, 상기 하지층은 실리콘 화합물을 함유하는 제3 층 및 상기 제3 층 하부에 제공된 가공하고자 하는 막을 포함하고,
상기 방법은 상기 제3 층과 상기 가공하고자 하는 막 사이에 유기 막을 형성하는 단계; 상기 레지스트 층 및 상기 제1 층을 마스크로서 사용함으로써 상기 제3 층을 에칭하는 단계; 및 상기 제3 층을 마스크로서 사용함으로써 상기 유기 막을 에칭하는 단계를 더 포함하는 방법. - 하지층상에 제공되는 레지스트 층의 개구부에 폴리스티렌 유도체 및 측쇄상에 6개 이상의 탄소 원자를 갖는 아크릴을 함유하는 블록 공중합체 층을 형성하는 단계; 상기 블록 공중합체 층을 상-분리시킴으로써 상기 개구부에 폴리스티렌 유도체를 함유하는 제1 층 및 아크릴을 함유하는 제2 층을 형성하는 단계; 및 상기 제2 층을 제거하는 단계를 포함하는 패턴 형성 방법에서 상기 블록 공중합체 층에 사용되는 블록 공중합체.
- 제10항에 있어서, 상기 제1 층 및 제2 층을 형성하는 단계가 상기 개구부에 상기 제1 층 및 상기 제2 층을 포함하는 실린더 구조물을 형성하는 것을 포함하는 블록 공중합체.
- 제10항에 있어서, 상기 폴리스티렌 유도체의 부피 분율과 상기 아크릴의 부피 분율이 다른 것인 블록 공중합체.
- 제10항에 있어서, 상기 폴리스티렌 유도체가 폴리스티렌을 포함하고, 상기 아크릴이 폴리(헥실 메타크릴레이트)를 포함하는 것인 블록 공중합체.
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JP6189131B2 (ja) | 2013-08-01 | 2017-08-30 | 株式会社東芝 | 半導体装置およびその製造方法 |
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