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KR20100119446A - Semiconductor device with buried gate and method for manufacturing the same - Google Patents

Semiconductor device with buried gate and method for manufacturing the same Download PDF

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Publication number
KR20100119446A
KR20100119446A KR1020090038556A KR20090038556A KR20100119446A KR 20100119446 A KR20100119446 A KR 20100119446A KR 1020090038556 A KR1020090038556 A KR 1020090038556A KR 20090038556 A KR20090038556 A KR 20090038556A KR 20100119446 A KR20100119446 A KR 20100119446A
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South Korea
Prior art keywords
trench
active region
buried gate
buried
isolation layer
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KR1020090038556A
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Korean (ko)
Inventor
김광옥
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주식회사 하이닉스반도체
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Priority to KR1020090038556A priority Critical patent/KR20100119446A/en
Publication of KR20100119446A publication Critical patent/KR20100119446A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/06—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials
    • H01L21/10—Preliminary treatment of the selenium or tellurium, its application to the foundation plate, or the subsequent treatment of the combination
    • H01L21/108—Provision of discrete insulating layers, i.e. non-genetic barrier layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
    • H01L21/46—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428
    • H01L21/461—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/469—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After-treatment of these layers
    • H01L21/4757—After-treatment
    • H01L21/47573—Etching the layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Life Sciences & Earth Sciences (AREA)
  • Biotechnology (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Semiconductor Memories (AREA)

Abstract

PURPOSE: A semiconductor device with a buried gate and a method for manufacturing the same are provided to reduce the resistance of a buried gate by forming the shape of a trench at an active region to be isotropic to extend the bury area of the buried gate. CONSTITUTION: A semiconductor substrate(21) has an active region which is defined by an element isolation film(22). Trench(24A, 24B) is formed by etching the active region and the element isolation film at the same time. A gate insulating layer(25) is formed in the trench sidewall of the active region. A buried gate(26) is buried at a part of the trench.

Description

Semiconductor device with buried gate and manufacturing method therefor {SEMICONDUCTOR DEVICE WITH BURIED GATE AND METHOD FOR MANUFACTURING THE SAME}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device manufacturing method, and more particularly, to a semiconductor device having a buried gate and a manufacturing method thereof.

As the size of semiconductor devices such as DRAM is reduced, patterning of gate lines becomes difficult, and it is difficult to secure capacitance (Cs). In order to solve the problem of patterning of the gate line and securing the capacitance (Cs), development of a buried gate line (BG) structure is being actively progressed.

In the buried gate structure, there is no problem of gate line patterning, and by reducing the parasitic capacitance between the gate line and the bit line, capacitive Cs can be solved.

1 is a diagram illustrating a semiconductor device having a buried gate according to the related art.

Referring to FIG. 1, an active region 13 is defined on a semiconductor substrate 11 by an isolation layer 12, and the trench 14A having a predetermined depth is etched by simultaneously etching the isolation layer 12 and the active region 13. , 14B) is formed. The gate insulating film 15 is formed on the surface of the trench 14A formed in the active region 13. A buried gate 16 is formed on the gate insulating film 15 to partially fill the trenches 14A and 14B, and a hard mask film 17 is formed on the semiconductor substrate 11.

In the prior art of FIG. 1, the gate conductive film is deposited on the entire surface until the trenches 14A and 14B are filled to form the buried gate 16, and then chemical mechanical polishing and etch back are sequentially performed.

In the related art, since the trenches 14A and 14B to which the buried gate 16 is buried are formed by simultaneously etching the device isolation layer and the active region, a critical dimension (CD) and an active region formed in the device isolation layer 12 are formed. The line widths formed at the same are the same (see CD1).

However, in the related art, since the gate insulating layer 15 is formed by oxidizing the surface of the trench 14A of the active region 13, the line width of the trench 14A in which the buried gate 16 is to be filled is reduced ('CD2'). Reference). As a result, the buried area of the buried gate 16 is reduced, resulting in an increase in resistance of the buried gate 16.

SUMMARY OF THE INVENTION The present invention has been proposed to solve the above problems of the prior art, and an object of the present invention is to provide a semiconductor device having a buried gate capable of increasing the buried area of the buried gate and reducing the resistance of the buried gate.

A semiconductor device of the present invention for achieving the above object is a semiconductor substrate in which an active region is defined by a device isolation film; A trench formed by simultaneously etching the active region and the device isolation layer; A gate insulating film formed on sidewalls of the trench in the active region; And a buried gate partially filling the trench, wherein the trench has a larger line width formed in the active region than a line width formed in the device isolation layer.

Preferably, the depth of the trench formed in the active region and the depth of the trench formed in the device isolation layer have substantially the same depth, or the depth of the trench formed in the device isolation layer is deeper than the depth of the trench formed in the active region. It features.

Preferably, the sidewalls of the trenches formed in the active region have an isotropic profile, and the sidewalls of the trenches formed in the active region have a fully isotropic profile or a Boeing isotropic profile. Has

Preferably, the trench formed in the active region has a bulb type.

In the present invention described above, when the trench to be filled with the buried gate is buried, the buried gate is formed by making the line width of the trench formed in the active region larger than the trench formed in the device isolation layer or by forming the shape of the trench formed in the active region in an isotropic manner. The buried area to be buried is increased, thereby reducing the resistance of the buried gate.

Hereinafter, the preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .

FIG. 2A is a diagram illustrating a structure of a semiconductor device having a buried gate according to a first embodiment of the present invention, and FIG. 2B is a plan view of the semiconductor device with a trench according to FIG. 2A.

2A and 2B, the active region 23 is defined by the device isolation layer 22 on the semiconductor substrate 21, and the device isolation layer 22 and the active region 23 are simultaneously etched to have a predetermined depth. Trenchs 24A and 24B are formed. The gate insulating film 25 is formed on the surface of the trench 24A formed in the active region 23. A buried gate 26 partially filling the trenches 24A and 24B is formed on the gate insulating layer 25, and a hard mask layer serving as an etch barrier for forming the trenches 24A and 24B is formed on the semiconductor substrate 21. 27 is formed. The hard mask film 27 is an oxide film or a nitride film, and the thickness thereof is 200 kPa or more.

In detail, the trench 24A formed in the active region 23 and the trench 24B formed in the device isolation layer 22 have the same depth (D1 = D2). For example, the depths of the trenches 24A and 24B are secured to 300 kPa or more.

The line width CD12 of the trench 24A formed in the active region 23 is larger than the line width CD11 of the trench 24B formed in the device isolation film 22. Thus, after the gate insulating film 25 is formed, the line width CD13 of the trench 24A formed in the active region is equal to the line width CD11 of the trench formed in the device isolation film (CD11 = CD13). That is, in consideration of the line width expected to be increased by the thickness of the gate insulating film, the line width of the trench 24A formed in the active region at the time of initial trench formation is made larger than the line width of the trench 24B formed in the device isolation film.

As such, varying the line width of the trench may be controlled during the trench mask process. When patterning the trenches using the photosensitive film, the line width of the trench 24B formed in the device isolation layer 22 may be smaller than the line width of the trench 24A formed in the active region 23. Here, the trench line width formed in the device isolation film 22 is defined to be the same as the trench line width of the prior art, and accordingly, the present invention is a method of increasing the line width of the trench defined in the active region than the prior art.

As described above, the first embodiment increases the line width of the trench 24A formed in the active region 23, thereby increasing the buried area in which the buried gate 26 is to be buried. Can reduce the resistance.

In the first embodiment, the buried gate 26 can further lower the resistance of the buried gate 26 by using singly or mixed materials selected from the group consisting of W, TiN, WN, WSi, Ru, Al, and Cu. have.

3 is a diagram illustrating a structure of a semiconductor device having a buried gate according to a second embodiment of the present invention.

Referring to FIG. 3, an active region 33 is defined on the semiconductor substrate 31 by the device isolation layer 32, and the trench 34A having a predetermined depth is etched by simultaneously etching the device isolation layer 32 and the active region 33. 34B) is formed. A gate insulating film 35 is formed on the surface of the trench 34A formed in the active region 33. A buried gate 36 is formed on the gate insulating layer 35 to partially fill the trenches 34A and 34B. A hard mask layer 37 is formed on the semiconductor substrate to serve as an etch barrier for forming the trench. The hard mask film 37 is an oxide film or a nitride film, the thickness of which is 200 kPa or more.

In detail, the trench 34A formed in the active region and the trench 34B formed in the device isolation layer have different depths. For example, the trench formed in the device isolation layer is deeper than the trench formed in the active region (D21 <D22). For example, the depth of the trench 24A formed in the active region is ensured to be 300 µm or more, and the trench formed in the device isolation layer is 200 µm or more larger than the trench formed in the active region. As described above, since the trench 34B formed in the device isolation layer is deeper than the trench 34A formed in the active region, the semiconductor device according to the second embodiment has a saddle fin structure.

The line width CD22 of the trench 34A formed in the active region 33 is larger than the line width CD21 of the trench 34B formed in the device isolation film 32. Accordingly, after the gate insulating film 25 is formed, the line width CD23 of the trench 24A formed in the active region is equal to the line width CD21 of the trench formed in the device isolation film (CD21 = CD23). That is, in consideration of the line width expected to be increased by the thickness of the gate insulating film, the line width of the trench 34A formed in the active region at the time of initial trench formation is formed to be larger than the line width of the trench 34B formed in the device isolation film.

As such, varying the line width of the trench may be controlled during the trench mask process. When patterning the trench using the photosensitive film, the line width of the trench 34B formed in the device isolation layer 32 may be smaller than the line width of the trench 34A formed in the active region 33. Here, the trench line width formed in the device isolation film 32 is defined to be the same as the trench line width of the prior art. Accordingly, the present invention is a method of increasing the line width of the trench defined in the active region than the prior art.

As described above, in the second embodiment, by increasing the line width of the trench 34A formed in the active region, the buried area in which the buried gate 36 is buried increases, thereby reducing the resistance of the buried gate 36. You can.

In the second embodiment, the buried gate 36 may further lower the resistance of the buried gate by using a material selected from the group consisting of W, TiN, WN, WSi, Ru, Al, and Cu alone or in combination.

4 is a diagram illustrating a structure of a semiconductor device having a buried gate according to a third embodiment of the present invention.

Referring to FIG. 4, the active region 43 is defined by the isolation layer 42 on the semiconductor substrate 41, and the trench 44A having a predetermined depth is formed by simultaneously etching the isolation layer 42 and the active region 43. , 44B). The gate insulating film 45 is formed on the surface of the trench 44A formed in the active region 43. A buried gate 46 partially filling the trenches 44A and 44B is formed on the gate insulating layer 45, and a hard mask layer 47 is formed on the semiconductor substrate to serve as an etch barrier for forming the trench. The hard mask film 47 is an oxide film or a nitride film, and the thickness thereof is 200 kPa or more.

In detail, the depth of the trench 44B formed in the device isolation layer is deeper than the trench 44A formed in the active region (D31 <D32). For example, the depth of the trench 44A formed in the active region is ensured to be 300 µm or more, and the trench formed in the device isolation film is secured to 200 µm or more than the trench formed in the active region.

The line width CD32 of the trench 44A formed in the active region 43 is larger than the line width CD31 of the trench 44B formed in the device isolation layer 42. Accordingly, after the gate insulating layer 45 is formed, the line width CD33 of the trench 44A formed in the active region is equal to or larger than the line width CD31 of the trench formed in the device isolation layer (CD31 ≦ CD33). That is, in consideration of the line width expected to be increased by the thickness of the gate insulating layer, the line width of the trench formed in the active region at the time of the first trench formation is made larger than the line width of the trench formed in the device isolation layer. In addition, the trench 44A formed in the active region 43 has a fully isotropic profile, which is obtained by isotropically etching the active region 43 in the state where the hard mask film 47 is formed.

As such, varying the line width of the trench may be controlled during the trench mask process. When patterning the trench by using the photosensitive film, the line width of the trench 44B formed in the device isolation layer 42 may be smaller than the line width of the trench 44A formed in the active region 43. Here, the trench line width formed in the device isolation layer 42 is defined to be the same as the trench line width of the prior art. Accordingly, the present invention is a method of increasing the line width of the trench defined in the active region than the prior art.

As described above, the third embodiment increases the line width of the trench 44A formed in the active region 43, thereby increasing the buried area in which the buried gate 46 is buried. Can reduce the resistance.

In the third embodiment, the buried gate 46 can further lower the resistance of the buried gate 46 by using a material selected from the group consisting of W, TiN, WN, WSi, Ru, Al, and Cu alone or in combination. have.

5 is a diagram illustrating a structure of a semiconductor device having a buried gate according to a fourth embodiment of the present invention.

Referring to FIG. 5, the active region 53 is defined on the semiconductor substrate 51 by the device isolation layer 52, and the device isolation layer 52 and the active region 53 are simultaneously etched to provide a twist of a certain depth. 54A and 54B are formed. The gate insulating film 55 is formed on the surface of the trench 54A formed in the active region 53. A buried gate 56 is formed on the gate insulating layer 55 to partially fill the trenches 54A and 54B, and a hard mask layer 57 is formed on the semiconductor substrate to serve as an etch barrier for forming the trench. The hard mask film 57 is an oxide film or a nitride film and has a thickness of 200 GPa or more.

In detail, the depth of the trench 54B formed in the device isolation layer is deeper than that of the trench 54A formed in the active region (D41 <D42). For example, the depth of the trench 54A formed in the active region is ensured to be 300 µm or more, and the trench formed in the device isolation layer is 200 µm or more larger than the trench formed in the active region.

In addition, the trench 54A formed in the active region 53 has a Bow isotropic shape, that is, a Bowing isotropic profile having a rounded sidewall and a bottom profile, and a device isolation layer 52. The shape of the trench 54B formed at) has a vertical profile. Since the shape of the trench formed in the active region has the isotropic isotropy, the buried area of the buried gate is increased even if the gate insulating film 55 is formed.

As such, the shape of the trench may be adjusted during the trench process. The trenches formed in the active region can obtain the isotropic board by using isotropic etching.

As described above, according to the fourth embodiment, the buried isotropic shape of the trench 54A formed in the active region 53 increases the buried area in which the buried gate 56 is buried. Can reduce the resistance.

In the fourth embodiment, the buried gate 56 can further lower the resistance of the buried gate 56 by using a material selected from the group consisting of W, TiN, WN, WSi, Ru, Al, and Cu alone or in combination. have.

6 is a diagram illustrating a structure of a semiconductor device having a buried gate according to a fifth embodiment of the present invention.

Referring to FIG. 6, an active region 63 is defined on the semiconductor substrate 61 by an isolation layer 62, and a trench 64A having a predetermined depth is formed by simultaneously etching the isolation layer 62 and the active region 63. , 64B). The gate insulating film 65 is formed on the surface of the trench 64A formed in the active region 63. A buried gate 66 partially filling the trenches 64A and 64B is formed on the gate insulating layer 65, and a hard mask layer 67 is formed on the semiconductor substrate to serve as an etch barrier for forming the trench. The hard mask film 67 is an oxide film or a nitride film and has a thickness of 200 GPa or more.

In detail, the depth of the trench 64B formed in the device isolation layer is deeper than the trench 64A formed in the active region (D51 <D52). For example, the depth of the trench 64A formed in the active region is ensured to be 300 µm or more, and the trench formed in the device isolation film is secured to 200 µm or more than the trench formed in the active region.

The shape of the trench 64A formed in the active region 63 is a bulb type, and the shape of the trench 64B formed in the isolation layer 62 has a vertical profile. Accordingly, the semiconductor device according to the fifth embodiment has a structure in which a lower portion of the saddle fin is implemented in a bulb shape. Since the trench formed in the active region has a bulb shape, the buried area of the buried gate 66 is increased even if the gate insulating film 65 is formed.

As such, the shape of the trench may be adjusted during the trench process. The shape of the trench formed in the active region and the shape of the trench formed in the device isolation layer may be defined differently during the trench etching.

As described above, in the fifth embodiment, since the trench 64A formed in the active region 63 is formed in the shape of a bulb, the buried gate 66 is buried, and thus the buried gate 66 is increased. ) Resistance can be reduced.

In the fifth embodiment, the buried gate 66 may further lower the resistance of the buried gate by using a material selected from the group consisting of W, TiN, WN, WSi, Ru, Al, and Cu alone or in combination.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.

1 is a view showing a semiconductor device having a buried gate according to the prior art.

FIG. 2A illustrates a structure of a semiconductor device having a buried gate according to a first embodiment of the present invention. FIG.

FIG. 2B is a plan view of the semiconductor device in which the trench in FIG. 2A is formed. FIG.

3 is a diagram illustrating a structure of a semiconductor device having a buried gate according to a second embodiment of the present invention.

4 is a diagram illustrating a structure of a semiconductor device having a buried gate according to a third embodiment of the present invention.

FIG. 5 is a diagram showing the structure of a semiconductor device having a buried gate according to a fourth embodiment of the present invention; FIG.

6 is a diagram illustrating a structure of a semiconductor device having a buried gate according to a fifth embodiment of the present invention.

* Explanation of symbols for the main parts of the drawings

21 substrate 22 device isolation film

23: active area 24A, 24B: trench

25 gate insulating film 26 buried gate

27: hard mask

Claims (7)

A semiconductor substrate having an active region defined by an isolation layer; A trench formed by simultaneously etching the active region and the device isolation layer; A gate insulating film formed on sidewalls of the trench in the active region; And A buried gate partially filling the trench; And the trench is larger in line width formed in the active region than in line width formed in the device isolation layer. The method of claim 1, And a depth of the trench formed in the active region and a depth of the trench formed in the device isolation layer are substantially the same depth. The method of claim 1, And a trench deeper in the device isolation layer than a trench deeper in the active region. The method of claim 3, And a sidewall of the trench formed in the active region has an isotropic profile. The method of claim 4, wherein And a sidewall of the trench formed in the active region has a fully isotropic profile or a bowing isotropic profile. The method of claim 3, The trench formed in the active region has a bulb type. The method according to any one of claims 1 to 6, The buried gate is a semiconductor device using a material selected from the group consisting of W, TiN, WN, WSi, Ru, Al and Cu alone or in combination.
KR1020090038556A 2009-04-30 2009-04-30 Semiconductor device with buried gate and method for manufacturing the same KR20100119446A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9685519B2 (en) 2012-10-24 2017-06-20 Samsung Electronics Co., Ltd. Semiconductor device having buried channel array

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9685519B2 (en) 2012-10-24 2017-06-20 Samsung Electronics Co., Ltd. Semiconductor device having buried channel array

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