KR20100073945A - Electrophoretic display device and method of fabricating the same - Google Patents

Abstract

PURPOSE: An electrophoretic display device and a method for manufacturing the same are provided to prevent damage to a wire or a driving device in the end of an electrophoretic film. CONSTITUTION: A shock absorbing pattern(131) is formed with the same material as a first passivation layer(128). The shock absorbing pattern has the same thickness as the first passivation layer. The shock absorbing pattern is formed on a non display area and has a first width. A pixel electrode(140) contacts a thin film transistor and a drain electrode(122) through a drain contact hole(133). One end of an electrophoretic film(167) is located on the shock absorbing pattern. The electrophoretic film is attached to a display area.

Description

Electrophoretic display device and method of manufacturing the same {Electrophoretic display device and method of fabricating the same}

The present invention relates to an electrophoretic display device, and more particularly, to an electrophoretic display device and a method of manufacturing the same, which can prevent the occurrence of cracks in link wiring or driving device electrodes in a non-display area of an array substrate when an electrophoretic film is attached. It is about.

In general, liquid crystal displays, plasma displays, and organic field displays have become mainstream display devices. However, recently, various types of display devices have been introduced to satisfy rapidly changing consumer demands.

In particular, with the advancement and portability of the information usage environment, the company is accelerating to realize light weight, thin film, high efficiency and color video. As a part of this, research on electrophoretic display devices combining only the advantages of paper and existing display devices is being actively conducted.

Electrophoretic displays have been in the spotlight as the next generation of display devices for their excellent contrast ratio, visibility, fast response speed, natural color display, low cost and ease of portability.

In addition, the electrophoretic display device does not require a polarizing plate, a backlight unit, a liquid crystal layer, etc., unlike a liquid crystal display device, thereby reducing manufacturing costs.

Hereinafter, a conventional electrophoretic display device will be described with reference to the accompanying drawings.

1 is a view briefly showing a structure of the electrophoretic display to explain the driving principle.

As shown in the drawing, the conventional electrophoretic display device 1 includes an ink layer 57 interposed between the first and second substrates 11 and 36 and the first and second substrates 11 and 36. Include. The ink layer 57 includes a plurality of capsules 63 filled with a plurality of white pigments 59 and black pigments 61 charged through a condensation polymerization reaction.

Meanwhile, a plurality of pixel electrodes 28 connected to a plurality of thin film transistors (not shown) are formed in each pixel area (not shown) on the first substrate 11. That is, the plurality of pixel electrodes 28 are selectively applied with a positive voltage or a negative voltage, respectively. In this case, when the size of the capsule 63 including the white pigment 59 and the black pigment 61 is not constant, only a capsule 63 having a predetermined size may be selectively used.

Applying a voltage of positive or negative polarity to the ink layer 57 described above, the charged white pigments and black pigments 59 and 61 inside the capsule 63 are attracted toward opposite polarities. . That is, when the black pigment 61 moves upward, black is displayed. When the white pigment 59 moves upward, white is displayed.

Hereinafter, an electrophoretic display device according to the related art will be described in detail with reference to the accompanying drawings.

FIG. 2 is a schematic cross-sectional view of a conventional electrophoretic display device, and the same reference numerals are used for the same names as those of FIG. 1.

As shown in the drawing, the electrophoretic display device 1 according to the related art has electrophoretic interposed between the first and second substrates 11 and 36 opposingly bonded and the first and second substrates 11 and 36. Film 60. The electrophoretic film 60 has an ink layer 57 including a plurality of capsules 63 filled with a plurality of black pigments 61 and white pigments 59 charged through a condensation polymerization reaction, on an opposite side thereof. The first and second adhesive layers 51 and 53 correspondingly formed of a transparent material and the common electrode 55 made of a transparent conductive material therebetween are included. At this time, the black pigment 61 is positively charged and the white pigment 59 is negatively charged.

The second substrate 36 is made of transparent plastic or glass, and the first substrate 11 is mainly made of an opaque stainless material, and if necessary, a transparent plastic material or glass is used. Can be.

In this case, a color filter layer 40 including red, green, and blue color filter patterns is formed on the entire lower surface of the second substrate 36.

On the other hand, the first substrate 11 includes a gate wiring (not shown) and a data wiring (not shown) defining a pixel region P by vertically crossing each other in a matrix form, and the gate wiring (not shown) and data. The thin film transistor Tr, which is a switching element, is formed for each pixel region P at an intersection point of the wiring (not shown).

The thin film transistor Tr overlaps the gate electrode 14 extending from the gate wiring (not shown), the gate insulating layer 16 covering the gate electrode 14, and the gate electrode 14, and the active layer ( A semiconductor layer 18 composed of 18a and an ohmic contact layer 18b, a source electrode 20 in contact with the semiconductor layer 18 and extending from a data line (not shown), and the source electrode 20 Spaced drain electrodes 22.

In addition, a passivation layer 26 including a drain contact hole 27 exposing the drain electrode 22 is formed on the entire surface of the display area above the thin film transistor Tr.

The pixel electrode 28 connected to the drain electrode 22 through the drain contact hole 27 on the passivation layer 26 corresponds to each pixel region P. As shown in FIG. The pixel electrode 28 is mainly composed of one selected from a transparent conductive material such as indium tin oxide (ITO) and indium zinc oxide (IZO).

The electrophoretic display device 1 having the above-described configuration uses pixels including natural light or room light as external light sources, and is selectively applied with a positive polarity or a negative polarity by the thin film transistor Tr. The electrode 28 induces a positional change of the plurality of white pigments 59 and the black pigments 61 filled in the capsule 63 to realize an image.

The electrophoretic display device 1 having the above-described configuration can be manufactured by greatly proceeding two processes. The first process is an array process for completing the array substrate 11 including the pixel electrode 28 including the thin film transistor Tr, and the second process is to transfer the electrophoretic film 60 to the array substrate 11. It is a film laminating process which completes the display apparatus 1 by sticking.

3 is a diagram illustrating a step of laminating an electrophoretic film on an array substrate during a process of manufacturing a conventional electrophoretic display, and FIG. 4 is a cross-sectional view of a portion of a display area and a non-display area of a conventional electrophoretic display. to be.

After completing the array substrate 11 forming the thin film transistor Tr and the pixel electrode 28 on the insulating substrate 11, laminating for attaching the film 60 including the electrophoretic ink layer 57. The process proceeds corresponding to the predetermined width of the display area DA of the array substrate 11 and the non-display area NA adjacent thereto. In the non-display area NA of the array substrate 11, an external driving circuit board for driving the thin film transistor Tr and the pixel electrode 28 formed in the display area DA of the array substrate 11 (not shown). Gate and data pad electrodes (not shown) for connection, and gate and data link wirings 24 for connection between the gate and data pad electrodes (not shown) and the gate and data wires (not shown). ), A common connection wiring 15 for applying a common voltage, a Vgl wiring (not shown) for applying a gate low voltage, a circuit (not shown) for preventing static electricity, and the like are formed.

Therefore, the non-display area NA does not have a substantial component for realizing an image, and the gate and the data pad electrode (not shown) must remain exposed to be connected to the external driving circuit board (not shown). Therefore, the electrophoretic film 60 does not need to be attached. In this case, the electrophoretic film 60 may be attached to correspond to a predetermined width of the non-display area NA adjacent to the display area DA, even if an error occurs during the laminating process. This is to completely attach the electrophoretic film 60.

However, the gate link wiring 24 in the non-display area NA where the end where the electrophoretic film 60 begins to be attached is positioned on the roll 90 on the stage 80 when the electrophoretic film 60 is attached. Or a foreign material is attached to the end side of the electrophoretic film 60, and the roll 90 is pressed when the roll 90 is first contacted with an upper end of the electrophoretic film 60. As a result, a concentrated force acts on a portion overlapping with the foreign material, thereby causing cracks in the gate link wiring 24 or an electrode (not shown) of the driving element and a gate insulating layer positioned below these components. There is a situation.

5A and 5B are photographs of a part of a plan view of an array substrate corresponding to a portion where an end of the electrophoretic film is located, respectively. FIG. 5A shows a state before attaching the electrophoretic film, and FIG. 5B shows a state after attaching the electrophoretic film. It is shown.

As shown in FIG. 5A, the gate link wiring is in a normal state before laminating the electrophoretic film, but after the laminating process, the crack is formed in the gate link wiring corresponding to the portion where the end of the electrophoretic film is located as shown in FIG. 5B. It can be seen that this occurred.

Meanwhile, referring to FIG. 4, the gate link wiring 24 in which the crack is generated is further cut so that open defects in which the signal voltage is not transmitted to the gate or data wiring (not shown) connected to the gate link wiring 24 are performed. Another wiring located under the gate insulating film 16, for example, common connection wiring 15 or Vgl wiring (not shown) Contact failure) causes a short failure and finally causes a drive failure of the array substrate 11 to occur.

4, the cross-sectional structure of the conventional electrophoretic display device 1 in the non-display area NA is 2 μm to 4 μm, which is relatively thick as an organic insulating material in the display area DA. While the second protective layer 26 having a thickness of about μm is formed, it is understood that the second protective layer 26 made of the organic insulating material is not formed in the non-display area NA.

On the other hand, in order to minimize defects such as cracks generated in the gate link wiring 24 or the electrode of the driving element, the antistatic circuit except for the gate link wiring 24 to the contact portion of the end of the electrophoretic film 60 ( May be designed to avoid formation, but in practice, such design avoidance conditions result in an increase in design, process margin, or unnecessary design parts, and the non-display area NA is widened by such avoidance design. It is opposed to the recent trend of minimizing the width of the non-display area NA except the display area DA. In addition, even if this avoidance design is implemented, this is only limited to the driving element for the antistatic circuit (not shown) configuration, and the gate link wiring 24 is a component formed continuously in the non-display area NA. It is impossible to design.

The present invention has been made to solve the above-mentioned problem, the end of the electrophoretic film by providing a buffer means for cushioning the impact of the initial contact of the roll in the position where the end of the electrophoretic film is attached to the array substrate An object of the present invention is to provide an electrophoretic display device and a method of manufacturing the same, which can prevent the generation of cracks in wirings or driving elements.

Electrophoretic display device according to the present invention for achieving the above object, the electrophoretic display device according to the present invention, a display area consisting of a plurality of pixel areas, and a non-display area around the display area is defined on the substrate Gate wirings and data wirings formed to define a plurality of pixel areas crossing each other in the display area, and gate and data link wirings connected to the gate and data wirings in the non-display area; A thin film transistor comprising the gate electrode, the gate insulating film, the semiconductor layer, and source and drain electrodes spaced apart from each other in a stacked form in each of the plurality of pixel regions; First and second storage electrodes formed on each of the plurality of pixel regions and formed on and under the gate insulating layer to form a storage capacitor together with the gate insulating layer; A first passivation layer covering the thin film transistor and the storage capacitor and having a first thickness as an organic insulating material in the display area and having a drain contact hole exposing the drain electrode; A buffer pattern formed of the same material constituting the first protective layer and having the same thickness and having a first width in the non-display area; A pixel electrode formed in each pixel area in contact with the drain electrode of the thin film transistor through the drain contact hole on the first protective layer in the display area; One end thereof is disposed on the buffer pattern on the pixel electrode, and includes an electrophoretic film attached to the entire display area.

The electrophoretic film may include an adhesive layer contacting the pixel electrode, an ink layer including a plurality of capsules filled with a plurality of white pigments and black pigments charged sequentially through a condensation polymerization reaction, and a transparent conductive material. It is made of a common electrode made of, and a base film.

A color filter layer including a red, green, and blue color filter pattern that is sequentially repeated on the electrophoretic film and a counter substrate are configured.

A second protective layer is included as an inorganic insulating material between the first protective layer and the thin film transistor.

The non-display area has the same configuration as a gate pad electrode connected to one end of the gate link wiring, a data pad electrode connected to one end of the data link wiring, and a thin film transistor formed in the pixel region for implementing an antistatic circuit. A driving thin film transistor having is formed. In this case, a common connection line made of the same material is formed on the same layer as the gate line in the non-display area, and the gate link line crosses the common connection line and is formed on the gate insulating layer.

The first thickness is 2㎛ to 4㎛, characterized in that the first width is 0.5mm to 1mm, characterized in that the buffer pattern and the first protective layer is formed in connection.

The pixel electrode is formed to overlap the thin film transistor, the gate line on one side and the data line on one side connected to the thin film transistor.

In the method of manufacturing an electrophoretic display device according to the present invention, a plurality of pixel areas are defined by crossing a display area composed of a plurality of pixel areas and the display area on a substrate on which a non-display area around the display area is defined. Forming gate and data lines, and gate and data link lines connected to the gate and data lines in the non-display area; A thin film transistor comprising the gate electrode, the gate insulating film, the semiconductor layer, and the source and drain electrodes spaced apart from each other in a stacked form in each of the plurality of pixel regions, the first storage electrode, the gate insulating film, and the second storage. Forming a storage capacitor having a stacked structure of electrodes; A first protective layer covering the thin film transistor and the storage capacitor and having a drain contact hole exposing the drain electrode and having a first thickness as an organic insulating material in the display area; and forming the first protective layer in the non-display area. Forming a buffer pattern having the same thickness and having a first width using the same material forming the protective layer; Contacting the drain electrode of the thin film transistor through the drain contact hole on the first passivation layer in the display area, and forming a pixel electrode for each pixel area; The electrophoretic film is positioned so that one end thereof is positioned on the buffer pattern over the pixel electrode, and the roll is brought into contact with the end of the electrophoretic film positioned in the buffer pattern through a laminating device having a roll. Attaching the electrophoretic film in correspondence to the entire display area by transferring pressure.

And forming a color filter layer on the electrophoretic film, bonding the transparent counter substrate, or forming a color filter layer on the opposing substrate and facing the electrophoretic film.

The forming of the first protective layer having the drain contact hole and the buffer pattern may include forming an organic insulating material layer by coating an organic insulating material on the entire surface of the thin film transistor; By performing halftone exposure or diffraction exposure on the organic insulating material layer, a first organic insulating layer having a second thickness thicker than the first thickness and having the drain contact hole exposing the drain electrode is formed in the display area. And forming a second organic insulating layer having an organic pattern of the second thickness and a third thickness thinner than the first thickness in the non-display area; Performing a dry etching to remove the second organic insulating layer having a third thickness, and reducing the thickness of the first organic insulating layer and the organic pattern to have the first thickness.

The first thickness is 2 μm to 4 μm, and the first width is 0.5 mm to 1 mm.

Before forming the first protective layer, forming a second protective layer of an inorganic insulating material on the entire surface over the thin film transistor.

The forming of the gate and data lines and the gate and data link wirings may include forming a gate pad electrode connected to one end of the gate link wiring and a data pad electrode connected to one end of the data link wiring in the non-display area. The forming of the thin film transistor may include forming a driving thin film transistor having the same configuration as the thin film transistor formed in the pixel area in the non-display area.

The pixel electrode may be formed to overlap the thin film transistor, the gate wiring on one side and the data wiring on one side in the pixel region.

The forming of the gate and data wirings and the gate and data link wirings may include forming the gate wirings in a display area on the substrate and forming a common connection wiring in the non-display area; Forming the gate insulating film over the gate wiring and the common connection wiring; Patterning the gate insulating film to form a link contact hole exposing one end of the gate wiring; Forming the data line crossing the gate line in the display area on the gate insulating layer provided with the link contact hole, and through the data link line and the link contact hole connected to the data line in the non-display area. Forming the gate link wiring in contact with one end of the gate wiring and crossing the common wiring.

The electrophoretic display device according to the present invention has an effect of suppressing the generation of cracks in the wiring or the driving circuit due to the impact of the roll when the electrophoretic film of the non-display area is attached.

Since there is no need for a separate avoidance design for preventing the generation of cracks such as wiring or a driving circuit generated when the electrophoretic film is attached, there is an advantage of preventing an increase in the width of the non-display area.

In the method of manufacturing an electrophoretic display device according to the present invention, an additional process is not required to form a means for suppressing crack generation such as link wiring or a driving circuit in a non-display area, and thus additional manufacturing It has the advantage of not incurring costs.

Hereinafter, an electrophoretic display device according to the present invention will be described with reference to the accompanying drawings.

6 is a plan view of a portion of a display area and a non-display area of the electrophoretic display device according to the present invention, and FIG. 7 is a cross-sectional view of a portion taken along the cutting line VII-V of FIG. 6.

As shown, the electrophoretic display device 100 is largely composed of an array substrate 101 and an electrophoretic film 167 attached thereto.

The array substrate 110 includes a display area DA having a plurality of pixel areas P to display an image and a gate and a data pad part connected to an external driving circuit board (not shown) outside thereof. It is divided into a non-display area NA.

In the display area DA, a plurality of gates and data lines 107 and 118 are formed to intersect each other via the gate insulating layer 110 to define the pixel area P. In the non-display area NA, the gate is formed. A gate link wiring 125 and a gate pad electrode (not shown) connected through the wiring 107 and the link contact hole 117, and a data link wiring (not shown) and a data pad electrode (not shown) connected to the data wiring 118. The common connection line 108 for applying the common voltage and the Vgl line 109 for applying the gate low voltage are formed on the common lines 104 provided in the display area DA.

Meanwhile, in the drawing, the common wiring 104 and the common connection wiring 108 are formed on the same layer, and the plurality of common wirings are divided in the form of the common connection wiring 108 formed in the non-display area NA. 104 is formed. In this case, the common wiring 104, the common connecting wiring 108, and the gate wiring 107 are made of the same metal material on the same layer. Therefore, since the gate link wiring 125 connected to the gate wiring 107 has a configuration intersecting with the common connecting wiring 108, the common connecting wiring formed on the same layer as the gate wiring 107 ( In order to prevent a short with the 108, a layer different from the gate wiring 107 is formed on the gate insulating film 110 in the drawing. In this case, since the data line 118 is formed on a different layer from the common connection line 108, a short problem does not occur when the data link line (not shown) connected thereto intersects with the common connection line 108. Therefore, the data link line (not shown) is made of the same metal material on the gate insulating layer 110 on which the data line 118 is formed.

Meanwhile, one pixel region P is connected to the gate wiring 107 and the data wiring 118, and has a gate electrode 103, a gate insulating film 110, and an active layer 115a of pure amorphous silicon. And a thin film transistor Tr, which is a switching element composed of source and drain electrodes 120 and 122 spaced apart from each other, and a semiconductor layer 115 including an ohmic contact layer 115b of impurity amorphous silicon. Although not shown in the drawings, a plurality of driving thin film transistors (not shown) having the above-described configuration are formed as driving elements for implementing an antistatic circuit (not shown).

In addition, the common wiring 104 is formed in each pixel area P under the gate insulating layer 110 to be parallel to the gate wiring 107, and corresponds to the common wiring 104. 122 is formed to extend and overlap, so that the overlapping common wiring 104 extends to the first storage electrode 105, the drain electrode 122 extends to the second storage electrode 124, and the two electrodes 105. And a storage capacitor StgC together with the gate insulating layer 110 interposed therebetween.

Meanwhile, a first protective layer 128 is formed on the thin film transistor Tr (not shown) as the switching and driving element as an inorganic insulating material. In this case, although not shown in the drawing, the driving gate electrode of the driving thin film transistor (not shown) is electrically connected to each driving thin film transistor (not shown) in the non-display area NA. A plurality of contact holes (not shown) are formed to correspond to any one of the driving source electrode and the driving drain electrode, and the gate and data pad contact holes may also correspond to the gate and data pad electrodes (not shown). (Not shown) is formed.

In the display area DA, a second protective layer 130 having a thickness of about 2 μm to 4 μm is formed as an organic insulating material. In this case, the drain electrode 122 of the thin film transistor Tr formed in each of the pixel regions P may be formed in the second protective layer 130 and the first protective layer 128 below. A drain contact hole 133 is formed to expose the drain.

In addition, in the non-display area NA, the same organic insulating material as the material of the second protective layer 130 has a thickness of about 2 μm to 4 μm, and the end of the electrophoretic film 167 is located. Corresponding to the portion is characterized in that the buffer pattern 131 for cushioning the impact due to the contact of the roll during the laminating process is formed.

In this case, the width of the buffer pattern 131 is always the end of the electrophoretic film 167 even if the end of the electrophoretic film 167 is accepted in consideration of the position error during the laminating proceeds. It is characterized in that it is formed to have a sufficient width to be positioned above the buffer pattern (131). Since the alignment error of the electrophoretic film 167 at the time of laminating is usually 0.5 mm or less, it is preferable to be formed to have a width of about 0.5 mm to 1 mm.

In this case, the buffer pattern 131 may be formed to be spaced apart from the second passivation layer 130 formed in the display area DA, or as a modification, although not shown in the drawing, the second passivation layer ( It may be formed in connection with 130.

Therefore, as described above, the buffer pattern 131 made of an organic insulating material having elasticity and elasticity compared to the inorganic insulating material is provided in the non-display area NA, so that the roll first contacts through the electrophoretic film 167. Thus, the shock is buffered during pressurization, so that the generation of cracks can be suppressed in the gate link wiring 125, the electrode (not shown) of the driving element, and the gate insulating layer 110 disposed under the components. Even if a foreign material is interposed, the buffer pattern 131 has a thickness of about 2 μm to 4 μm and has elasticity, so that cracks generated by the foreign material being pressed can also be suppressed to some extent. Therefore, such a generation of cracks is suppressed, so that a short problem caused by the end of the gate link wiring 125 cut by the crack generation penetrates the gate insulating layer 110 and comes into contact with the common connection wiring 108 located below. It can also be suppressed naturally.

A plurality of capsules 160 filled with the base film 150 and the plurality of black pigments 158 and white pigments 156 charged through the condensation polymerization reaction in correspondence with the array substrate 101 having the above-described configuration. An ink layer 163 including an adhesive layer, an adhesive layer 165 formed of a transparent material under the ink layer 163, and a transparent conductive material between the ink layer 163 and the base film 150. An electrophoretic film 167 including the common electrode 153 is attached and is configured.

In addition, a color filter layer 170 having red, green, and blue color filter patterns 170a, 170b (not shown), which are sequentially repeated, is formed on an upper portion of the electrophoretic film 167. 180 constitutes the electrophoretic display device 100 according to the present invention.

Hereinafter, a method of manufacturing an electrophoretic display device according to the present invention having the above-described structure will be described with reference to the drawings.

8A to 8K illustrate one pixel region including a portion in which a thin film transistor configured in the display area DA and a portion in which a storage capacitor is formed, in the electrophoretic display according to the present invention, and the end of the electrophoretic film is positioned. The process cross-sectional view of a portion of the non-display area is shown. For convenience of description, an area in which a switching thin film transistor is formed in each pixel area P is defined as a switching area TrA.

First, as shown in FIG. 8A, a first metal material such as aluminum (Al), aluminum alloy (AlNd), copper (Cu), or copper alloy may be formed on an insulating substrate 101, for example, a glass substrate or a plastic substrate. And depositing a chromium (Cr) and titanium alloy to form a first metal layer (not shown), and then applying a photoresist, exposing with a mask, developing a photoresist, etching, and stripping the photoresist. The mask process may include a gate line (not shown) extending in one direction and a common line (not shown) extending in parallel to the display area.

At the same time, a gate electrode 103 connected to the gate line (not shown) is formed in the first storage electrode 105 and the switching region TrA. In this case, the first storage electrode 105 is formed in a form branched from the common wiring (not shown) formed in parallel with the gate wiring (not shown) or may be formed as the common wiring (not shown) itself.

In the non-display area NA, a common connection line 108 connected to the common line (not shown) and a Vgl line (not shown) are formed to be spaced apart from the common connection line 108. In addition, although not shown in the drawings, a gate electrode (hereinafter referred to as a driving gate electrode) of a driving thin film transistor, which serves as a driving element to be provided for a circuit configuration for preventing static electricity, is formed.

Meanwhile, the first metal layer (not shown) may be formed to have a double layer structure by continuously depositing different metal materials. When patterning a first metal layer (not shown) having such a double layer structure, for example, a gate wiring (not shown) having a double layer structure of aluminum alloy (AlNd) / molybdenum (Mo) and titanium alloy / copper (Cu) and The gate electrode 103, the first storage electrode 105, the common wiring (not shown), the common connection wiring 108, and the driving gate electrode (not shown) may be formed. In the drawing, for convenience, a gate wiring (not shown) having a single layer structure, a gate electrode 103, a first storage electrode 105, a common wiring (not shown), a common connection wiring 108, and a driving gate electrode (not shown) As shown.

Next, as shown in FIG. 8B, the gate wiring (not shown), the gate electrode 103, the first storage electrode 105, the common wiring (not shown), the common connection wiring 108, and the driving gate electrode are shown. An inorganic insulating material such as silicon oxide (SiO ₂ ) or silicon nitride (SiNx) is deposited on the entire surface to form the gate insulating layer 110.

Subsequently, pure amorphous silicon and impurity amorphous silicon are successively deposited on the gate insulating layer 110 to form a pure amorphous silicon layer (not shown) and an impurity amorphous silicon layer (not shown), and then perform a mask process. By patterning, an impurity amorphous silicon pattern 115c is formed in the switching region TrA in response to the gate electrode 103 and on the active layer 115a. In this case, the active layer 115a and the impurity amorphous silicon pattern 115c have the same material and have a same shape and correspond to a driving gate electrode (not shown) provided in the non-display area NA. And a driving impurity amorphous silicon pattern (not shown) are formed. Although not shown in the drawings, the gate insulating layer 110 is patterned on the boundary of the display area DA to form a link contact hole (not shown) that exposes one end of the plurality of gate wires (not shown). This is to connect a gate link wiring (not shown) and a gate pad electrode (not shown) and the gate wiring (not shown) to be formed in a later process.

Next, as shown in FIG. 8C, a second metal material such as molybdenum (Mo) and copper (Cu) is disposed on the active layer 115a, the impurity amorphous silicon pattern (115c of FIG. 8B), and the gate insulating layer 110. ), A titanium alloy or aluminum alloy (AlNd) is deposited to form a second metal layer (not shown) on the entire surface of the substrate. At this time, the second metal layer (not shown) is formed to have a two-layer structure of, for example, titanium alloy / copper (Cu) by continuously depositing two or three of the second metal material, or molybdenum (Mo) / It may be formed to have a triple layer structure of aluminum alloy (AlNd) / molybdenum (Mo). In the drawings, one having a single layer structure is shown as an example.

Thereafter, by patterning the second metal layer (not shown), a data line 118 is formed in the display area DA to cross the gate line (not shown) to define the pixel area P. A data link wiring (not shown) connected to the data line 118 in the display area NA, a data pad electrode (not shown) at an end thereof, and the gate wiring (not shown) through the link contact hole (not shown). Gate link wiring 125 and one end thereof contacted with each other, and a gate pad electrode (not shown) connected to the other end of the gate link wiring 125.

At the same time, source and drain electrodes 120 and 122 are formed in the switching region TrA in each pixel region P so as to be spaced apart from each other on the impurity amorphous silicon pattern 115c of FIG. 8B, and the drain electrode ( The second storage electrode 124 overlapping the first storage electrode 105 may be formed by extending the 122. In this case, the source electrode 120 is connected to the data line 118.

Although not shown in the drawing, a driving source electrode (not shown) and a driving drain electrode (not shown) are formed in the non-display area NA to be spaced apart from each other even in response to the driving impurity amorphous pattern (not shown).

Thereafter, the active layer 115a is formed between the source and drain electrodes 120 and 122 by performing dry etching to remove the impurity amorphous silicon pattern 115c between the source and drain electrodes 120 and 122. An ohmic contact layer 115b of impurity amorphous silicon is formed on the active layer 115a and in contact with the source and drain electrodes 120 and 122 and spaced apart from each other. At this time, the active layer 115a and the ohmic contact layer 115b spaced apart from each other form a semiconductor layer 115. In this case, the same process is performed in the non-display area NA to form a driving ohmic contact layer (not shown) below the driving source and drain electrodes (not shown), and the driving gates sequentially stacked on the non-display area NA. The electrode (not shown), the gate insulating layer 110, the driving active layer (not shown), the driving ohmic contact layer (not shown), and the driving source and drain electrodes (not shown) form a driving thin film transistor (not shown).

Meanwhile, the forming of the semiconductor layer 115 and the source and drain electrodes 120 and 122 described above are performed through two different mask processes. However, although not shown in the drawings as a modification, diffraction or exposure is performed in a state in which a pure and impurity amorphous silicon layer is formed on the gate insulating layer 110, and the second metal layer is formed on the impurity amorphous silicon layer before patterning it. The semiconductor layer, the source, and the drain electrode may be formed through a single mask process, in which a photoresist pattern having different thicknesses is formed by performing a mask process using a halftone exposure technique. In this case, a semiconductor pattern is formed under the data line and the data pad electrode with the same material forming the semiconductor layer.

Next, as shown in FIG. 8D, the data line, the source and drain electrodes 120 and 122, the second storage electrode 124, the data link wiring (not shown), and the data pad electrode (not shown). ), An inorganic insulating material, for example, silicon oxide (SiO ₂ ) or silicon nitride (SiNx), is deposited over the gate link wiring 125, the gate pad electrode (not shown), and the driving source and drain electrodes (not shown). The first protective layer 128 is formed. In this case, in the case of the first passivation layer 128, the gate and data pad electrodes (not shown) are not deposited by corresponding to a portion corresponding to the gate and data pad electrodes (not shown) by the shadow frame when the first protective layer 128 is deposited. ) Will be exposed.

Next, an organic insulating material such as photo acryl or benzocyclobutene (BCB) is coated on the first passivation layer 128 to have a thickness of about 3 μm to 5 μm, and the surface thereof is flat. An organic insulating layer (not shown) is formed.

Subsequently, diffraction exposure or halftone exposure is performed on the organic insulating layer (not shown) and developed, thereby, about 3 μm to 5 μm for the display area DA including the plurality of pixel areas P. FIG. Forming a first organic insulating pattern 129a having a first thickness of 0.5 mm to 1 mm corresponding to a portion where an end of the electrophoretic film 167 is to be positioned in a later process in response to the non-display area NA A second organic insulating pattern is formed so as to form a buffer pattern 131 having a width and a first thickness, and have a second thickness of about 1 μm thinner than the first thickness to correspond to the other non-display area NA. 129b is formed.

In this case, corresponding to each of the drain electrodes 122 in each pixel region P, a first hole 133 exposing the first protective layer 128 disposed thereon is formed, and the non-display area NA Corresponding to some of the plurality of driving source and drain electrodes (not shown) or driving gate electrodes (not shown), a second hole (not shown) exposing the first protective layer 128 formed on the electrodes is formed.

Subsequently, as illustrated in FIG. 8E, the first protective layer may be formed of an inorganic insulating material exposed to the first and second holes 132 (not shown) by performing a first dry etching in a first gas atmosphere. By removing the 128, a drain contact hole 133 and a plurality of first contact holes (not shown) are formed to expose the drain electrode 122 of the switching region TrA.

  Next, as shown in FIG. 8F, the second dry etching is performed in the second gas atmosphere to remove the second organic insulating pattern (129b of FIG. 8E) having the second thickness in the non-display area NA. . By the second dry etching in the second gas atmosphere, the thickness of the first organic insulating pattern 129a of FIG. 8E is reduced in the display area DA, and the thickness of 2 μm to 4 μm is reduced. 2, the protective layer 130 is formed, and at the same time, the thickness of the non-display area NA is reduced by about 1 μm to form a buffer pattern 131 having a thickness of about 2 μm to about 4 μm. In addition, the gate and the data pad electrode (not shown) may be exposed in the non-display area NA by the second dry etching.

The reason why the second protective layer 130 is formed of the organic insulating material so as to have a thickness of about 2 μm to 4 μm in the display area DA is because of the gate line (not shown) and the data line 118 located below the second protective layer 130. In order to minimize the parasitic capacitance caused by the pixel electrode (not shown) formed so as to overlap the (), and to have a flat surface.

Also, in the non-display area NA, the second protective layer 130 made of the organic insulating material is not formed between electrodes (not shown) of the driving thin film transistor (not shown) to implement an antistatic circuit. Electrical connection is required, and the driving source and drain electrodes (not shown) of these driving thin film transistors have a very small area, and the connection pattern must be formed of a transparent conductive material in a later process through the first contact hole (not shown). In addition, since the thickness of the second protective layer 130 is too thick for the area of the first contact hole (not shown), breakage occurs in the first contact hole (not shown), and thus the driving electrodes (not shown). This is to solve this problem because of poor contact with. In the case of the display area DA, the drain contact hole 133 has a larger area than the driving source and the drain electrode (not shown) of the driving thin film transistor (not shown), thereby sufficiently filling the drain contact hole 133. By forming wide, problems such as the above-described disconnection do not occur.

In addition, when the second protective layer 130 made of the organic insulating material is formed on the entire surface of the non-display area NA, the thickness of the second protective layer 130 is too thick and has flexibility and elasticity during the cutting process. In order to solve this problem, the second protective layer 130 made of the organic insulating material is not formed in the non-display area NA, because cutting may not be performed smoothly.

Meanwhile, in the present invention, the buffer pattern 131 is formed of an organic insulating material having elastic force in the non-display area NA, but has a width of 0.5 mm to 1 mm corresponding to the vicinity of the display area DA. As a result, no problem occurs when cutting.

Next, as illustrated in FIG. 8G, a transparent conductive material such as indium tin oxide (ITO), indium zinc oxide (IZO), and indium tin zinc oxide may be disposed on the second protective layer 130. A conductive material layer (not shown) is formed on the entire surface by depositing one of the (ITZO). Subsequently, the conductive material layer (not shown) is patterned to contact the drain electrode 122 in the pixel region P through the drain contact hole 133, and in the pixel region P. The pixel electrode 140 is formed to completely overlap the gate line (not shown) and the data line 118 contacting the switching thin film transistor Tr. The reason for forming the pixel electrode 140 in this form is to maximize the aperture ratio.

In the case of the present invention, the pixel electrode 140 is formed so as to completely overlap with the gate and data line (118) connected to the switching thin film transistor Tr, which may cause a problem of parasitic capacitance. As a result, the second protective layer 130 having a thickness of about 2 μm to 4 μm is formed.

In the non-display area NA, the transparent conductive material layer (not shown) is patterned to form a first contact hole (not shown) on the first protective layer 128 exposed to the outside of the buffer pattern 131. A connection pattern (not shown) for electrically connecting the electrodes of the adjacent driving thin film transistor (not shown) is formed through the gate auxiliary pad electrode (not shown) by covering the gate and data pad electrodes (not shown). ) And a data press pad electrode (not shown).

Next, as shown in FIGS. 8H and 8I, the substrate 101 having the pixel electrodes 140 formed in the pixel regions P is positioned on a stage (not shown) of the laminating apparatus, and is transparent and flexible on the top thereof. A base film 150 made of a material having properties such as PET, a lower portion of the common electrode 153 formed of a transparent conductive material, and a plurality of white pigments 156 charged through a condensation polymerization reaction. Ink layer 163 including a plurality of capsules 160 filled with a black pigment 158 and an electrophoretic film 167 including an adhesive layer 165 under the ink layer 163. The adhesive layer 165 and the pixel electrode 140 face each other and are positioned between the common electrode 153 and the pixel electrode 140.

Thereafter, the ends of the electrophoretic film 167 are aligned to be positioned on the buffer pattern 131 formed in the non-display area NA, and then the roll of the laminating device is aligned with the ends of the electrophoretic film 167. The electrophoretic film 167 is attached to the array substrate 101 by advancing in one direction while applying a constant pressure while making contact.

In the case of the present invention during the laminating process, the end of the electrophoretic film 167, which is in initial contact with the roll 190 of the laminating apparatus, is positioned on the buffer pattern 131 made of an organic insulating material having elastic force. The impact due to the roll contact is alleviated to prevent the generation of cracks in the gate link wiring 125, the electrode (not shown) of the driving element, the gate insulating layer 110, and the like.

On the other hand, the completion of the process to the above-described process is to complete the monochrome electrophoresis device.

The process is optional and proceeds when manufacturing an electrophoretic device capable of color implementation.

Next, as shown in FIG. 8J, an electrophoretic film 167 attached to the display area DA, more specifically, one of red, green, and blue on the entire surface of the display area DA above the base film 150. For example, a red color resist is applied by a spin coating method to form a red color filter layer (not shown), and then a transmission region through which light passes and a block to block light. Exposure is performed using an exposure mask composed of a region, and the exposed color resist layer is developed to form a red color filter pattern 170a corresponding to a part of the pixel region P. FIG. In this case, since the color resist layer has a negative property, portions that receive light remain, and portions that do not receive light are removed to form red color filter patterns 170a corresponding to some pixel regions P. FIG. do.

Subsequently, the green color filter pattern 170b (not shown) is formed on the base film 150 to correspond to a portion of the pixel region P by proceeding in the same manner as the method of forming the red color filter pattern 170a. The filter layer 170 is completed. In this case, the red, green, and blue color filter patterns 170a, 170b (not shown) may be repeated in sequence to correspond to each pixel area P. FIG.

In addition, although the above-mentioned method takes the formation of the color filter layer by the pigment dispersion method as an example, the three-color color filter pattern 170a, 170b, not shown also by the method of dotting by each pixel area P using an inkjet apparatus. It is also possible to form a color filter layer 170 having a).

Next, as shown in FIG. 8K, an opposite substrate (not shown) of a transparent and flexible plastic material is disposed on the color filter layer 170, and is sealed along the non-display area NA around the display area DA. A pattern (not shown) is formed, and the opposing substrate 180 is bonded to the array substrate 101 so as to cover the display area DA. In this case, the counter plate 180 may be attached to expose the gate and the data auxiliary pad electrode (not shown). In this case, the counter substrate 180 may be in the form of a film, and may be attached to the electrophoretic film 167 or the color filter layer 170 through an adhesive layer (not shown). In this case, the seal pattern (not shown) is omitted.

On the other hand, the color filter layer 170 is shown as an example formed on top of the electrophoretic film 167, the color filter layer 170 is first formed on the lower surface of the opposing substrate 180, the electrophoresis The array substrate 101 may be bonded to the film 167.

The present invention is not limited to the above embodiments and modifications thereof, and it will be apparent that various modifications and changes can be made without departing from the spirit and the spirit of the invention.

1 is a view for explaining a driving principle of an electrophoretic display.

2 is a schematic cross-sectional view of a conventional electrophoretic display.

3 is a diagram illustrating a step of laminating an electrophoretic film on an array substrate during a process of manufacturing a conventional electrophoretic display.

4 is a cross-sectional view of a portion of a display area and a non-display area of a conventional electrophoretic display device.

5A and 5B are photographs of a part of a plan view of an array substrate corresponding to a portion where an end of the electrophoretic film is located, respectively, FIG. 5A shows a state before attaching the electrophoretic film, and FIG. 5B shows a state after attaching the electrophoretic film. Figure showing the state.

6 is a plan view of a portion of a display area and a non-display area of the electrophoretic display device according to the present invention;

FIG. 7 is a cross-sectional view of a portion taken along the line VII-VII of FIG. 6. FIG.

8A to 8K illustrate a pixel area including a portion in which a thin film transistor configured in a display area and a portion in which a storage capacitor is formed, and a non-display in which an end of the electrophoretic film is positioned in the electrophoretic display device according to the present invention. Process step-by-step cross-sectional view of a portion of the area.

<Description of reference numerals for main parts of the drawings>

100: electrophoresis display device 101: substrate

103: gate electrode 108: common connection wiring

105: storage first electrode 110: gate insulating film

115: semiconductor layer 115a: active layer

115c: ohmic contact layer 118: data wiring

120 source electrode 122 drain electrode

124: storage second electrode 125: gate link wiring

128: first protective layer 130: second protective layer

131: buffer pattern 140: pixel electrode

150: base film 153: common electrode

156: White Pigment 158: Black Pigment

160: capsule 163: ink layer 165: adhesive layer

167: electrophoretic film 170: color filter layer

180: counter substrate

Claims (17)

A display area formed of a plurality of pixel areas, a gate line and a data line formed to define each of the plurality of pixel areas crossing each other on the display area on a substrate on which a non-display area around the display area is defined, and the non-display area A gate and data link wiring formed at and connected to the gate and data wiring; A thin film transistor comprising the gate electrode, the gate insulating film, the semiconductor layer, and source and drain electrodes spaced apart from each other in a stacked form in each of the plurality of pixel regions; First and second storage electrodes formed on each of the plurality of pixel regions and formed on and under the gate insulating layer to form a storage capacitor together with the gate insulating layer; A first passivation layer covering the thin film transistor and the storage capacitor and having a first contact thickness in the display area as an organic insulating material and having a drain contact hole exposing the drain electrode; A buffer pattern formed of the same material constituting the first protective layer and having the same thickness and having a first width in the non-display area;  A pixel electrode formed in each pixel area in contact with the drain electrode of the thin film transistor through the drain contact hole on the first protective layer in the display area; An electrophoretic film whose one end is positioned on the buffer pattern over the pixel electrode and is attached to correspond to the entire display area. Electrophoretic display device comprising a. The method of claim 1, The electrophoretic film, An ink layer comprising a pressure-sensitive adhesive layer in contact with the pixel electrode, a plurality of capsules filled with a plurality of white pigments and black pigments charged sequentially through a condensation polymerization reaction, a common electrode made of a transparent conductive material, and a base Electrophoretic display device characterized in that consisting of a film. The method of claim 1, An electrophoretic display device comprising a color filter layer including red, green, and blue color filter patterns which are sequentially repeated on the electrophoretic film, and an opposing substrate. The method of claim 1, An electrophoretic display device comprising a second protective layer as an inorganic insulating material between the first protective layer and the thin film transistor. The method of claim 1, The non-display area has the same configuration as a gate pad electrode connected to one end of the gate link wiring, a data pad electrode connected to one end of the data link wiring, and a thin film transistor formed in the pixel region for implementing an antistatic circuit. Electrophoretic display device characterized in that the drive thin film transistor having a. The method of claim 1, Wherein the first thickness is 2 μm to 4 μm, and the first width is 0.5 mm to 1 mm. The method of claim 1, And the buffer pattern and the first protective layer are connected to each other. The method of claim 1, And the pixel electrode is formed to overlap the thin film transistor, the gate wiring on one side and the data wiring on one side in the pixel region. A display area formed of a plurality of pixel areas, a gate line and a data line defining each of the plurality of pixel areas crossing each other on the display area on a substrate on which a non-display area around the display area is defined, and on the non-display area. Forming a gate and data link wiring connected to the gate and data wiring; A thin film transistor comprising the gate electrode, the gate insulating film, the semiconductor layer, and the source and drain electrodes spaced apart from each other in a stacked form in each of the plurality of pixel regions, the first storage electrode, the gate insulating film, and the second storage. Forming a storage capacitor having a stacked structure of electrodes; A first protective layer covering the thin film transistor and the storage capacitor and having a drain contact hole exposing the drain electrode and having a first thickness as an organic insulating material in the display area; and forming the first protective layer in the non-display area. Forming a buffer pattern having the same thickness and having a first width using the same material forming the protective layer; Contacting the drain electrode of the thin film transistor through the drain contact hole on the first passivation layer in the display area, and forming a pixel electrode for each pixel area; The electrophoretic film is positioned so that one end thereof is positioned on the buffer pattern over the pixel electrode, and the roll is brought into contact with the end of the electrophoretic film positioned in the buffer pattern through a laminating device having a roll. Attaching the electrophoretic film corresponding to the entire display area by applying pressure Method of manufacturing an electrophoretic display device comprising a. The method of claim 9, Forming a color filter layer on the electrophoretic film, bonding a transparent opposing substrate, or forming a color filter layer on the opposing substrate and facing the electrophoretic film so as to face the electrophoretic film. . The method of claim 9, Forming the first protective layer having the drain contact hole and the buffer pattern, Forming an organic insulating material layer by applying an organic insulating material on the entire surface of the thin film transistor; By performing halftone exposure or diffraction exposure on the organic insulating material layer, a first organic insulating layer having a second thickness thicker than the first thickness and having the drain contact hole exposing the drain electrode in the display area. Forming a second organic insulating layer having an organic pattern of the second thickness and a third thickness thinner than the first thickness in the non-display area; Performing a dry etching to remove the second organic insulating layer having the third thickness, and reducing the thickness of the first organic insulating layer and the organic pattern to have the first thickness. Method of manufacturing an electrophoretic display device comprising a. The method of claim 9, Wherein the first thickness is 2 μm to 4 μm and the first width is 0.5 mm to 1 mm. The method of claim 9, Before forming the first passivation layer, forming a second passivation layer on the front surface of the thin film transistor using an inorganic insulating material. The method of claim 9, The forming of the gate and data wires and the gate and data link wires may include: Forming a gate pad electrode connected to one end of the gate link wiring and a data pad electrode connected to one end of the data link wiring in the non-display area, The forming of the thin film transistor may include forming a driving thin film transistor having the same configuration as the thin film transistor formed in the pixel area in the non-display area. The method of claim 9, And the pixel electrode is formed to overlap the thin film transistor, the gate wiring on one side and the data wiring on one side connected to the pixel region. The method of claim 14, The forming of the gate and data wires and the gate and data link wires may include: Forming the gate wiring in a display area on the substrate and forming a common connection wiring in the non-display area; Forming the gate insulating film over the gate wiring and the common connection wiring; Patterning the gate insulating film to form a link contact hole exposing one end of the gate wiring; Forming the data line crossing the gate line in the display area on the gate insulating layer provided with the link contact hole, and through the data link line and the link contact hole connected to the data line in the non-display area. Forming the gate link wiring in contact with one end of the gate wiring and crossing the common wiring;  Method of manufacturing an electrophoretic display device comprising a. The method of claim 5, And a common connection line formed of the same material on the same layer as the gate line, wherein the gate link line crosses the common connection line and is formed on the gate insulating layer.

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