KR20090000488A - Thin film transistor array of horizontal electornic field applying type - Google Patents

Abstract

A thin film transistor array of horizontal electronic field applying type is provided to improve the transmittance of the liquid crystal display device by eliminating a pixel electrode connecting part. A semiconductor pattern(30) of the thin film transistor is formed in the top of the substrate. A gate insulating layer is placed on the above semiconductor pattern. The gate line(32) includes the gate electrode of the thin film transistor. The interlayer insulating film is placed on the gate line. A data line(34) includes the source electrode of the thin film transistor it intersects with the gate line and the pixel region is defined. The drain electrode(34D) of the thin film transistor separating from data line and is formed on the interlayer insulating film. The protective film covers the data line and the drain electrode. A pixel contact holes(50) exposes the drain electrode through the protective film. Common electrodes are formed on the protective film in order to be in a line with data line.

Description

Thin film transistor array of horizontal electornic field applying type

1 is a view schematically showing a conventional horizontal field application liquid crystal display device.

2A and 2B are diagrams illustrating an electric field formed in a pixel region of the liquid crystal display shown in FIG. 1 and driving characteristics of the liquid crystal.

3 is a plan view illustrating a horizontal field applied thin film transistor array according to an embodiment of the present invention.

FIG. 4 is a cross-sectional view of the thin film transistor array shown in FIG. 3 taken along the line "I-I '" and the line "II-II'";

5A and 5B are a plan view and a cross-sectional view for explaining a first mask process for manufacturing the thin film transistor array shown in FIGS. 3 and 4.

6A and 6B are a plan view and a cross-sectional view for explaining a second mask process of manufacturing the thin film transistor array shown in FIGS. 3 and 4.

7A and 7B are a plan view and a cross-sectional view for illustrating a third mask process of manufacturing the thin film transistor array shown in FIGS. 3 and 4.

8A and 8B are a plan view and a cross-sectional view for explaining a fourth mask process for manufacturing the thin film transistor array shown in FIGS. 3 and 4.

9A and 9B are a plan view and a cross-sectional view for explaining a fifth mask process of manufacturing the thin film transistor array shown in FIGS. 3 and 4.

10A and 10B are a plan view and a cross-sectional view for explaining a sixth mask process for manufacturing the thin film transistor array shown in FIGS. 3 and 4.

<Explanation of symbols for the main parts of the drawings>

30: semiconductor pattern 30T: storage area

30D: drain region 30C: channel region

30S: source area 30a: channel link area

30b: storage link area 32: gate line

32a: gate storage electrode 32G: gate electrode

34: data line 34S: source electrode

34D: drain electrode 37: common electrode

37a: data superimposition portion 37b: pixel portion

38 pixel electrode finger portion 41 substrate

45 gate insulating film 47 interlayer insulating film

40S: source contact hole 40D: drain contact hole

49: protective film 50: pixel contact hole

The present invention relates to a horizontal field applied thin film transistor array. In particular, the present invention relates to a horizontal field applied thin film transistor array capable of improving transmittance.

The liquid crystal display device displays an image by adjusting the light transmittance of the liquid crystal using an electric field. Such liquid crystal displays are roughly classified into a vertical electric field application type and a horizontal electric field application type according to the direction of the electric field for driving the liquid crystal.

In the vertical field applying liquid crystal display, the liquid crystal is driven by a vertical electric field formed between the pixel electrode and the common electrode disposed to face the upper and lower substrates. Such a vertical field application liquid crystal display device has an advantage of large aperture ratio but a narrow viewing angle.

The horizontal field application type liquid crystal display drives a liquid crystal by a horizontal electric field between a pixel electrode and a common electrode arranged side by side on a lower substrate. Such a horizontal field application liquid crystal display has a wide viewing angle.

Referring to FIG. 1, a horizontal field application type liquid crystal display includes a thin film transistor array 10 and a color filter array 20 facing each other with a liquid crystal 9 interposed therebetween.

The color filter array 20 includes a black matrix 3, a color filter 5, and an overcoat layer 7 sequentially formed on the upper substrate 1. The black matrix 3 serves to prevent light leakage and to prevent optical interference between neighboring color filters. The color filter 5 can display colors by including red (R), green (G), and blue (B). The overcoat layer 7 serves to planarize the upper substrate 1 on which the black matrix 3 and the color filter 5 are formed.

The thin film transistor array 10 is connected to the gate line 12 and the data line 14 and the gate line 12 and the data line 14, which cross each other on the lower substrate 11 to define a pixel region. The thin film transistor TFT, the pixel electrode 18 connected to the thin film transistor TFT, the common electrode 22 parallel to the pixel electrode 18, and the common line 16 connected to the common electrode 22 are connected. Include. Here, the common electrode 22 and the pixel electrode 18 include portions formed in the form of slits, and the slits are formed to be parallel to each other in the pixel area.

The thin film transistor TFT supplies the data signal from the data line 14 to the pixel electrode 18 in response to the gate signal from the gate line 12. A horizontal electric field is formed between the pixel electrode 18 supplied with the data signal through the thin film transistor TFT and the common electrode 22 supplied with the reference voltage through the common line 16. The liquid crystal 9 rotates by this horizontal electric field. The degree of rotation of the liquid crystal 9 is adjusted in accordance with the data signal. As described above, the horizontal field application type liquid crystal display realizes an image by controlling the degree of rotation of the liquid crystal 9 by the horizontal electric field so that the light transmittance through the pixel region is changed.

An alignment layer for aligning the liquid crystal 9 is further formed on the lower substrate 11 on which the thin film transistor array 10 is formed and the upper substrate 1 on which the color filter array 20 is formed. Since the alignment film has an orientation by the rubbing process, the initial alignment state of the liquid crystal 9 is determined according to the rubbing direction.

Polarizers (not shown) are further formed on both surfaces of the liquid crystal cell including the thin film transistor array 10 and the color filter array 20 facing each other with the liquid crystal 9 therebetween.

The polarizer serves to transmit light having the same optical axis as its optical axis. Since the optical axes of the polarizing plates formed on both sides of the liquid crystal cell are attached to be orthogonal to or parallel to each other, the intensity of transmitted light is adjusted according to the degree of rotation of the optical axis while the light is transmitted through the liquid crystal cell so that the liquid crystal display device can express gray scales.

2A and 2B are diagrams illustrating an electric field formed in a pixel region of the liquid crystal display of FIG. 1 and driving characteristics of the liquid crystal. Hereinafter, the liquid crystal 9 of FIG. 1 is shown separately from the liquid crystal 9a in a state where no electric field is formed and the liquid crystal 9b in a state where an electric field is formed.

2A and 2B, when no electric field 29 is formed between the pixel electrode 18 and the common electrode 22, the liquid crystal 9a maintains an initial alignment state in which its major axis is parallel to the rubbing direction. On the other hand, when the electric field 29 is formed between the pixel electrode 18 and the common electrode 22, the liquid crystal 9b rotates to be parallel to the electric field 29 direction. At this time, the degree of rotation of the liquid crystal 9b must match the design value in consideration of the optical axis of the polarizing plate so that accurate gradation can be expressed. However, the electric field 29 formed between the pixel electrode 18 and the common electrode 22 is distorted in the partial region A so that the degree of rotation of the liquid crystal 9b does not match the designed value.

The reason why the electric field 29 formed between the pixel electrode 18 and the common electrode 22 is distorted in the partial region A is because the pixel electrode 18 and the common electrode 22 each receive a driving signal to generate a horizontal electric field. This is because it has a specific structure to form. In more detail, the horizontal field application type liquid crystal display includes the common electrode 22 and the pixel electrode 18 side by side in the pixel region to form a horizontal electric field as described above. Here, the pixel electrode 18 connects the pixel electrode finger portions 18a parallel to the common electrode 22 and the pixel electrode finger portions 18a and the drain electrode of the thin film transistor through the drain contact hole 25. It is divided into the pixel electrode connection part 18b connected to 14D. The pixel electrode connecting portion 18b is formed in a direction perpendicular to the pixel electrode finger portions 18a to supply the pixel signal from the thin film transistor to the pixel electrode finger portions 18a to connect the pixel electrode finger portions 18a. do. The pixel electrode finger 18a receives a pixel signal from the pixel electrode connector 18b to form a horizontal electric field with the common electrode 22. The common electrode 22 is formed in parallel with the pixel electrode finger portions 18a and is connected to the common line 16 that supplies a reference voltage. The common line 16 is formed in a direction perpendicular to the common electrode 22 and connected to the common electrode 22 to supply a reference voltage to the common electrode 22. In addition, the common electrode 22, the common line 16, the pixel electrode finger 18a, and the pixel electrode connection 18b may be formed of a transparent metal on the same layer to improve transmittance.

Due to the above-described structural features, the driving signal flowing along the pixel electrode finger portion 18a and the common line 16 distorts the horizontal electric field formed between the common electrode 22 and the pixel electrode finger portion 18a. . As a result, even if an electric field is formed in the region adjacent to the pixel electrode connection portion 18b and the common line 16, the disclination region A in which the liquid crystal 9b rotates differently from the designed value is generated. The abnormal driving of the liquid crystal 9b in the declining region A not only expresses the gray scale correctly but also causes light leakage when displaying black, thereby lowering the contrast ratio. In order to prevent this, a method of covering the disclination region A with a black matrix has been proposed. However, since the opening region of the liquid crystal cell is reduced, the transmittance of the liquid crystal display is reduced. As described above, the decrease in transmittance caused by the disclination region A is more serious in a smaller liquid crystal display device.

An object of the present invention is to provide a horizontal field applied thin film transistor array capable of improving transmittance.

In order to achieve the above object, a horizontal field applied thin film transistor array according to an embodiment of the present invention is a semiconductor pattern of a thin film transistor formed on a substrate; A gate insulating layer covering the semiconductor pattern; A gate line formed on the gate insulating layer, the gate line including a gate electrode of the thin film transistor; An interlayer insulating layer covering the gate line; A data line defining a pixel region crossing the gate line and including a source electrode of the thin film transistor and formed on the interlayer insulating layer; A drain electrode of the thin film transistor separated from the data line and formed on the interlayer insulating film; A passivation layer covering the data line and the drain electrode; Pixel contact holes penetrating the passivation layer to expose the drain electrode; Common electrodes formed on the passivation layer to be parallel to the data line; A common line formed on the passivation layer to be parallel to the gate line and connecting the common electrodes; And pixel electrode finger parts alternately with the common electrodes and covering the pixel contact holes one-to-one and parallel to the common electrodes and connected to the drain electrode.

The semiconductor pattern may include: a source region connected to the source electrode; A drain region connected to the drain electrode; And a channel region connected to the source region and the drain region and overlapping the gate line.

The semiconductor device may further include a gate storage electrode extending from the previous or next gate line of the gate line, and the semiconductor pattern may further include a storage region connected to the drain region and overlapping the gate storage electrode.

The gate storage electrode and the storage area overlap with a data line preceding or next to the data line.

The semiconductor pattern further includes a storage link region formed between the storage region and the drain region to connect the storage region and the drain region.

The storage link region overlaps the pixel electrode finger.

The semiconductor pattern further includes a channel link region formed between the separated channel regions.

The common electrodes may include a data overlapping part overlapping the data line; And a pixel portion formed in the pixel area.

The common electrodes, the common line, and the pixel electrode finger parts formed of a transparent conductive metal.

The gate line is formed between the drain electrode in the gate line direction and an end of the common electrodes.

Other objects and advantages of the present invention other than the above object will be apparent from the description of the preferred embodiment of the present invention with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 3 to 10B.

3 is a plan view illustrating a horizontal field applied thin film transistor array according to an exemplary embodiment of the present invention. FIG. 4 is a cross-sectional view of the thin film transistor array shown in FIG. 3 taken along lines "I-I '" and "II-II'".

3 and 4, the horizontal field-applied thin film transistor array according to the exemplary embodiment of the present invention crosses each other with the interlayer insulating layer 47 therebetween on the substrate 41 to define a pixel region 32. And a plurality of common electrodes formed in parallel with the data line 34 with the thin film transistor TFT connected to the data line 34, the gate line 32, and the data line 34 and the passivation layer 49 interposed therebetween. (37), parallel to the common line 36 and common electrodes 37 which are formed in parallel with the gate line 32 with the passivation layer 49 therebetween to connect the common electrodes 37. And pixel electrode finger portions 38 connected to the thin film transistor TFT. In addition, the horizontal field-applied thin film transistor array according to the embodiment of the present invention further includes a storage capacitor Cst connected to the thin film transistor TFT.

The gate line 32 supplies a gate signal to the thin film transistor TFT, and the data line 34 supplies a data signal to the thin film transistor TFT. To this end, the gate line 32 includes the gate electrode 32G of the thin film transistor TFT, and the data line 34 includes the source electrode 34S of the thin film transistor TFT.

The thin film transistor TFT supplies the data signal of the data line 34 to the pixel electrode fingers 38 in response to the gate signal of the gate line 32. To this end, the thin film transistor TFT includes a gate electrode 32G included in the gate line 32, a source electrode 34S included in the data line 34, and a drain electrode 34D connected to the pixel fingers 38. And a semiconductor pattern 30 formed under the gate line 32 with the gate insulating layer 45 therebetween.

The semiconductor pattern 30 is formed in a pattern connected along the gate electrode 32G, the source electrode 34S, and the drain electrode 34D. The semiconductor pattern 30 is connected to the source region 30S overlapping the source electrode 34S, the drain region 30D overlapping the drain electrode 34D, and the source region 30S and the drain region 34D. The channel region 30C overlapped with the gate electrode 32G. The source region 30S is exposed through the source contact hole 40S penetrating the interlayer insulating film 47 and the gate insulating film 45 to be connected to the source electrode 34S. The drain region 30D is connected to the drain electrode 34D through the drain contact hole 40D that penetrates the interlayer insulating film 47 and the gate insulating film 45 to expose the drain region 30D. Lightly Doped Drain with n-impurities implanted between the channel region 30C and the source region 30S and between the channel region 30C and the drain region 30D to reduce the off current of the thin film transistor TFT. The area may be further formed. In addition, the semiconductor pattern 30 may include a channel link region formed between the channel regions 30C adjacent to the source electrode 34S and the channel region 30C adjacent to the drain region 30D. 30a) further.

A buffer layer 43 may be further formed between the semiconductor pattern 30 and the substrate 41 to prevent a foreign substance from flowing into the semiconductor pattern 30 from the substrate 41.

The common electrodes 37 are connected to a driving circuit and connected to a common line 36 that supplies a reference voltage (hereinafter, a common voltage) for driving a liquid crystal. The common line 36 is formed of a transparent conductive metal together with the common electrodes 37 to improve transmittance of the liquid crystal display. In addition, the common electrodes 37 include a data overlapping portion 37a overlapping the data line 34 as well as the pixel portion 37b formed in the pixel area in order to improve transmittance of the liquid crystal display. The data overlapping portion 37a enlarges the area where the horizontal electric field is applied to enlarge the area where the liquid crystal is driven, thereby improving transmittance of the liquid crystal display.

The pixel electrode fingers 38 are formed in the pixel area and are formed to be parallel to the common electrodes 37 and alternately to the common electrodes 37. In addition, the pixel electrode fingers 38 are formed of a transparent conductive metal like the common electrodes 37 to further improve transmittance. The pixel electrode fingers 38 are connected to the drain electrode 34D to receive a data signal of the data line 34. To this end, the pixel electrode finger parts 38 extend toward the drain electrode 34D to cover the pixel contact holes 50 exposing the drain electrode 34D with one-to-one (1: 1). As described above, the thin film transistor array according to the exemplary embodiment includes the pixel contact holes 50 corresponding to the pixel electrode finger parts 38 in a one-to-one manner, so that the pixel electrode finger parts 38 are directly connected to the drain electrode 34D. Therefore, it is not necessary to form a pixel electrode connection part separately to supply a data signal. Accordingly, the electric field formed between the pixel electrode finger portions 38 and the common electrodes 37 may be slightly distorted by the data signal flowing through the drain electrode 34D in parallel with the gate line 32. However, since the drain electrode 34D has the passivation layer 49 therebetween, the influence on the electric field is significantly smaller than that of the conventional pixel electrode connecting portion formed on the same layer as the pixel electrode finger 38 and the common electrode 37. Accordingly, the thin film transistor array according to the embodiment of the present invention can reduce the disclination region by removing the pixel electrode connection part, thereby improving the transmittance of the horizontal field application liquid crystal display device. In addition, the horizontal field applied thin film transistor array according to the exemplary embodiment of the present invention may further include an electric field distortion part generated by the drain electrode 34D in parallel with the gate line 32 in order to further improve the transmittance of the liquid crystal display device. Overlap with (32). The gate line 32 and the field distortion portion are masked by the black matrix to improve the contrast ratio. In the horizontal field-applied thin film transistor array according to the exemplary embodiment of the present invention, since the field distortion part of the drain electrode 34D is overlapped with the gate line 32, the portion covered by the black matrix can be reduced. The transmittance can be improved. The gate line 32 according to an exemplary embodiment of the present invention has a drain electrode 34D and a common electrode in a direction parallel to the gate line 32 in order to overlap the electric field distortion part of the drain electrode 34D with the gate line 32. 37) It is formed to pass between the ends.

The storage capacitor Cst has a data signal from a thin film transistor TFT connected to an arbitrary (nth, n is natural number) gate line 32 and an arbitrary (mth, m is natural number) data line 34. The pixel electrode fingers 38 can be charged and held. To this end, the thin film transistor array according to the embodiment of the present invention may include a gate storage electrode connected to the previous (n−1) th or next (n + 1th) gate line 32 of an arbitrary (nth) gate line. 32a and the storage region 30T of the semiconductor pattern 30. The storage region 30T of the semiconductor pattern 30 is connected to the drain region 30D of the semiconductor pattern 30 and overlaps the gate storage electrode 32a with the gate insulating layer 45 interposed therebetween, so that the storage capacitor Cst Configure The storage area 30T of the gate storage electrode 32a and the semiconductor pattern 30 according to an exemplary embodiment of the present invention may have an arbitrary (mth, m is a natural number) data line 34 to further improve transmittance of the liquid crystal display. Is overlapped with the previous (m-1) th or the next (m + 1) th data line 34. In this case, the semiconductor pattern 30 further includes a storage link region 30L formed between the storage region 30T and the drain region 30D to connect the storage region 30T and the drain region 30D. The storage link region 30L may be formed to overlap the pixel electrode finger 38 adjacent to the data line 34 to prevent a decrease in transmittance of the liquid crystal display.

As a result of applying the thin film transistor array according to the embodiment of the present invention shown in FIGS. 3 and 4 to a 2.2-inch liquid crystal display device having a resolution of 320 × 240 (pixel row direction pixels × pixel column direction pixels), It is about 2% higher than the pixel electrode connection part.

Hereinafter, a method of manufacturing a thin film transistor array according to an exemplary embodiment of the present invention will be described with reference to FIGS. 5A to 10B.

5A and 5B, a buffer layer 43 is formed on a substrate 41, and a semiconductor pattern 30 is formed thereon by a first mask process including a photolithography process and an etching process.

Specifically, the buffer layer 43 is formed by depositing an inorganic insulating material such as silicon oxide (SiO ₂ ) on the substrate 41. The semiconductor pattern 30 is formed by forming an amorphous silicon thin film or a polysilicon thin film on the buffer film 43, and then patterning the polysilicon thin film by a photolithography process and an etching process using a first mask. The polysilicon thin film is formed by forming and crystallizing an amorphous silicon thin film. As a method of crystallizing the amorphous silicon thin film, a laser annealing method, a solid phase crystallization method (hereinafter referred to as "SPC") method, and the like are used. Since polysilicon has about 100 times faster charge mobility than amorphous silicon, it is more effective when applied to thin film transistor arrays with built-in driving circuits requiring high response speed.

6A and 6B, a gate insulating layer 45 and a gate metal layer are formed on the buffer layer 43 on which the semiconductor pattern 30 is formed. Thereafter, the gate metal layer is patterned through a second mask process including a photolithography process and an etching process to form a gate pattern including the gate line 32 and the gate storage line 32a. Thereafter, n + impurities are implanted into the semiconductor pattern 30 using the gate pattern as a mask to form source regions, drain regions, channel link regions, and storage link regions 30S, 30D, 30a, and 30b.

As the gate insulating layer 45, an inorganic insulating material such as silicon oxide (SiO ₂ ), silicon nitride (SiNx), or the like is used, and as the gate metal layer, Mo, Ti, Cu, AlNd, Al, Cr, Mo alloy, Cu alloy, Al Metal materials, such as alloys, etc. are laminated | stacked in more than a single layer or a double layer.

7A and 7B, an interlayer insulating layer 47 is formed on the gate insulating layer 45 on which the gate pattern is formed. Subsequently, the interlayer insulating layer 47 and the gate insulating layer 45 are patterned through a third mask process including a photolithography process and an etching process to expose the source region 30S and the drain region ( A drain contact hole 40D exposing 30D is formed.

As the interlayer insulating film 47, an inorganic insulating material such as silicon oxide (SiO ₂ ), silicon nitride (SiNx), or the like is used.

8A and 8B, a source / drain metal layer is formed on the interlayer insulating layer 47. Thereafter, the source / drain metal layer is patterned through a fourth mask process including a photolithography process and an etching process to form a source / drain pattern including the data line 34 and the drain electrode 34D.

As the source / drain metal layer, a metal material such as Mo, Ti, Cu, AlNd, Al, Cr, Mo alloy, Cu alloy, Al alloy, or the like laminated with a single layer or two or more layers is used.

9A and 9B, the passivation layer 49 is formed on the interlayer insulating layer 47 on which the source / drain patterns are formed, and the passivation layer 49 is formed through a fifth mask process including a photolithography process and an etching process. A pixel contact hole 50 is formed through which the drain electrode 34D is exposed.

As the protective film 49, an organic insulating material or an inorganic insulating material such as silicon oxide (SiO ₂ ), silicon nitride (SiNx), or the like is used.

Referring to FIGS. 10A and 10B, after forming a transparent metal layer on the passivation layer 49, the transparent metal layer is patterned through a sixth mask process including a photolithography process and an etching process. The transparent conductive pattern including the common electrode 37 and the common line 36 is formed.

Examples of the transparent metal layer include indium tin oxide (ITO), tin oxide (TO; tin oxide), indium zinc oxide (IZO; indium zinc oxide), and indium tin zinc oxide (ITZO). Is used.

As described above, the horizontal field application type liquid crystal display according to the exemplary embodiment of the present invention may include pixel contact holes that correspond to the pixel electrode finger parts one-to-one and expose the drain electrode, thereby eliminating the pixel electrode connection portion parallel to the gate line. The transmittance of the liquid crystal display device can be improved.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (10)

A semiconductor pattern of the thin film transistor formed on the substrate; A gate insulating layer covering the semiconductor pattern; A gate line formed on the gate insulating layer, the gate line including a gate electrode of the thin film transistor; An interlayer insulating layer covering the gate line; A data line defining a pixel region crossing the gate line and including a source electrode of the thin film transistor and formed on the interlayer insulating layer; A drain electrode of the thin film transistor separated from the data line and formed on the interlayer insulating film; A passivation layer covering the data line and the drain electrode; Pixel contact holes penetrating the passivation layer to expose the drain electrode; Common electrodes formed on the passivation layer to be parallel to the data line; A common line formed on the passivation layer to be parallel to the gate line and connecting the common electrodes; And And pixel electrode finger parts alternately with the common electrodes and covering the pixel contact holes one-to-one and parallel to the common electrodes, the pixel electrode fingers being connected to the drain electrode. The method of claim 1, The semiconductor pattern is A source region connected to the source electrode; A drain region connected to the drain electrode; And And a channel region connected to the source region and the drain region and overlapping the gate line. The method of claim 2, A gate storage electrode extending from the previous or next gate line of the gate line, And the semiconductor pattern further comprises a storage region connected to the drain region and overlapping the gate storage electrode. The method of claim 3, wherein The gate storage electrode and the storage area are And a horizontal field applied thin film transistor array overlapping the previous or next stage data line of the data line. The method of claim 4, wherein The semiconductor pattern is And a storage link region formed between the storage region and the drain region to connect the storage region and the drain region. The method of claim 5, wherein The storage link area is And a horizontal field applied thin film transistor array superimposed on the pixel electrode finger portion. The method of claim 2, The semiconductor pattern is And a channel link region formed between the separated channel regions. The method of claim 1, The common electrodes A data overlapping part overlapping the data line; And And a pixel portion formed in the pixel region. The method of claim 1, And the common electrodes, the common line, and the pixel electrode finger portions formed of a transparent conductive metal. The method of claim 1, The gate line is And a horizontal field applied thin film transistor array formed between the drain electrode in the gate line direction and the ends of the common electrodes.

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