KR20090073686A - Method of manufacturig thin film transistor substrate - Google Patents

Abstract

A method of manufacturing thin film transistor substrate is provided to obtain the channel length of the thin film transistor without a reduction of processing margin by using masks having the different transmittance. The gate electrode pattern is formed on the substrate(101) having an electrostatic protection circuit part, a gate driving unit, and a pixel display. The gate insulating layer is formed in the top of the substrate in which the gate electrode pattern is formed. By using masks having the different transmittance, a source and drain electrode(308,310) pattern, and a semiconductor pattern(312) group are formed. The protective film(318) including a contact hole is formed so that the drain electrode of the pixel display is exposed on the substrate in which source and drain electrode pattern are formed. The pixel electrode(332) is formed on the protective film.

Description

The manufacturing method of a thin film transistor substrate {METHOD OF MANUFACTURIG THIN FILM TRANSISTOR SUBSTRATE}

The present invention relates to a method of manufacturing a thin film transistor substrate capable of preventing a process margin reduction during the manufacturing process of the thin film transistor substrate.

The liquid crystal display displays an image by adjusting the light transmittance of the liquid crystal having dielectric anisotropy using an electric field. To this end, the liquid crystal display device includes a liquid crystal display panel for displaying an image and a driving circuit for driving the liquid crystal display panel.

The liquid crystal display panel includes a color filter substrate and a thin film transistor substrate bonded by a sealing material with a liquid crystal interposed therebetween.

The color filter substrate has a black matrix and a color filter and a common electrode stacked on an insulating substrate.

The thin film transistor substrate includes a gate line and a data line intersecting on a lower insulating substrate, and a thin film transistor connected between the gate line and the data line and the pixel electrode. The thin film transistor supplies the data signal from the data line to the pixel electrode in response to the scan signal from the gate line.

The driving circuit includes a data driver for driving a plurality of data lines and a gate driver for driving a plurality of gate lines.

In order to reduce the material cost, reduce the number of processes, and shorten the process time, a gate in panel technology that forms a gate driver on the liquid crystal display panel is used. As described above, the driving circuit unit is formed in the pixel display unit displaying the image and the non-display area outside the pixel display unit to drive the image, and the thin film transistor is formed in the pixel display unit and the non-display area. The thin film transistors formed in each of these regions have different densities and are formed in different channels. However, the density of the thin film transistors in each region is also produced without considering the channel length, which causes defects due to process margin reduction.

In order to solve the above problems, the present invention is to provide a method for manufacturing a thin film transistor substrate that can prevent the process margin reduction during the manufacturing process of the thin film transistor substrate.

In order to achieve the above technical problem, a method of manufacturing a thin film transistor substrate according to the present invention includes the steps of forming a gate electrode pattern on each of the regions to be formed on the antistatic circuit portion, the gate driver, and the pixel display portion; Forming a source and drain electrode pattern and a semiconductor pattern group for each region by forming a gate insulating layer on the substrate on which the gate electrode pattern is formed and using a mask having a different transmittance for each region; Forming a passivation layer including a contact hole on the substrate on which the source and drain electrode patterns are formed to expose the drain electrode of the pixel display unit; And forming a pixel electrode on the passivation layer.

In the method of manufacturing the thin film transistor substrate according to the present invention, a mask having different transmittances is used in consideration of a semiconductor pattern, a source, and a drain electrode of the thin film transistor formed in each region of the pixel display unit, the gate driver, and the antistatic circuit unit. Accordingly, the channel length of the thin film transistor desired by the user can be implemented without reducing the process margin for each region.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to FIGS. 1 to 8.

1 is a plan view illustrating a liquid crystal display panel according to an exemplary embodiment of the present invention.

Referring to FIG. 1, a liquid crystal display panel includes an image display unit 100 displaying an image, a gate driver 150 driving a gate line GL of the pixel display unit 100, and a data line of the pixel display unit 100. And a data driver (not shown) for driving the DL and an antistatic circuit unit 140 for preventing static electricity. To this end, the liquid crystal display panel includes a color filter substrate and a thin film transistor substrate bonded to each other with the liquid crystal layer interposed therebetween.

The color filter substrate has a color filter, a black matrix, and a common electrode.

The color filter includes red, green, and blue color filters R, G, and B to implement color. The red, green, and blue color filters R, G, and B each have red, green, and blue colors by absorbing or transmitting light of a specific wavelength through the red, green, and blue pigments they contain.

The black matrix is formed to distinguish the sub-pixel region where the color filter is to be formed and to overlap the gate line GL, the data line DL, and the thin film transistor TFT of the thin film transistor substrate TFT. The black matrix blocks the transmitted light generated by the undesired liquid crystal array to improve the contrast of the liquid crystal display device and prevents light leakage current of the thin film transistor TFT by blocking direct light irradiation with the thin film transistor TFT.

The common electrode is formed on the color filter. The common electrode applies a common voltage to the liquid crystal corresponding to the pixel voltage of the pixel electrode. To this end, the common electrode is formed of a material such as indium tin oxide (ITO) or indim zinc oxide (IZO) that is transparent and conductive. In addition, an overcoat layer for planarizing the surface of the color filter may be further formed between the color filter and the common electrode.

The thin film transistor substrate includes a thin film transistor TFT and a pixel electrode.

The thin film transistor TFT supplies a video signal of the data line DL to the pixel electrode 332 in response to a scan signal of the gate line GL. To this end, the thin film transistor TFT may include a first gate electrode 302 connected to the gate line GL, a first source electrode 308 connected to the data line DL, and a first electrode connected to the pixel electrode 332. A first semiconductor overlapping the first gate electrode 306 with the first drain electrode 310 and the gate insulating layer 106 interposed therebetween to form a channel between the first source electrode 308 and the first drain electrode 310. Ohmic contact of the first semiconductor pattern 312 formed on the active layer 314 except for the channel portion for ohmic contact with the active layer 314, the first source electrode 308, and the first drain electrode 310 of the pattern 312. Layer 316.

The gate line GL supplies a scan signal from the gate driver 150 to the first gate electrode 306 of the thin film transistor TFT. The data line DL supplies a video signal to the first source electrode 308 of the thin film transistor TFT from the data driver. The gate line GL and the data line DL are formed to cross each other to form a sub pixel area.

The pixel electrode 332 is connected to the first drain electrode 210 of the thin film transistor TFT formed in the pixel display unit 100 through the first contact hole 320 and is formed on the passivation layer 318. The pixel electrode 222 is formed of a transparent conductive film. Here, when the video signal is supplied through the thin film transistor TFT, the pixel electrode 332 generates an electric field together with the common electrode supplied with the common voltage, thereby changing the arrangement direction of the liquid crystal molecules between the two electrodes. Gradation is realized by varying the light transmittance passing through.

The passivation layer 318 is formed between the thin film transistor TFT and the pixel electrode 322 to protect the data line DL and the thin film transistor TFT. The passivation layer 318 may be formed of a double layer of an inorganic and an organic passivation layer or a single layer formed of only one of them.

The gate driver 150 sequentially supplies scan pulses to the gate lines GL. The gate driver 150 includes a plurality of thin film transistors and is formed in the non-display area of the liquid crystal display panel. The thin film transistor of the gate driver 150 has the same configuration as the thin film transistor TFT of the pixel display unit 100. The thin film transistor of the gate driver 150 forms a gate insulating layer 106 on the second gate electrode 202 on the substrate 101, and overlaps the second semiconductor pattern 212 on the gate insulating layer 106. The second source electrode 208 and the second drain electrode 210 overlap with the second gate electrode 206 with the second source electrode 208, the second drain electrode 210, and the gate insulating layer 106 interposed therebetween. A second layer formed on the active layer 214 except for the channel portion for ohmic contact with the active layer 214, the second source electrode 208, and the second drain electrode 210 of the second semiconductor pattern 212, which forms a channel therebetween. The ohmic contact layer 216 of the two semiconductor patterns 212 is included.

The antistatic circuit unit 140 is formed in the non-display area of the liquid crystal display panel to block external static electricity that may be applied to the pixel display unit 100. The antistatic circuit unit 140 protects the pixel display unit 100 by inducing and distributing static electricity when external static electricity enters the pixel display unit 100 through the gate line GL and the data line DL. To this end, the antistatic circuit unit 140 forms at least one diode. The diode of the antistatic circuit unit 140 has the same configuration as the thin film transistor TFT of the pixel display unit 100.

The diode of the antistatic circuit portion 140 forms a gate insulating film 106 on the third gate electrode 102 on the substrate 101, and overlaps the third semiconductor pattern 112 on the gate insulating film 106. The third source electrode 108 and the third drain electrode 110 are overlapped with the third gate electrode 106 with the third source electrode 108, the third drain electrode 110, and the gate insulating layer 106 interposed therebetween. A first layer formed on the active layer 114 except for the channel portion for ohmic contact with the active layer 114, the third source electrode 108, and the third drain electrode 110 of the third semiconductor pattern 112 forming a channel therebetween. And an ohmic contact layer 116 of the three semiconductor patterns 112.

3 to 7 are cross-sectional views illustrating a method of manufacturing a thin film transistor substrate according to the present invention. 5A is a plan view of a mask pattern for each region used in the second mask process according to the present invention.

Referring to FIG. 3, a gate metal pattern including first to third gate electrodes 302, 202, and 102 is formed on the substrate 101.

Specifically, the gate metal layer is formed on the substrate 101 through a deposition method such as a sputtering method. As the gate metal layer, a single metal material such as molybdenum (Mo), titanium (Ti), copper (Cu), aluminum neodium (AlNd), aluminum (Al), chromium (Cr), Mo alloy, Cu alloy, Al alloy, etc. It is used as a layer, or it is used by the structure which laminated | stacked two or more layers using the said metal. Subsequently, the gate metal layer is patterned by a photolithography process and an etching process to form a gate metal pattern including the first to third gate electrodes 302, 202, and 102.

Referring to FIG. 4, the gate insulating layer 106 is formed on the substrate 101 on which the gate metal pattern is formed, and the first to third source electrodes 308, 208, 108, and the first to third drain electrodes 310, 210, and 110 are disposed thereon. A first to third semiconductor pattern 312, 212, and 112 including a source and drain electrode pattern including an active layer and an active layer 314, 214, 114, and an ohmic contact layer 316, 216, 116 superimposed thereunder for each region. A semiconductor pattern group is formed. The semiconductor pattern groups 312, 212, and 112 and the source and drain electrode patterns are formed in one mask process using a diffraction exposure mask or half tone. As shown in FIG. 4, the thin film transistor of the pixel display unit 100, the thin film transistor of the gate driver 150, and the diode of the antistatic unit 140 have different channel lengths. Thus, the present invention uses a mask having a different transmittance for each region when forming a semiconductor pattern of a thin film transistor and a diode for each region.

Specifically, the gate insulating layer 106, the amorphous silicon layer 115, the amorphous silicon layer 117 doped with impurities (n + or p +) and the source / drain metal layer 111 on the substrate 101 on which the gate metal pattern group is formed. This is formed sequentially.

An inorganic insulating material such as silicon oxide (SiOx) or silicon nitride (SiNx) is used as the gate insulating layer 106, and molybdenum (Mo), titanium (Ti), copper (Cu), and aluminum are used as the source / drain metal layer 111. A metal material such as neodium (AlNd), aluminum (Al), chromium (Cr), Mo alloy, Cu alloy, Al alloy, or the like is used as a single layer, or a structure in which two or more layers using the metal are stacked.

After the photoresist is applied on the source / drain metal layer 111, the photoresist is exposed and developed by a photolithography process using the halftone mask 220, thereby forming first and second photoresist patterns 119A having a step difference. 119B) is formed. To this end, the mask 220 includes a blocking region S2, a transflective region S3, and a transmissive region S1 as shown in FIGS. 5A and 5B. In this case, a mask for forming the source and drain electrodes 108 and 110 and the semiconductor pattern 112 of the antistatic circuit unit 140 may form a compensation slit as shown in FIG. 5A.

The blocking region S2 is located in a region where a source and a drain of each of the pixel display unit 100, the gate driver 150, and the antistatic circuit unit 140 are to be formed, thereby blocking ultraviolet rays during the exposure process with the blocking layer 222. After the process, as shown in FIG. 5B, the first photoresist pattern 119A remains.

The transmissive region S1 transmits all ultraviolet rays so that the photoresist is removed as shown in FIG. 5B after development.

The transflective region S3 is positioned in a region where a channel of each of the thin film transistors of the pixel display unit 100, the gate driver 150, and the antistatic circuit unit 140 is to be formed, and partially transmits ultraviolet rays during the exposure process. As shown in FIG. 5B, a second photoresist pattern 119B thinner than the first photoresist pattern remains.

In this case, the transflective regions S3 have different thicknesses of the transflective materials 224, 226, and 228 so as to have different transmittances for respective regions of the pixel display unit 100, the gate driver 150, and the antistatic circuit unit 140. As shown in FIG. 8, the transflective materials 224, 226 and 228 have different transmittances of light depending on their thicknesses.

In other words, the thicker the transflective material 224, 226, 228, the smaller the transmittance of light. When the same light is irradiated when the channel lengths L1, L2, and L3 are wide in the order of the antistatic circuit unit 140, the gate driver 150, and the pixel display unit 100, the channel lengths L1, L2, and L3 may be reduced. As the width increases, the light is more affected by the light, and thus the anti-transmissive circuits 140, the gate driver 150, and the channel lengths L1, L2, L3 of the pixel display unit 100 are formed in order of the transflective materials 224, 226, 228. To form a thick thickness.

Accordingly, the transflective material 228 corresponding to the position where the channel L1 of the antistatic circuit unit 140 is to be formed is formed to have a transmittance of 25 to 35%, and the channel L2 of the gate driver 150. The transflective material 226 corresponding to the position to be formed is formed to have a transmittance of 30 to 40%, and the transflective material 224 corresponding to the position where the channel L3 of the pixel display unit 100 is to be formed. Is formed to have a transmittance of 35 to 45%.

Therefore, by using the mask 220 having different transmittances for each region of the pixel display unit 100, the gate driver 150, and the antistatic circuit unit 140, it is possible to prevent the process margin that occurs in the process.

In the etching process using the photoresist pattern, the source / drain metal layer 111, the amorphous silicon layer 115, and the amorphous silicon layer 117 doped with impurities (n-type or p-type) are patterned. As described above, the source and drain metal patterns and the semiconductor pattern group below them are formed. In this case, the first to third source electrodes 308, 208, and 108 and the first to third drain electrodes 310, 210, and 110 for each region are connected to each other.

Subsequently, by ashing the photoresist pattern by an ashing process using an oxygen (O ₂ ) plasma, the first photoresist pattern 119A is thinned as shown in FIG. 5D, and the second photoresist pattern 119B is removed. do. Subsequently, the first to third source and first to third drain metal layers exposed through the etching process using the ashed first photoresist pattern 119A, and the ohmic contact layer below are removed. Accordingly, the first to third source electrodes 308, 208, 108 and the first to third drain electrodes 310, 210, and 110 are separated and the active layers 314, 214, and 114 for each region are exposed.

Then, the first photoresist pattern 119A remaining on the source / drain metal pattern is removed by a strip process as shown in FIG. 5E.

Referring to FIG. 6, a passivation layer 318 is formed on the gate insulating layer 106 on which the source and drain electrode patterns are formed.

In detail, the passivation layer 318 is formed on the gate insulating layer 106 on which the source and drain electrode patterns are formed. The passivation layer 318 is formed of an inorganic insulating material such as the gate insulating layer 106 or an organic insulating material such as an acrylic resin. The protective film 318 is patterned by a photolithography process and an etching process to form a contact hole 320 penetrating the gate insulating film 106 and / or the protective film 318. The contact hole 320 is formed to pass through the passivation layer 318 to expose the drain electrode 310 of the pixel display unit.

Referring to FIG. 7, the pixel electrode 332 is formed on the passivation layer 318.

Specifically, the transparent conductive layer is formed on the protective film 318 through a deposition method such as sputtering. Tin oxide (TO), indium tin oxide (ITO), indium zinc oxide (IZO), indium tin zinc oxide (ITZO), etc. Is used. The transparent conductive layer is patterned by a photolithography process and an etching process to form a pixel electrode.

In the detailed description of the present invention described above with reference to the preferred embodiment of the present invention, those skilled in the art or those skilled in the art having ordinary knowledge of the present invention described in the claims to be described later It is apparent that various modifications and changes can be made in the present invention without departing from the spirit and scope of the invention.

1 is a plan view illustrating a liquid crystal display panel according to an exemplary embodiment of the present invention.

FIG. 2 is a cross-sectional view of the thin film transistor substrate formed in each region of the pixel display unit, the gate driver, and the antistatic circuit unit illustrated in FIG. 1.

3 is a cross-sectional view for describing a method of manufacturing the gate metal pattern illustrated in FIG. 2.

4 is a cross-sectional view for describing a method of manufacturing the semiconductor pattern, the source and the drain electrode pattern illustrated in FIG. 2.

5A through 5E are cross-sectional views illustrating a method of forming the semiconductor pattern, the source and the drain electrode pattern illustrated in FIG. 4 using a halftone mask.

FIG. 6 is a cross-sectional view for describing a method of manufacturing the protective film illustrated in FIG. 2.

FIG. 7 is a cross-sectional view for describing a method of manufacturing the pixel electrode illustrated in FIG. 2.

8 is a graph showing the transmittance according to the thickness of the transflective material of the halftone mask.

<Explanation of symbols for the main parts of the drawings>

100: pixel display portion 101: substrate

102, 202, 302: gate electrode 106, 206, 306: gate insulating film

108,208,308: source electrode 110,210,310: drain electrode

114,214,314: active layer 116,216,316: ohmic contact layer

140: antistatic circuit portion 150: gate driving portion

318: protective film 332: pixel electrode

220: mask 222: blocking layer

224,226,228: semipermeable material

Claims (6)

Forming a gate electrode pattern on each of the regions where the antistatic circuit portion, the gate driver, and the pixel display portion are to be formed on the substrate; Forming a source and drain electrode pattern and a semiconductor pattern group for each region by forming a gate insulating layer on the substrate on which the gate electrode pattern is formed and using a mask having a different transmittance for each region; Forming a passivation layer including a contact hole on the substrate on which the source and drain electrode patterns are formed to expose the drain electrode of the pixel display unit; Forming a pixel electrode on the passivation layer. The method of claim 1, The mask is A blocking region for blocking ultraviolet rays; A semi-transmissive region partially transmitting the ultraviolet rays; It includes a transmission region that transmits all the ultraviolet, The semi-transmissive region is a method of manufacturing a thin film transistor substrate, characterized in that to form a different transmittance by varying the thickness for each region. The method of claim 2, The transflective region corresponding to the position where the channel of the thin film transistor of the pixel display unit is to be formed has a transmittance of 25 to 35%. The method of claim 2, The transflective region corresponding to the position where the channel of the thin film transistor of the gate driver is to be formed has a transmittance of 30 to 40%. The method of claim 2, The transflective region corresponding to the position where the channel of the thin film transistor of the antistatic circuit part is to be formed has a transmittance of 35 to 45%. The method of claim 1, And the thin film transistors of the pixel display part, the gate driver, and the antistatic circuit part are formed at the same time.

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