KR20070117043A - Display device - Google Patents

Abstract

A display device is provided to form neighboring lines on different layers to double a width of a line on the same layer so as to reduce resistance by half. A display panel includes a gate line and a data line. A plurality of data driving integrated circuits is connected to the data line. A plurality of power lines(PL1~PL4) is connected between the data driving integrated circuits. The power line is formed by the same process as the gate line and the data line. The neighboring power lines of the power lines are disposed on different layers. Some of the power lines are formed on the same layer as the gate line, and the rest of the power lines are formed on the same layer as the data line.

Description

Display device {DISPLAY DEVICE}

With reference to the accompanying drawings will be described in detail the embodiments of the present invention to make the present invention clear.

1 is a block diagram of a liquid crystal display according to an exemplary embodiment of the present invention.

2 is an equivalent circuit diagram of one pixel of a liquid crystal display according to an exemplary embodiment of the present invention.

3 is a layout view of a liquid crystal display according to an exemplary embodiment of the present invention.

4 is an enlarged view of a portion of the power line shown in FIG. 3.

FIG. 5 is a cross-sectional view of the power line shown in FIG. 4 taken along the line V-V. FIG.

6A and 6B are diagrams showing the relationship between the width and the spacing of power lines positioned on the same layer, respectively.

<Description of Drawing>

3: liquid crystal layer 100: lower display panel

191: pixel electrode 200: upper display panel

230: color filter 270: common electrode

300: liquid crystal panel assembly 400: gate driver

500: data driver 600: signal controller

800: gray voltage generator

R, G, B: Input image data DE: Data enable signal

MCLK: Main Clock Hsync: Horizontal Sync Signal

Vsync: Vertical Sync Signal CONT1: Gate Control Signal

CONT2: data control signal DAT: digital video signal

Clc: Liquid Crystal Capacitor Cst: Keeping Capacitor

Q: switching element PL1-PL4: power line

SL: signal line

The present invention relates to a display device.

Recently, organic light emitting diode display (OLED), plasma display panel (PDP), liquid crystal display (liquid crystal display) in place of heavy and large cathode ray tube (CRT) Flat panel displays such as LCDs are being actively developed.

The PDP is a device for displaying characters or images using plasma generated by gas discharge, and the organic light emitting diode display displays characters or images by using electroluminescence of specific organic materials or polymers. The liquid crystal display applies an electric field to the liquid crystal layer interposed between the two display panels, and adjusts the intensity of the electric field to adjust the transmittance of light passing through the liquid crystal layer to obtain a desired image.

Such a display device may use a so-called chip on glass (COG) method in which a driving IC is directly mounted on a substrate instead of a flexible printed circuit board for cost reduction.

In this case, the wiring between each driving IC includes a signal line transferring a signal between the driving ICs and a power line transferring a power source such as a driving voltage. Such wiring is formed together with display signal lines such as gate lines and data lines. In particular, in the case of a power supply line, if the driving voltage required for the driving IC is insufficient due to the resistance present in the wiring, the operation of the entire display device is affected.

Accordingly, an object of the present invention is to provide a display device capable of reducing wiring resistance of a power line.

According to an embodiment of the present invention, a display device including a gate line and a data line, a plurality of data driver ICs connected to the data line, and a connection between the data driver ICs are provided. And a plurality of power lines, wherein the power lines are formed in the same process as the gate lines and the data lines, and neighboring power lines among the power lines are disposed on different layers.

In this case, some of the power lines may be formed on the same layer as the gate line, and others may be formed on the same layer as the data line.

Here, the spacing of the power lines disposed on the same layer among the power lines may be substantially the same as the width of the power lines.

The data driving IC may be mounted on the display panel.

On the other hand, the display device includes an insulating substrate, first and second power lines formed on the insulating substrate, a first insulating film formed on the first and second power lines, and a first insulating film formed on the first insulating film. And a third insulating film formed on the third and fourth power lines, and the third and fourth power lines.

Here, the widths of the first to fourth power lines are the same, and the interval between the first power line and the second power line or the distance between the third power line and the fourth power line is the first to fourth power source. It may be equal to the width of the line.

DETAILED DESCRIPTION Embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification. When a portion of a layer, film, region, plate, etc. is said to be "on top" of another part, this includes not only when the other part is "right on" but also another part in the middle. On the contrary, when a part is "just above" another part, there is no other part in the middle.

First, a display device according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 1 and 2, and a liquid crystal display device will be described as an example.

1 is a block diagram of a liquid crystal display according to an exemplary embodiment of the present invention, and FIG. 2 is an equivalent circuit diagram of one pixel of the liquid crystal display according to an exemplary embodiment of the present invention.

As shown in FIG. 1, a liquid crystal display according to an exemplary embodiment of the present invention includes a liquid crystal panel assembly 300, a gate driver 400, a data driver 500, and a data driver 500 connected thereto. The gray voltage generator 800 connected to the signal generator 500 and a signal controller 600 for controlling the gray voltage generator 800 are included.

The liquid crystal panel assembly 300 may include a plurality of signal lines G ₁ -G _n , D ₁ -D _m and a plurality of pixels PX connected to the plurality of signal lines G ₁ -G _n , D ₁ -D _m , and arranged in a substantially matrix form. Include. On the other hand, in the structure shown in FIG. 2, the liquid crystal panel assembly 300 includes lower and upper panels 100 and 200 facing each other and a liquid crystal layer 3 interposed therebetween.

The signal lines G ₁ -G _n and D ₁ -D _m are a plurality of gate lines G ₁ -G _n for transmitting a gate signal (also called a “scan signal”) and a plurality of data lines for transmitting a data signal ( D ₁ -D _m ). The gate lines G ₁ -G _n extend substantially in the row direction and are substantially parallel to each other, and the data lines D ₁ -D _m extend substantially in the column direction and are substantially parallel to each other.

Each pixel PX, for example, the pixel PX connected to the i-th (i = 1, 2,, n) gate line G _i and the j-th (j = 1, 2,, m) data line Dj. ) Includes a switching element Q connected to the signal line G _i D _j , a liquid crystal capacitor Clc, and a storage capacitor Cst connected thereto. Holding capacitor Cst can be omitted as needed.

The switching element Q is a three-terminal element of a thin film transistor or the like provided in the lower panel 100, the control terminal of which is connected to the gate line G _i , and the input terminal of which is connected to the data line D _j . The output terminal is connected to the liquid crystal capacitor Clc and the storage capacitor Cst.

The liquid crystal capacitor Clc has two terminals, the pixel electrode 191 of the lower panel 100 and the common electrode 270 of the upper panel 200, and the liquid crystal layer 3 between the two electrodes 191 and 270 is a dielectric material. Function as. The pixel electrode 191 is connected to the switching element Q, and the common electrode 270 is formed on the front surface of the upper panel 200 and receives the common voltage Vcom. Unlike in FIG. 2, the common electrode 270 may be provided in the lower panel 100. In this case, at least one of the two electrodes 191 and 270 may be formed in a linear or bar shape.

The storage capacitor Cst, which serves as an auxiliary part of the liquid crystal capacitor Clc, is formed by overlapping a separate signal line (not shown) and the pixel electrode 191 provided on the lower panel 100 with an insulator interposed therebetween. A predetermined voltage such as the common voltage Vcom is applied to the separate signal line. However, the storage capacitor Cst may be formed such that the pixel electrode 191 overlaps the front gate line directly above the insulator.

On the other hand, in order to implement color display, each pixel PX uniquely displays one of the primary colors (spatial division) or each pixel PX alternately displays the primary colors over time (time division). The desired color is recognized by the spatial and temporal sum of these primary colors. Examples of the primary colors include three primary colors such as red, green, and blue. FIG. 2 illustrates that each pixel PX includes a color filter 230 representing one of the primary colors in an area of the upper panel 200 corresponding to the pixel electrode 191 as an example of spatial division. Unlike FIG. 2, the color filter 230 may be formed above or below the pixel electrode 191 of the lower panel 100.

At least one polarizer (not shown) for polarizing light is attached to an outer surface of the liquid crystal panel assembly 300.

Referring back to FIG. 1, the gray voltage generator 800 generates two sets of gray voltage sets (or reference gray voltage sets) related to the transmittance of the pixel PX. One of the two sets has a positive value for the common voltage Vcom and the other set has a negative value.

A gate driver 400, a gate line (G ₁ -G _n) and is connected to the gate turn-on voltage (Von), and a gate signal consisting of a combination of a gate-off voltage (Voff), a gate line (G ₁ of the liquid crystal panel assembly 300 -G _n ).

The data driver 500 is connected to the data lines D ₁ -D _m of the liquid crystal panel assembly 300 and selects a gray voltage from the gray voltage generator 800 and uses the data line D ₁ as a data signal. -D _m ). However, when the gray voltage generator 800 provides only a predetermined number of reference gray voltages instead of providing all of the voltages for all grays, the data driver 500 divides the reference gray voltages to divide the gray voltages for all grays. Generate and select the data signal from it.

The signal controller 600 controls the gate driver 400, the data driver 500, and the like.

Each of the driving devices 400, 500, 600, and 800 may be mounted directly on the liquid crystal panel assembly 300 in the form of at least one integrated circuit chip, or may be a flexible printed circuit film (not shown). It may be mounted on the liquid crystal panel assembly 300 in the form of a tape carrier package (TCP) or mounted on a separate printed circuit board (not shown). Alternatively, these driving devices 400, 500, 600, and 800 may be integrated in the liquid crystal panel assembly 300 together with the signal lines G ₁ -G _n , D ₁ -D _m and the thin film transistor switching element Q. It may be. In addition, the driving devices 400, 500, 600, and 800 may be integrated into a single chip, in which case at least one of them or at least one circuit element constituting them may be outside the single chip.

Next, the operation of the liquid crystal display will be described in detail.

The signal controller 600 receives input image signals R, G, and B and an input control signal for controlling the display thereof from an external graphic controller (not shown). Examples of the input control signal include a vertical sync signal Vsync, a horizontal sync signal Hsync, a main clock MCLK, and a data enable signal DE.

The signal controller 600 properly processes the input image signals R, G, and B according to operating conditions of the liquid crystal panel assembly 300 based on the input image signals R, G, and B and the input control signal, and controls the gate. After generating the signal CONT1 and the data control signal CONT2, the gate control signal CONT1 is sent to the gate driver 400, and the data control signal CONT2 and the processed image signal DAT are transmitted to the data driver 500. Export to).

The gate control signal CONT1 includes a scan start signal STV indicating a scan start and at least one clock signal controlling an output period of the gate-on voltage Von. The gate control signal CONT1 may also further include an output enable signal OE that defines the duration of the gate-on voltage Von.

The data control signal CONT2 is a load for applying a data signal to the horizontal synchronization start signal STH and the data lines D ₁ -D _m indicating the start of image data transmission for the pixels PX in one row [bundling]. Signal LOAD and data clock signal HCLK. The data control signal CONT2 is also an inverted signal that inverts the voltage polarity of the data signal relative to the common voltage Vcom (hereinafter referred to as " polarity of the data signal " by reducing the " voltage polarity of the data signal for the common voltage &quot;) RVS) may be further included.

According to the data control signal CONT2 from the signal controller 600, the data driver 500 receives the digital image signal DAT for the pixels PX in one row (bundling), and each digital image signal DAT. By converting the digital image signal DAT into an analog data signal by selecting a gray scale voltage corresponding to), it is applied to the corresponding data lines D ₁ -D _m .

The gate driver 400 applies the gate-on voltage Von to the gate lines G ₁ -G _n in response to the gate control signal CONT1 from the signal controller 600, thereby applying the gate lines G ₁ -G _n . Turn on the switching element (Q) connected to. Then, the data signal applied to the data lines D ₁ -D _m is applied to the pixel PX through the switching element Q turned on.

The difference between the voltage of the data signal applied to the pixel PX and the common voltage Vcom is shown as the charging voltage of the liquid crystal capacitor Clc, that is, the pixel voltage. The arrangement of the liquid crystal molecules varies depending on the magnitude of the pixel voltage, thereby changing the polarization of light passing through the liquid crystal layer 3. The change in polarization is represented by a change in transmittance of light by a polarizer attached to the display panel assembly 300.

This process is repeated in units of one horizontal period (also referred to as "1H" and equal to one period of the horizontal sync signal Hsync and the data enable signal DE), thereby all the gate lines G ₁ -G _n. ), The gate-on voltage Von is sequentially applied to the data signal to all the pixels PX, thereby displaying an image of one frame.

When one frame ends, the state of the inversion signal RVS applied to the data driver 500 is controlled so that the next frame starts and the polarity of the data signal applied to each pixel PX is opposite to the polarity of the previous frame. "Invert frame"). In this case, the polarity of the data signal flowing through one data line is changed (eg, row inversion and point inversion) or the polarity of the data signal applied to one pixel row is different depending on the characteristics of the inversion signal RVS within one frame. (E.g. column inversion, point inversion).

3 is a layout view of a liquid crystal display according to an exemplary embodiment of the present invention. FIG. 4 is an enlarged view of a part of the power line shown in FIG. 3, and FIG. 5 is a VV line of the power line shown in FIG. 4. It is a cross-sectional view cut along. 6A and 6B are diagrams showing the relationship between the width and the spacing of power lines positioned on the same layer, respectively.

Referring to FIG. 3, a printed circuit board (PCB) 550 in which the signal controller 600, the gray voltage generator 800, and the like, and a power generator (not shown) generating power are located, is shown. The liquid crystal panel assembly 300 is located outside the liquid crystal panel assembly 300.

In addition, a signal transmission line 561 is disposed on the flexible printed circuit film (FPC) 560 attached between the printed circuit board 550 and the lower panel 100 of the liquid crystal panel assembly 300. The power transmission line 562 extends.

A plurality of data driver ICs 511-518 constituting the data driver 500 are mounted on the lower panel 100 in a COG manner, and a part 511-514 is disposed on the left side of the flexible printed circuit film 560. The remaining 515-518 are arranged to be symmetrical with each other on the right side. In addition, the data lines DL are connected to each of the driving ICs 511 to 518 over the display area DA and the peripheral area PA thereof.

The signal transmission line 561 is connected to two driving ICs 514 and 515 to form a signal line SL between each driving IC 511 to 518, and the voltage transmission line 562 is also connected to the two driving ICs 514 and 515. It is connected to form a power supply line (PL) between each driving IC (511-518).

At this time, for example, the power lines PL1 to PL4 between the two driving ICs 516 and 517 located on the right side are arranged in order from top to bottom with a constant width and spacing.

The first and third power lines PL1 and PL3 are formed on the insulating substrate 110 such as glass at regular intervals from each other, and the first insulating layer 140 is formed thereon.

The second and fourth power lines PL2 and PL4 are formed at regular intervals on the insulating layer 140, and the second insulating layer 180 is formed thereon.

In this case, the first and third power lines PL1 and PL3 are formed of the same layer as the gate lines G ₁ -G _n , and the second and fourth power lines PL2 and PL4 are the data lines DL. It is formed of the same layer as.

Here, the first to fourth power lines PL1 to PL4 may be formed of an upper layer formed of a low resistivity metal such as an aluminum-based metal, a silver-based metal, or a copper-based metal to reduce signal delay or voltage drop. (PL1q, PL2q, PL3q, PL4q) and a material having excellent contact properties between indium tin oxide (ITO) and indium zinc oxide (IZO), for example, an underlayer (PL1p, made of chromium, molybdenum, titanium, tantalum or an alloy thereof) PL2p, PL3p, PL4p).

At this time, as shown in FIG. 6A, the width W1 of the first power supply line PL1 and the third power supply line PL3 and the interval W2 therebetween are maintained at about 1: 1, and also shown in FIG. 6B. The width W3 of the second power line PL2 and the fourth power line PL4 and the distance W4 therebetween are also maintained at about 1: 1.

As a result, the resistance present in the power lines PL1-PL4 can be reduced by half.

In more detail, the lower layers PL1p, PL2p, PL3p, and PL4p of the power lines PL1-PL4 may not be fully etched by the current technology, and may short-circuit with neighboring wirings. To prevent this, by designing a space between the wirings by the width of the wiring so that the ratio is 1: 1. However, in the related art, since all the power lines are formed on the same layer, the width of the wiring has to be narrowed to secure the wiring gap, and the resistance of the wiring increases by the width of the narrowed wiring.

However, according to the embodiment of the present invention, since the adjacent wirings are located on different layers, the widths W1 and W3 of the wirings located on the same layer can be increased, thereby reducing the resistance of the wiring by the increased width. . For example, if the same area can double the width of the wiring, the resistance is cut in half.

As such, when the neighboring wirings are formed on different layers, the width of the wirings located on the same layer can be doubled and the resistance can be reduced by half.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

Claims (6)

A display panel unit having a gate line and a data line, A plurality of data driving ICs connected to the data lines, and A plurality of power lines connected between the data driving ICs Including, The power line is formed in the same process as the gate line and the data line, Adjacent power lines among the power lines are arranged on different layers. Display device. In claim 1, A part of the power line is formed on the same layer as the gate line, and the other part is formed on the same layer as the data line. In claim 2, The display device of claim 1, wherein a distance between power lines disposed on the same layer among the power lines is substantially the same as the width of the power lines. In claim 3, And the data driver IC is mounted on the display panel. In claim 1, Insulation board, First and second power lines formed on the insulating substrate, A first insulating film formed on the first and second power lines, Third and fourth power lines formed on the first insulating film, and A second insulating film formed on the third and fourth power lines Display device comprising a. In claim 5, The widths of the first to fourth power lines are the same, An interval between the first power line and the second power line or an interval between the third power line and the fourth power line is equal to the width of the first to fourth power lines. Display device.

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