KR20070094234A - Method for designing reticle - Google Patents

Abstract

A method for designing a reticle is provided to increase or maximize productivity by reducing a time for identifying omission of an alignment key, an overlay key, and a test pattern. A main chip region is set on a reticle(S100). A plurality of alignment keys, a plurality of overlay keys, and a plurality of test patterns are indexed by using proper names in order to arrange images of the alignment keys, the overlay keys, and the test patterns in a scribe line region(S200). A scribe line pattern region is formed(S300). The alignment keys, the overlay keys, and the test patterns are arranged in a scribe line pattern region(S400). A cutting region is arranged in the scribe line pattern region(S500). A design is identified by using proper names corresponding to the alignment keys, the overlay keys, and the test patterns which are arranged in the scribe line pattern region(S600).

Description

Method for designing reticle}

1 is a flow chart showing a method of designing a reticle according to an embodiment of the present invention.

2 is a plan view illustrating the main chip pattern region and a scribe line;

Explanation of symbols on the main parts of the drawings

100: main chip pattern area 200: scribe line pattern area

The present invention relates to a method of designing a reticle, and more particularly, a plurality of alignment keys, overlay keys, and test patterns, which are arranged in a scribe area at an edge of a main chip area of the reticle, are indexed to a unique name, respectively. The present invention relates to a reticle design method that can increase or maximize productivity since it is possible to prevent missing alignment keys, overlay keys, and test patterns, and to shorten the design time of the reticle.

In recent years, with the rapid spread of information media such as computers, semiconductor devices are also rapidly developing. In terms of its function, the semiconductor device is required to operate at a high speed and to have a large storage capacity. In response to these demands, manufacturing techniques have been developed for semiconductor devices to improve the degree of integration, reliability, response speed, and the like.

As a result, each unit process that can guarantee a high production yield is being developed as part of the competitiveness of the semiconductor industry, and at the same time, various methods for reducing process errors in each unit process are continuously being researched and developed. The most restrictive unit process for increasing the integration of semiconductor devices is a photo-lithographic process. For example, a semiconductor device is formed of a plurality of insulating layers and conductive layers formed on a wafer, and their patterns are formed by exposure, development and etching according to a mask pattern such as a photoresist pattern. Therefore, in order to form the layer of the photoresist desired pattern, only the layer to be etched in the exposure process should be exposed to the light source. The light source generally includes ultraviolet light or X-ray light having a single wavelength, and the ultraviolet light or X-ray light incident on the light source may be shielded by an image pattern formed on the reticle to selectively expose the photoresist.

According to the trend toward higher integration of semiconductor devices, the number of image patterns designed on the reticle becomes smaller, and the number of the image patterns increases, which is required for a large amount of time to manufacture the reticle. The reticle includes an image including at least one main chip pattern region and a scribe line pattern region surrounding the main chip pattern region. Therefore, in order to shorten the time it takes to design a chip on a reticle, the main chip area and the data structure of the scribe line pattern area surrounding the main chip area are separately designed. Here, the main chip pattern region is an operation core region of the semiconductor device, and when the semiconductor manufacturing process is completed, the main chip pattern region may be individually cut and then packaged or packaged and distributed separately as individual devices. In this case, the main chip pattern area is determined in different types of formats according to sizes or product specifications to be designed therein.

In addition, in the scribe line pattern region, an alignment key for aligning the main chip pattern region and an overlay key are formed between the plurality of thin films stacked in the main chip pattern region in order to increase a process effect at a wafer level in a semiconductor manufacturing process. Can be. In addition, when the scribe line pattern region is completed at the wafer level, a test individual element such as a transistor formed in the main chip pattern region may be formed as a portion to be cut in chip units.

Referring to the reticle design method according to the prior art as follows.

First, the main chip pattern region is determined according to the specifications of the product selected for the semiconductor manufacturing process. For example, as a general semiconductor device formed in the main chip pattern region, a threshold value is determined according to a channel length constraint corresponding to the size of a gate electrode of the transistor as a transistor.

After the main chip pattern region is determined, a photo key including various types of alignment keys, overlay keys, and test patterns to be designed in the scribe line region around the main chip pattern region is received through a database of an interface. Create the screen of the interface. Here, the various kinds of the alignment key, the overlay key, and the test pattern may be individually imaged one by one corresponding to the main chip pattern, or may be grouped into an already set group and imaged to appear on the screen of the interface.

Next, in order to design the alignment key and the overlay key, a scribe line pattern region is generated as a screen of the interface along a circumference of the main chip pattern region.

Next, the alignment key and the overlay key are selected and arranged in the scribe line pattern area on the screen of the interface. In this case, a plurality of the alignment key, the overlay key, and the test pattern disposed in the scribe line pattern region may be arranged in a line along the pattern region of the scribe line formed in one direction.

The reticle design may be completed after setting a cutting region for opening a predetermined portion in the portion where the alignment key, the overlay key, and the test pattern are disposed and remain in the scribe line pattern region. . Here, the cutting region is a part designed to expose a predetermined pattern formed in a previous process of the semiconductor manufacturing process using the reticle as it is in the current process.

Finally, it is checked whether the alignment key, the overlay key, and the test pattern are normally disposed in the scribe line pattern area appearing on the screen of the interface. For example, the alignment key, the overlay key, and the test pattern disposed in the scribe line pattern area are checked.

Therefore, the reticle design method according to the prior art is to image and arrange the alignment key, the overlay key, and the test pattern disposed in the scribe line pattern region defining the main chip pattern region, and the said Images of the align key, overlay key, and test pattern can be verified to complete the reticle design and produce the reticle.

However, the reticle design method according to the prior art had the following problems.

In the reticle design method according to the related art, the alignment key, the overlay key, and the test pattern are generated as an image when the alignment key, the overlay key, and the test pattern are output from the interface database. It is not easy to check that the alignment key, the overlay key, and the test pattern are missing in the design verification operation for confirming this as it is arranged. there was.

An object of the present invention for solving the above problems, the alignment key, overlay key, which is disposed in the scribe line pattern area, and the alignment key, overlay key during the design verification performed to confirm the placement of the test pattern The present invention provides a method of designing a reticle that can easily identify missing and test patterns, and shorten the verification time required to confirm the test pattern, thereby increasing or maximizing productivity.

According to an aspect of the present invention, there is provided a method of designing a reticle, including: setting a main chip region to be indexed to the reticle; The plurality of alignment keys, overlay keys, and test patterns, which are disposed in the scribe line area outside the main chip region, are indexed with respective unique names, and the images of the plurality of alignment keys, overlay keys, and test patterns are scribed. Placing in an area; And confirming each unique name corresponding to the alignment key, overlay key, and test pattern when the alignment key, overlay key, and test pattern is arranged in the scribe line area. Determining whether the corresponding alignment key, overlay key, and test pattern are missing or added.

Hereinafter, a reticle design method according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings. However, embodiments of the present invention may be modified in many different forms, and the scope of the present invention should not be construed as being limited by the embodiments described below. Embodiments of the present invention are provided to more completely explain the present invention to those skilled in the art. Accordingly, the shape and the like of the elements in the drawings are exaggerated to emphasize a more clear description, and the elements denoted by the same reference numerals in the drawings means the same elements. In the following description of the present invention, if it is determined that a detailed description of a related known function or configuration may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted.

1 is a flowchart illustrating a method of designing a reticle according to an exemplary embodiment of the present invention.

As shown in FIG. 1, in the method of designing a reticle according to the present invention, first, a main chip pattern region 100 is determined according to a specification of a product selected for a semiconductor manufacturing process (S100). Here, the main chip pattern region 100 is a region in which wirings connecting the active semiconductor elements and the active semiconductor elements are wired corresponding to the active regions of the wafer. For example, a typical active semiconductor device formed in the main chip pattern region 100 is a transistor, and a threshold value is determined according to a channel length constraint corresponding to the size of a gate electrode of the transistor. Therefore, the main chip pattern region 100 is manufactured by a maker and commercially distributed so that the active semiconductor devices are arranged according to a predetermined size.

In addition, when the main chip pattern region 100 is determined, various types of alignment keys, overlay keys, and test patterns to be designed in the scribe line region around the main chip pattern region 100 through a database of an interface are included. After receiving the photo key to be assigned to a predetermined predetermined unique name and generates it as a screen of the interface (S200). Here, the various types of the alignment key, the overlay key, and the test pattern are not imaged, but are created to have unique names by being designated for each function and use. For example, the initial letter of the alignment key designates 'a', and mixes it with the number according to the size or shape so as to specify a unique name of the alignment key, and the initial letter of the overlay key is 'o'. To specify the unique name of the corresponding overlay key by mixing with numbers according to size or shape, and specifying the 't' as the initial of the test pattern, and mixing with numbers according to the size or shape of the test pattern. You can specify a unique name. In this case, a plurality of the alignment key, the overlay key, and the test pattern may be mixed with each other or each may be designated as one unique name in a group. In addition, when the corresponding unique name is selected on the screen of the interface, an image of the alignment key, the overlay key, or the test pattern corresponding to the unique name may appear on one side of the screen.

Next, a scribe is performed along the circumference of the main chip pattern region 100 so that the alignment key, the overlay key, and the test pattern having a predetermined function and size are designed to correspond to the main chip pattern region 100. A line pattern area 200 is generated as a screen of the interface (S300).

2 is a plan view illustrating a main chip pattern region 100 and a scribe line, in which nine main chip pattern regions 100 are defined in a scribe line pattern region 200 defining the main chip pattern region 100. Is defined by. Here, the scribe line pattern region 200 is reduced in the screen of the interface. In addition, the scribe line pattern area 200 may be enlarged and displayed on the screen of the interface.

Next, the alignment key, the overlay key, and the test pattern are selected and assigned to the scribe line pattern area 200 on the screen of the interface (S400). Here, a plurality of the alignment key, the overlay key, and the test pattern disposed in the scribe line pattern region 200 may be arranged in a line along the pattern region of the scribe line formed in one direction. For example, the align key is mainly designed in the scribe line pattern region 200 adjacent to an edge of the main chip pattern region 100, and the overlay keys are the same or similar in size to each other within a predetermined distance from the align key. A plurality of clusters are designed to have a scribe line pattern region 200. In addition, the test pattern is designed such that an active semiconductor device having the same or similar size as the active semiconductor device formed in the main chip pattern region 100 is formed in the scribe line pattern region 200.

Thereafter, the alignment key, the overlay key, and the test pattern, which are patterned by a previous semiconductor process in a portion where the alignment key, the overlay key, and the test pattern are disposed in the scribe line pattern region 200, are included. A cutting area for generally opening a predetermined portion including the photo key may be disposed and the reticle design may be completed (S500). Here, the cutting region is a part designed to expose a predetermined pattern formed in a previous process of the semiconductor manufacturing process using the reticle as it is in the current process. For example, when the alignment key and the overlay key are stacked too many times in the previous semiconductor manufacturing process, the cutting region may be difficult or unnecessary when no further semiconductor manufacturing process is performed in the current semiconductor manufacturing process and the subsequent semiconductor manufacturing process. This can be designed. In addition, when the test pattern is completed in the previous semiconductor manufacturing process and the patterning process to be stacked on the test pattern is not required in the current semiconductor manufacturing process and the subsequent semiconductor manufacturing process, fabrication by the previous semiconductor manufacturing process The part where the test pattern is formed is designed as the cutting area.

Finally, at least one of the alignment key, the overlay key, and the test pattern is normally disposed in the scribe line pattern area 200 appearing on the screen of the interface. Each unique name corresponding to the pattern may be confirmed (S600). Here, the scribe line pattern region 200 appearing on the interface screen has a plurality of square side shapes surrounding the circumferences of the plurality of main chip pattern regions 100 to define the plurality of main chip pattern regions 100. Is done. In addition, the align key, the overlay key, and the test pattern formed in the scribe line pattern region 200 having the plurality of rectangular side shapes are designed to be numerous. In this case, it is not easy to confirm that the alignment key, the overlay key, and the image of the test pattern are missing by using the screen of the interface. Accordingly, the alignment key, the overlay key, and the test pattern to be disposed in the scribe line pattern area 200 may be missing by identifying each unique name corresponding to the alignment key, the overlay key, and the test pattern. In addition, unnecessary alignment keys, overlay keys, and test patterns have been added to facilitate the design.

For example, in the case of a plurality of the alignment keys disposed in the scribe line pattern region 200, the alignment is performed at a portion where a letter or number following the initial character loses continuity based on the initial letter of the alignment key. You can easily check if a key is missing. In addition, it is possible to easily check whether the corresponding alignment key has been added in different parts of letters or numbers following the initial letter of the alignment key. Similarly, a plurality of overlay keys or test patterns disposed in the scribe line pattern area 200 may also be overlaid in a portion where a subsequent character or number based on an initial character has lost continuity, as in the case of the align key. Alternatively, it may be easy to check whether the test pattern is missing, and it may be easy to check whether the corresponding overlay key or the test pattern is added at different portions of letters or numbers which are based on the initial letter.

Therefore, the reticle design method according to the present invention is generated so that the alignment key, overlay key, and test pattern has a unique name when generating the alignment key, overlay key, and test pattern output from the interface database, , A unique name corresponding to the alignment key, the overlay key, and the test pattern may be apparent in a design verification operation for confirming that the alignment key, the overlay key, and the test pattern are disposed in the scribe line pattern area 200. This allows you to easily check that the alignment key, overlay key, and test pattern are missing or added during the design verification, and to shorten the verification time required to verify the design. Can be.

In addition, the description of the above embodiment is merely given by way of example with reference to the drawings in order to provide a more thorough understanding of the present invention, it should not be construed as limiting the present invention. In addition, various changes and modifications can be made by those skilled in the art without departing from the basic principles of the present invention. For example, the scribe line pattern region 200 may be represented as a peripheral pattern region formed along the circumference of the main chip pattern region 100.

As described above, according to the present invention, the alignment key, the overlay key, and the test pattern are generated to have unique names when generating the alignment key, the overlay key, and the test pattern output from the interface database. In the design verification operation for confirming that the alignment key, the overlay key, and the test pattern are disposed in the scribe line pattern area, each unique name corresponding to the alignment key, the overlay key, and the test pattern is arranged in a clear manner. It is possible to easily confirm that the alignment key, overlay key, and test pattern are missing or added during the verification operation, and to shorten the verification time required to confirm this, thereby increasing or maximizing productivity. .

Claims (1)

Setting a main chip area to be indexed in the reticle; The plurality of alignment keys, overlay keys, and test patterns, which are disposed in the scribe line area outside the main chip region, are indexed with respective unique names, and the images of the plurality of alignment keys, overlay keys, and test patterns are scribed. Placing in an area; And Upon identification of the alignment key, overlay key, and test pattern disposed in the scribe line area, a corresponding unique name corresponding to the alignment key, overlay key, and test pattern should be identified and placed in the scribe line area. Determining whether the alignment key, overlay key, and test pattern are missing or added.

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