JPS6223862B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an improvement in a master mask manufacturing method.

In reticles for semiconductor chips with high element integration such as large integrated circuits, element patterns and wiring patterns are arranged in a high density within the chip.
It is difficult to insert the chip name pattern within the pattern forming area of the chip.

For this reason, conventional master masks for large integrated circuits, etc., use a reticle that does not have a chip name pattern to form a chip pattern on the mask substrate, and at that time, a separate exposure is performed to form a mask name pattern corresponding to the chip name. It was manufactured using a method.

However, in this conventional method, if there is a change in a part of the mask pattern, or if the same mask layer (as in the master slicing method) etc.), when there are many different types of mask patterns, it is easy to produce a mask with a mask name pattern different from the chip pattern formed, and it is easy to make a mistake in manufacturing a mask with a different mask name pattern than the formed chip pattern. Since chip patterns tend to be very similar, it is difficult to detect mistakes. Therefore, master masks with different chip pattern types and mask names are shipped, and the master masks are based on the incorrect mask name. There has been a problem in that when used, it causes great damage in the manufacture of semiconductor devices such as integrated circuits.

In view of the above problems, the present invention provides a method for manufacturing a master mask that can prevent a master mask having a mask name different from the type of chip pattern from being shipped.

That is, the present invention, in manufacturing a master mask,
A chip name pattern is provided on one side of the scribe line surrounding the chip area of the rectangular chip pattern in the reticle, and a dummy area pattern is provided on the side opposite to the scribe line, and the chip pattern is repeatedly exposed on the mask substrate using the reticle. A process of forming a plurality of chip patterns in which the scribe line regions of adjacent chip patterns overlap, and a process of forming a chip name pattern formed on the scribe line in the formation of the chip patterns and a mask name pattern separately formed on the mask substrate. It is characterized by having a step of collating.

The present invention will be explained in detail below with reference to an illustrated example of manufacturing a master mask for forming a wiring pattern.

FIG. 1 is a first reticle surface diagram of the above embodiment of the present invention, FIG. 2 is a second reticle surface diagram, and FIG. 3 is a partial surface diagram of a master mask.

That is, in the method of the present invention, a reticle dry plate is first exposed to light using information from a magnetic tape using a pattern generator, and developed to form a chip area 2 excluding a wiring pattern area 1 as shown in FIG.
A chip name pattern 4 within one side of the scribe line 3, and a dummy area 5 at a location corresponding to the chip name pattern 4 on the scribe line that faces the scribe line having the chip name pattern 4 across the chip area 2; A primary reticle 7 having a light shielding layer is formed in the outer peripheral region 6 of the scribe line 3.

Next, using a contact printer,
The pattern of the next reticle 7 is transferred to a blank plate coated with positive resist, developed and etched to form a pattern that is left and right opposite to that of the first reticle, as shown in FIG. A secondary reticle made of a hard mask with a long service life, which has a light-shielding layer in the chip area 2 excluding the wiring pattern area 1, the chip name pattern 4 in the scribe line 3, the dummy area 5, and the outer peripheral area 6 of the scribe line 3. Form 8.

Next, a negative resist is applied and a mask symbol pattern having a visible size corresponding to the chip pattern to be formed on the peripheral edge thereof is exposed in advance on a master mask blank plate.
Step and... using the secondary reticle.
The chip pattern is exposed using the repeat method.
After developing and etching, a light-shielding pattern is formed in the light-transmitting chip area 2' partitioned by the scribe line 3' made of the light-shielding layer in a pattern opposite to that of the secondary reticle, as shown in Fig. 3. A plurality of chip patterns each having a layered wiring pattern 1' and a light-transmitting chip name pattern 4' are formed in alignment on one side of the scribe line 3' made of the light-shielding layer, and a light-shielding layer is formed at the periphery of the mask. A master mask 10 made of a hard mask having a mask name pattern 9 having a visually visible size is formed.

Thereafter, the chip name pattern 4' of the master mask 10 is compared with the mask name pattern 9, and it is confirmed that they match, and the manufacture of the master mask is completed.

However, since the method according to the present invention forms the chip name pattern within the scribe line as described above, the degree of integration of elements formed on the chip is not reduced.

As explained above, in the master mask formed by the method of the present invention, the chip name specified in the scribe line is compared with the mask name formed on the periphery of the master mask, and the formed chip pattern is Since the mask name and mask name exactly match, it has the effect of preventing damage to the manufacturing of semiconductor devices such as integrated circuits due to incorrect display of the mask name.

[Brief explanation of the drawing]

FIG. 1 is a first reticle surface diagram in one embodiment of the present invention when manufacturing a master mask for wiring patterns, FIG. 2 is a second reticle surface diagram, and FIG. 3 is a partial surface diagram of the master mask. It is. In the figure, 1 and 1' are wiring pattern areas;
2 and 2' are chip areas, 3 and 3' are scribe lines, 4 and 4' are chip name patterns, 5 is a dummy area, 6 is an outer peripheral area, 7 is a primary reticle, 8 is a secondary reticle, 9 is the chip name pattern, and 10 is the master mask.

Claims (1)

[Claims] 1. In manufacturing a master mask, a chip name pattern is provided on one side of a scribe line surrounding a chip area of a rectangular chip pattern in a reticle, a dummy area pattern is provided on the opposite side to the scribe line, and a reticle is manufactured. A process of repeatedly exposing a chip pattern on a mask substrate using a method to form a plurality of chip patterns in which the scribe line areas of adjacent chip patterns overlap, and a process of forming a chip name pattern on the scribe line by forming the chip pattern. A photomask manufacturing method comprising the step of comparing the mask name pattern with a mask name pattern separately formed on the mask substrate.