KR20070061264A - Triple well p-type low voltage triggered esd protection device - Google Patents

Abstract

A triple well p-type low voltage triggered ESD protection device is provided to perform an operation at a low trigger voltage, to minimize parasitic capacitance, and to obtain a fast response speed to an ESD pulse. A deep n-type well(30) is formed on a p-type substrate(20). An n-type well(40) and a p-type well(50) are formed within the deep n-type well. A bias applying region is formed to apply directly a bias voltage to the p-type well. The bias applying region is formed with a p+ diffusion region(80) which is formed at a junction side of the n-type well and the p-type well.

Description

Triple Well P-type Low Voltage Triggered ESD Protection Device

1 is a cross-sectional view showing an ESD protection device of the SCR structure having a low trigger voltage using a triple-well process according to an embodiment of the present invention.

2 is a cross-sectional view showing the structure of an ESD protection device composed of a horizontal pnp and a horizontal npn transistor according to the prior art.

Figure 3 is a cross-sectional view showing the structure of a low voltage triggered SCR (LVTSCR) according to the prior art.

Figure 4 is a graph showing the SCR characteristic curve according to the change of the anode voltage in the ESD protection device.

5 is a simplified circuit diagram of an SCR having two terminals.

* Explanation of symbols for the main parts of the drawings

20 p-substrate 30 deep n-well

40: n-well 50: p-well

60: p + diffusion region 70: n + diffusion region

80: p + diffusion region for RC networks

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an ESD protection device for protecting an internal circuit from an impact such as external static electricity in the semiconductor device technology. In particular, the present invention addresses disadvantages of conventional SCR and low voltage triggered SCR (LVTSCR) used in existing ESD protection circuits. An improved ESD protection device having a new triple-well structure is disclosed.

Electro-static discharge (ESD), which causes the instantaneous discharge of static electricity generated during the production or use of electronic components and products, results in the destruction of internal circuits and metal wiring in integrated circuits. It is targeted.

In particular, as the semiconductor manufacturing process technology has evolved from DSM (Deep Sub-Micron) to VDSM (Very Deep Sub-Micron), the thickness of the gate oxide film is reduced to 0.1 μm or less, and as semiconductor chips become smaller, Device destruction is becoming more serious. Therefore, the development of a protection device that satisfies several ESD performance indicators, such as high discharge speed, transparency in normal operation, robustness of sufficient discharge current, and low trigger voltage effectiveness, and Circuit design is very important.

ESD protection device of SCR structure has larger ESD protection than general ggNMOS (gate grounded NMOS) or gcNMOS (gate coupled NMOS) protection device, and due to its small area, it minimizes the parasitic capacitance component of the protection circuit. It has the characteristics suitable for the semiconductor chip which is becoming high speed / miniaturization.

Conventional SCRs as shown in FIG. 2 have much greater ESD protection than other devices such as ggNMOS that are commonly used. By using such characteristics, the desired ESD protection can be obtained with a small area consumption, and parasitic capacitance components of the ESD protection circuit can be minimized, which is suitable for high frequency analog and RF circuits. However, the typical SCR shown in the drawing has a very high trigger voltage of about 30V, so that before the protection device is operated, the internal line may be damaged as the gate oxide of the MOSFET in the semiconductor chip core circuit breaks or an ESD current is introduced. There was a risk of deterioration and damage.

The LVTSCR according to another prior art as shown in FIG. 3 has a structure utilizing the advantages of conventional SCR and ggNMOS, and has a structure in n + and p-type substrates that span the junction between n-well and p-type substrates. It triggers by the breakdown voltage of. In other words, the ggNMOS is formed in the SCR structure, and the base width of the lateral npn transistor is minimized to the channel width by using the ggNMOS structure, thereby increasing the current gain to have a low trigger voltage. . In addition, the base width of the horizontal pnp transistor of the SCR is also minimized to implement a protection device having a trigger voltage of about 6V. Recently, with the development of VDSM process technology, product development and commercialization of I / O interface circuits and semiconductor chips with a low power supply voltage of about 1.5V are actively progressed. LVTSCR is applied to these VDSM-class high-speed / low-voltage circuits. The trigger voltage is still high to apply.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object thereof is to provide an ESD protection device applicable to a semiconductor chip having high speed / low voltage characteristics.

Another object of the present invention is to provide an ESD protection device capable of minimizing parasitic capacitance while operating at a low trigger voltage.

Another object of the present invention is to provide an ESD protection device having a fast response speed against an ESD pulse.

In order to achieve the above object, the present invention proposes a novel triple-well low voltage trigger ESD protection device for ESD protection using a deep well process, one of advanced CMOS process technology.

Innovative technologies are being developed as the CMOS process technology is advanced to the VDSM level, and the present invention uses a triple well process technology. This can be achieved by adding additional deep n-well processes rather than simply n-well and p-well processes on the p-substrate, and this process support is of much use in circuit implementation. And scalability.

The triple-well low voltage trigger ESD protection device of the present invention for achieving the above object comprises a deep n-type well formed on a p-type substrate; N-well and p-well formed in contact with each other in the deep n-well; And a bias application region for directly applying a bias voltage to the p-well.

In the present invention, it is designed based on the VSDM process by improving the high trigger voltage, which is a disadvantage of the ESD protection device of the conventional SCR structure, and by connecting the RC-network to the designed device to have a faster response time of the protection circuit when the ESD pulse is applied. This study is to implement an ESD protection device that can be easily applied to integrated circuits of high speed / low voltage characteristics. In particular, the triple-well structure is formed by using a deep well process, which is one of advanced CMOS process technologies, and is designed to directly apply a bias to a p-well region where an SCR trigger is performed. ESD protection device according to the above idea has a very low trigger voltage compared to the conventional ones.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.

(Example 1)

In this embodiment, the main technical aspects proposed to implement a novel three-well low voltage trigger ESD protection device is as follows. First, we present the implementation method of SCR for improved ESD protection of CMOS chip in VDSM process. Second, we use deep well formation technology to form triple-well structure. The present invention provides a technique for effectively forming an ESD protection device by forming a p + having a high doping concentration at an n-well and a p-well junction for inducing a trigger and connecting an RC-network.

In order to explain the ESD protection principle of the ESD protection element of this embodiment, first, the ESD protection principle of the SCR element will be described.

Since the existing SCR structure has a property of changing from a high impedance state to a low impedance state, it is possible to construct an ESD protection circuit that is very efficient compared to the area of the protection element. 2 shows an SCR structure consisting of a simple horizontal pnp and a horizontal NPN transistor, wherein the P + diffusion region of the SCR in the n-well region is connected to the anode end, and the n + diffusion region in the p-well region is the cathode of the SCR. Connect to the stage. In the ESD protection device, the SCR characteristic curve according to the change of the anode voltage is shown in FIG. 4 and the operation principle is as follows.

When the anode voltage is greater than the trigger voltage, the emitter-base junction of the pnp transistor is forward biased and the pnp transistor is turned on. The current flowing through the pnp transistor flows into the p-well, which causes the npn transistor to turn on. The current of the npn transistor flowing from the n-well to the cathode places a forward bias on the pnp transistor, which no longer biases the pnp transistor, reducing the anode voltage to its minimum value. This is called holding voltage. Thereafter, the SCR performs a positive feedback operation to effectively discharge the ESD current through the anode stage.

Be SCR is simplified by the circuit of Figure 5 with the two terminals, and Rn-type-wells (R _nwell) and Rp-type-wells (R _pwell) is n-type - The resistance of the well, all of which are-well and p-type Provide bias to the pnp and npn transistors, respectively. In order to maintain state when the SCR is in latch mode, the condition as shown in Equation (1) must be satisfied.

β _npn ㆍ β _pnp ≥ 1

Here, β _npn and β _pnp are current gains of the npn and pnp transistors.

When the SCR structure is used as an ESD protection circuit, an avalanche breakdown at the junction between the n-well and p-well is required for the protection device to trigger. In the VDSM Advanced CMOS process, the avalanche breakdown voltage between n-well and p-substrate is very high, about 20V or higher, so the trigger voltage must be lowered to form an ESD protection circuit using SCR.

In this embodiment, a new ESD protection device of SCR structure with low trigger voltage is fabricated using a triple-well process.

The ESD protection element of this embodiment as shown in FIG. 1 includes a deep n-type well 30 formed on a p-type substrate 20; An n-type well and a p-type well formed in contact with each other in the deep n-type well 30; A p + diffusion region 60 formed in the n-type well 40 and forming an anode; An n + diffusion region 70 formed inside the p-well 50 and forming a cathode; And a p + diffusion region 80 for the RC network formed at the junction of the n-well 40 and the p-well 50.

The ESD protection device of the proposed structure forms a twin well of the p-well 50 and the n-well 40 after the deep n-well 30 process on the p-type substrate 20, and the n-type- High concentration implanted p + diffusion regions 80 were formed at the junction of well 40 and p-well 50 to induce a lower trigger voltage by applying a bias directly to p-well 50. . In this case, p + (60) on the n-well 40 side is connected to the I / O pad as the anode of the SCR, and n + on the p-well 50 side is connected to the ground terminal as the cathode end to the ESD discharge path. Will be provided.

Here, a p + region 80 is formed between the n-well 40 and the p-well 50 at a high doping concentration and is directly biased by an RC-network connected to this region when an ESD pulse is input. By applying, induces a forward bias at the junction between the n-well 40 and the p-well 50 so that the ESD current flowing through the anode end can be easily discharged to the cathode end. do. At the same time, the current flowing through p + 80 increases the potential of p-well 50 and causes the horizontal npn transistor to turn on. The potential of the n-well 40 is lowered by the turned-on npn transistor, so that the horizontal pnp transistor is turned on, so that the SCR effectively discharges the ESD current by performing a positive feedback operation.

Due to the structure of the deep n-type well 30, it is possible to directly apply a bias to the p-type well region 50 that determines the trigger voltage of the SCR, so that the protection device may operate at a lower voltage than the conventional SCR. . In addition, a high concentration of p + (80) is injected into the junction between the n-well 40 and the p-well 50, and an RC network is connected to the region to positively form the p-well 50. Applying a positive bias induces a low trigger voltage and allows the protection device to respond quickly to ESD pulses. Therefore, the ESD protection circuit fabricated through this is applied to VDSM class semiconductor chip with high speed / low voltage characteristics to improve its safety and reliability.

In another embodiment, an ESD protection device includes a deep p-well formed on an n-type substrate; N-well and p-well formed in contact with each other inside the deep p-well; A p + diffusion region formed inside said n-well; An n + diffusion region formed inside the p-well; And a p + diffusion region (bias application region) for the RC network formed on the junction of the n-well and p-well to directly apply a bias voltage to the n-well.

Since the ESD protection element of the present embodiment has a symmetrical structure in which the p-type region and the n-type region of the ESD protection element of the first embodiment are reversed, the ESD protection element has an operating characteristic that is symmetrical to that of the first embodiment with respect to the ground voltage. For example, it is advantageous to apply to a semiconductor chip operating by receiving a negative power supply voltage with respect to a ground voltage as a reference.

In the ESD protection device of this embodiment, the p + diffusion region is connected to the ground voltage of the semiconductor chip, and the n + diffusion region is connected to the I / O pad of the semiconductor chip, and is applied to the negative I / O pad. ESD pulses having a high voltage are blocked from entering the semiconductor chip. The p + diffusion region for the RC network for directly applying a bias to the SCR is also formed as an n + diffusion region, and the bias voltage applied thereto has the opposite sign (+,-) as in the case of the first embodiment.

Details except for the above are substantially the same as those of the first embodiment, and thus description thereof is omitted.

Although the preferred embodiments of the present invention have been described above, the present invention is not limited thereto, and various modifications and changes can be made within the scope of the claims and the detailed description of the invention and the accompanying drawings. Naturally, it belongs to the scope of the invention.

By implementing the triple-well low voltage trigger ESD protection device of the present invention, the ESD protection device can be efficiently applied to a semiconductor chip having high speed / low voltage characteristics.

The triple-well low voltage trigger ESD protection device of the present invention operates at a low trigger voltage and has the effect of minimizing parasitic capacitance, and / or having a fast response time to an ESD pulse.

In addition, the high-speed / low-voltage ESD protection device of the present invention can be applied to almost all nano-device-based I / O interface circuits and integrated circuit semiconductors, so the field of application is very wide, in the case of a semiconductor chip embedded therein high safety and reliability It can bring about the effect of the cost reduction and the effect of the one chip.

As semiconductor process technology is rapidly developed to VDSM level, the thickness of gate oxide of MOSFET is getting thinner, and the device destruction of semiconductor chip due to ESD phenomenon is intensifying.These ESD pulses are very high at several kV and several A. Because of the electrical characteristics of the voltage / current, the destruction caused by the deterioration of the internal circuit lines of the chip can not be ignored. Therefore, the importance of the technology for the effective ESD protection device that can be applied to such VDSM-class semiconductor chip is emerging. The SCR protection device of the new structure proposed in the present invention can be said to greatly improve that the SCR protection device is not applicable to a VDSM class integrated circuit due to its high trigger voltage even though the existing SCR has a large ESD protection capability.

Claims (8)

a deep n-well formed on a p-substrate; N-well and p-well formed in contact with each other inside the deep n-well; And A bias application region for directly applying a bias voltage to the p-well ESD protection device comprising a. The method of claim 1, And the bias application region is a p + diffusion region formed at a junction surface of the n-well and p-well. The method according to claim 1 or 2, A p + diffusion region formed inside said n-well; And N + diffusion region formed inside the p-well ESD protection device further comprising. The method of claim 3, The p + diffusion region is connected to an I / O pad, The n + diffusion region is connected to the ground terminal, And a bias voltage of an external RC network is applied to the bias application region. a deep p-well formed on the n-type substrate; N-well and p-well formed in contact with each other inside the deep p-well; A bias application region for directly applying a bias voltage to the n-well ESD protection device comprising a. The method of claim 5, And the bias application region is an n + diffusion region formed at a junction surface of the n-well and p-well. The method according to claim 5 or 6, A p + diffusion region formed inside said n-well; And N + diffusion region formed inside the p-well ESD protection device further comprising. The method of claim 7, wherein The n + diffusion region is connected to an I / O pad, The p + diffusion region is connected to the ground terminal, And an bias voltage of an external RC network is applied to the bias application region.

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