KR20070028978A - Liquid crystal display and driving method thereof - Google Patents

Abstract

A liquid crystal display device and a driving method thereof are provided to reduce a noise while driving adjacent gate lines by preventing the gate lines from being simultaneously driven by a gate-on voltage. A liquid crystal display device includes plural gate lines, plural data lines, pixel arrays, a first gate driving circuit(810L), and a second gate driving circuit(810R). The pixel arrays are arranged on the intersections between the gate and data lines. The first gate driving circuit is connected to one group of the gate lines and drives the gate lines. The second gate driving circuit is connected to the other group of the gate lines and drives the gate lines. The first and second gate driving circuits drive the gate lines, so that one of the one group of gate lines is overlapped with one of the other group of gate lines for a predetermined time interval, while adjacent gate lines are not overlapped with each other.

Description

Liquid crystal display and its driving method {LIQUID CRYSTAL DISPLAY AND DRIVING METHOD THEREOF}

1 is a block diagram of a liquid crystal display according to an embodiment of the present invention;

2 is an equivalent circuit diagram of two pixels of a liquid crystal display according to an exemplary embodiment of the present invention;

3 illustrates an example of the gate driving circuits illustrated in FIG. 1;

4 shows a specific configuration of a shift register;

5 is a timing diagram of signals used in the operation of the shift register shown in FIG. 4;

6 is a timing diagram showing that gate lines are driven by the operation of the gate driving circuits shown in FIG. 3;

7 illustratively shows that two adjacent gate lines are driven with a gate on voltage;

8 shows gate driving circuits according to an embodiment of the present invention;

9 is a timing diagram of signals by the operation of the gate driving circuits shown in FIG. 8; And

FIG. 10 is a view illustrating a change in pixel voltage when gate lines are driven by the gate driving circuits shown in FIG. 8.

The present invention relates to a liquid crystal display (LCD).

A general liquid crystal display device includes two display panels and a liquid crystal layer having dielectric anisotropy interposed therebetween. An electric field is applied to the liquid crystal layer, and the intensity of the electric field is adjusted to adjust the transmittance of light passing through the liquid crystal layer to obtain a desired image. Such liquid crystal displays are typical among portable flat panel displays (FPDs) that are easy to carry. Among them, TFT-LCDs using thin film transistors (TFTs) as switching elements are mainly used.

The TFT_LCDs are arranged in a matrix and include a plurality of pixel arrays including switching elements. Each pixel selectively receives a data voltage corresponding to an image signal through a switching element. The TFT-LCD also includes a gate driving circuit for applying a gate-on voltage to the gate line, a data driving circuit for applying an image signal to the data line, and a signal control circuit for controlling them. The gate driving circuit starts outputting the gate on voltage from the signal control circuit according to the vertical synchronization start signal, and sequentially applies the gate on voltage to the gate lines arranged in a line.

On the other hand, amorphous or polycrystalline silicon is used as the material of the TFT in such a TFT-LCD. Polysilicon TFT-LCDs have high electron mobility and can easily integrate driving circuits on glass substrates, while amorphous silicon (a-Si) TFT-LCDs have low liquidity due to their low electron mobility. The display panel assembly includes only pixels, and the driving circuit is manufactured as a separate integrated circuit (IC) and mounted on a glass substrate.

For example, if you want to implement XGA resolution, you need to drive 1024 * 3 * 768 subpixels, so use 8 384 channel data ICs and 3 256 channel gate driver ICs or 384 channel data. Four driver ICs and six 256-channel gate driver ICs are available. Here, in the latter case, since the pitch of the gate line is about three times the pitch of the data line, gate driving ICs constituting the gate driving circuit cannot be mounted on one side of the pixel array, so that driving ICs are provided on both sides of the pixel array. A dual bank structure that is divided and arranged is proposed.

In this case, the dual bank driving method needs to double the number of gate lines compared to the single bank driving method, and the shift speed of the shift register constituting the gate driving circuit must be doubled.

Accordingly, an object of the present invention is to provide a liquid crystal display including a gate driving circuit having an improved operation speed in a dual bank structure.

According to a feature of the present invention for achieving the above object, a liquid crystal display device is formed in a region where a plurality of gate lines, a plurality of data lines, and the gate line and the data line intersect; A pixel array connected to the gate line and the data line, a first gate driving circuit connected to a group of the gate lines, a first gate driving circuit driving the group of gate lines, and another group of the gate lines, A second gate driving circuit driving the other gate lines, wherein the first and second gate driving circuits overlap one of the group of gate lines with one of the other gate lines for a predetermined time; Drive the gate lines so that adjacent gate lines do not overlap to drive the gate lines The drives.

In this embodiment, the first gate driving circuit includes a plurality of first gate driving units respectively connected to the group of gate lines, and the second gate driving circuit is connected to the other group of gate lines. Each of the plurality of second gate driving units is connected.

In this embodiment, the group of gate lines and the other group of gate lines are alternately arranged one by one.

In this embodiment, the first gate driving circuit drives the group of gate lines in synchronization with a first vertical synchronizing start signal, and the second gate driving circuit synchronizes the gate of the other group in synchronism with a second vertical synchronizing signal. Drive the lines.

In this embodiment, the first vertical synchronization start signal is provided to a first first gate driving unit of the plurality of first gate driving units, and the second vertical synchronization start signal is the plurality of second gates. It is provided as the last second gate driving unit of the driving units.

In this embodiment, each of the plurality of gate lines is driven with a gate on voltage for 1H.

In this embodiment, the first vertical synchronizing signal and the second vertical synchronizing signal have a phase difference by 1 / 2H.

According to another aspect of the present invention, a liquid crystal display device includes: a plurality of gate lines, a plurality of data lines, and an area where the gate line and the data line cross each other, and are connected to the gate line and the data line, respectively. A pixel array, a first gate driving circuit sequentially driving odd-numbered gate lines of the gate lines in a first direction, and even-numbered gate lines of the gate lines in a second direction opposite to the first direction And a second gate driving circuit which drives sequentially.

The first gate driving circuit includes a plurality of first gate driving units respectively connected to the odd-numbered gate lines, and the second gate driving circuit includes a plurality of second gates respectively connected to the even-numbered gate lines. Gate drive units.

In this embodiment, the first gate driving circuit sequentially drives the odd-numbered gate lines in the first direction in synchronization with a first vertical synchronizing start signal, and the second gate driving circuit starts a second vertical synchronizing start. The even-numbered gate lines are sequentially driven in the second direction in synchronization with the signal.

According to another aspect of the present invention, a method of driving a liquid crystal display includes: sequentially driving a group of gate lines and sequentially driving another group of gate lines, wherein the group of gate lines and the other group include: Gate lines are alternately arranged one by one, and the gate lines are driven so that adjacent gate lines of the plurality of gate lines do not overlap.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram of a liquid crystal display according to an exemplary embodiment of the present invention, and FIG. 2 is an equivalent circuit diagram of two pixels of the liquid crystal display according to an exemplary embodiment of the present invention.

Referring to FIG. 1, the liquid crystal display device 100 according to an exemplary embodiment of the present invention includes a liquid crystal panel assembly 110 and gate driving circuits 150L and 150R, a data driving circuit 140, and a gray voltage generator connected thereto. 130 and the timing controller 120.

The liquid crystal panel assembly 110 may include a plurality of gate lines G1-G2n, a plurality of data lines D1-Dm, gate lines G1-G2n, and data lines D1-Dm in an equivalent circuit. Pixels Px formed in the intersection region of the < RTI ID = 0.0 >

Each pixel Px includes a switching element Q1 or Q2 connected to a corresponding gate line and a data line, a liquid crystal capacitor C _LC , and a storage capacitor C _ST connected thereto.

The switching elements Q1 and Q2 are provided on the lower panel 111, each gate terminal of which is connected to a corresponding gate line, each end of which is connected to a corresponding data line, and each other end of the switching element Q1 and Q2. It is connected to the liquid crystal capacitor C _LC .

The liquid crystal capacitor C _LC has two terminals, the pixel electrode 112 of the lower panel 111 and the common electrode 230 of the upper panel 113, and the liquid crystal layer between the two electrodes 112 and 114 is a dielectric material. Function. The pixel electrode 112 is connected to the switching element Q1, is formed on the front surface of the common electrode 114 DS upper panel 113, and receives the common voltage Vcom.

The storage capacitor C _ST is formed by overlapping a separate signal line (not shown) and the pixel electrode 112 provided on the lower panel 111, and a predetermined voltage such as a common voltage Vcom is applied to the separate signal line. do.

Meanwhile, in order to implement color display, each pixel must be configured to display color, which is possible by providing a red, green, or blue color filter 115 in a region corresponding to the pixel electrode 112. In FIG. 2, the color filter 115 is illustrated as formed in a corresponding region of the upper panel 113.

Referring to FIG. 1, the timing controller 120 responds to image data signals R, G, and B, a data enable signal DE, synchronization signals HSYNC and VSYNC, and a clock signal MCLK provided from the outside. Thus, control signals CONT1 and CONT2 and data signals R ', G', and B 'for controlling the operation of the data driving circuit 140 and the gate driving circuits 150L and 150R are generated.

The gray voltage generator 130 generates a pair of gray voltages related to the transmittance of the pixel. Each of the pair of gray voltages has a positive value and a negative value based on the common voltage Vcom.

The data driving circuit 140 generally includes a plurality of data driving ICs and is connected to the data lines of the liquid crystal panel assembly 110, and data signals R ′, G ′, and B from the timing controller 120. And one of the gray voltages from the gray voltage generator 130 are selected in response to the control signal CONT2 and applied to the pixel as a data signal.

The gate driving circuit 150L is disposed on the left side of the liquid crystal panel assembly 110, is connected to odd-numbered gate lines G1, G3,..., G2n-1, and is connected from the outside in response to the control signal CONT1. The gate on voltage Von and the gate off voltage Voff are provided to the gate lines. The gate driving circuit 150R is disposed on the right side of the liquid crystal panel assembly 110, is connected to even-numbered gate lines G2, G4,..., G2n, and gate-on from the outside in response to the control signal CONT1. The voltage Von and the gate off voltage Voff are provided to the gate lines.

The control signal CONT1 provided from the timing controller 120 to the gate driving circuits 150L and 150R indicates the vertical synchronization start signals STVL and STVR indicating the start of the output of the gate on pulse and the timing of the output of the gate on pulse. And controlling the gate clock signals CKL, CLBL, CKR, and CKBR, and an output enable signal OE defining a width of the gate-on pulse.

When the gate-on voltage Von is applied to one gate line and the switching elements connected thereto are turned on, the data driving circuit 140 transfers the data voltage to the data lines D1 -Dm. The data voltages supplied to the data lines D1 -Dm are applied to the pixels through the turned on switching elements. In general, the period during which a row of switching elements are turned on is referred to as '1H' or 'horizontal period'. In the embodiment of the present invention, since the number of gate lines is twice the number of pixel in the column direction, the gate-on voltage Von is sequentially applied to all the gate lines G1 -G2n in the liquid crystal panel assembly 110 for one frame. It takes 2nH to supply. In the liquid crystal display device 100 according to an exemplary embodiment, the period for applying the gate-on voltage Von to each of the gate lines G1 -G2n is maintained at 1H, but the gate-on voltages are adjacent to the gate lines. The period of applying (Von) is overlapped by 1 / 2H so as to have the same gate line driving time as the single bank driving method.

3 is a diagram illustrating an example of the gate driving circuits 150L and 150R shown in FIG. 1. Referring to FIG. 3, the gate driving circuit 150L includes a plurality of shift registers 151a through 151e respectively connected to odd-numbered gate lines, and the gate driving circuit 150R is connected to odd-numbered gate lines, respectively. A plurality of shift registers 152a-152e are included. A detailed configuration of the shift register is shown by way of example in FIG. 4.

Referring to FIG. 4, the shift register 151 includes an SR latch circuit 400 and an AND gate 410. When the output of the AND gate 410 is connected to the k-th gate line Gk, the first input terminal S of the SR latch circuit 400 is connected to the k-th gate line Gk-2, and the second input terminal ( R) is connected to the k + 2th gate line Gk + 2. The clock signal CK input to the AND gate 410 is a corresponding clock signal among CKL, CLBL, CKR, and CLBR. 5 is a timing diagram of signals used in the operation of the shift register 151 shown in FIG.

The first input terminal S of the SR latch circuit 400 in the first shift register 151a of the gate driving circuit 150L is connected to the vertical synchronization start signal STVL, and the first shift of the gate driving circuit 150R is performed. The first input terminal S of the SR latch circuit in the register 152a is connected with the vertical synchronization start signal STVR. The vertical synchronization start signals STVL and STVR have a phase difference of 1 / 2H. FIG. 6 is a timing diagram illustrating that the gate lines G1-G2n are driven by the operations of the gate driving circuits 150L and 150R shown in FIG. 3. As shown in FIG. 6, the gate lines G1 -G2n are sequentially driven with the gate-on voltage Von during the 1H period, and the intervals where the adjacent gate lines are driven with the gate-on voltage Von are 1 / 2H. Overlap each other.

7 exemplarily shows that two adjacent gate lines Gk and Gk + 1 are driven with the gate-on voltage Von. In FIG. 7, the pixel voltages Px1a and Px1b represent changes in complementary data voltages of the pixel Px1 connected to the gate line Gk, and the pixel voltages Px2a and Px2b respectively represent the pixel Px2 connected to the gate line Gk + 1. Each represents a change in the complementary data voltages.

The pixel Px1 is precharged by the data signal during the first period T1 in which the gate line Gk is driven by the gate-on voltage Von, and the pixel Px1 is the actual data signal during the second period T2. Driven by. During the third period T3, the pixel Px1 is floated.

Meanwhile, the pixel Px2 is precharged by the data signal of the gate line Gk during the second period T2 in which the gate line Gk + 1 is driven by the gate-on voltage Von, and the third period T3. Pixel Px2 is driven by the actual data signal. During the third period T3, the pixel Px2 is driven with an actual data signal.

In the third period T3, a voltage drop occurs in the floating state of the pixel Px1 due to the coupling capacitance Cc between the gate line Gk + 1 and the pixel Px1. The coupling capacitance Cc between the pixel Px1 and the gate line Gk + 1 is shown in FIG. 2. This kick-back phenomenon A1 causes vertical streaks.

8 is a diagram illustrating gate driving circuits according to an exemplary embodiment of the present invention.

Referring to FIG. 8, the gate driving circuit 810L disposed on the left side of the liquid crystal panel assembly 110 includes a plurality of shift registers 811a-811e and a ground transistor 812. Shift registers 811a-811e are connected to odd-numbered gate lines G1, G3,..., G2n-1. The ground transistor 812 is connected between the output of the shift register 811e and the ground voltage and controlled by the vertical synchronization start signal STVL. When the vertical synchronization start signal STVL is activated, the reset signal F_RSTL for resetting the shift registers 811a-811e is activated by the ground transistor 812.

 The gate driving circuit 810L disposed on the right side of the liquid crystal panel assembly 110 includes a plurality of shift registers 821a-821e and a ground transistor 812. Shift registers 821a-821e are connected to even-numbered gate lines G2, G4,..., G2n. Ground transistor 822 is connected between ground voltage and shift register 821a and controlled by the vertical sync start signal STVR. When the vertical synchronization start signal STVL is activated, the reset signal F_RSTR for resetting the shift registers 821a-821e is activated by the ground transistor 822. The scheme for resetting the shift registers 811a-811e and 821a-821e is far from the main feature of the present invention, and thus detailed description thereof is omitted herein.

 Each of the shift registers 811a-811e and 812a-812e has the same configuration as the shift register 151 shown in FIG. 4. However, the first input terminal S of the RS latch in the shift register 811a receives the vertical synchronization start signal STVL as an input, and the first input terminal S of the RS latch in the shift register 812e receives the vertical synchronization start signal. (STVR) is taken as input.

FIG. 9 is a timing diagram of signals by operations of the gate driving circuits 810L and 810R shown in FIG. 8. 8 and 9, since the vertical synchronization start signal STVL is input to the shift register 811a, the gate-on voltage Von is sequentially performed for 1H from the gate line G1 to the gate line G2n-1. Driven by. On the other hand, since the vertical synchronization start signal STVR is input to the shift register 821e, the vertical synchronization start signal STVR is driven with the gate-on voltage Von sequentially for 1H in the reverse direction from the gate line G2n to the gate line G2.

As such, the vertical synchronization start signals STVL and STVR are inputted in opposite directions of the gate driving circuits 810L and 810R so that two adjacent gate lines are not driven simultaneously with the gate-on voltage Von.

FIG. 10 is a diagram illustrating a change in pixel voltage when the gate lines Gk and Gk + 1 are driven by the gate driving circuits 810L and 810R shown in FIG. 8. The pixel Px1 connected to the gate line Gk is precharged in the first period T1 and driven as a data signal in the second period T2. When the adjacent gate line Gk + 1 is driven with the gate-on voltage Von, the pixel voltage Px1a / Px1b in the floating state slightly rises due to capacitance with the gate line Gk + 1, and again, the adjacent gate line When (Gk + 1) is driven to the ground voltage, the pixel voltages Px1a / Px1b fall. The magnitude of the rising voltage of the pixel Px1 coincides with the magnitude of the rising of the voltage, and the period that is higher than the floating state is 1H, which is a gate line driving time. Since 1H is a short time in one frame, it is difficult for a user to detect a change in the pixel Px1 voltage.

Such a gate line driving scheme may also be driven at a gate-on voltage such that two adjacent gate lines overlap each other at a central portion of the liquid crystal panel assembly 100. This can be prevented by adjusting the number 2n of gate lines. For example, when the number of gate lines is 801, the 399 th gate line and the 401 th gate line are driven to overlap each other, and the 400 th gate line is driven alone.

In the embodiment of the present invention, the first gate line G1 in the gate driving circuit 810L to the last gate line G2n-1 and the first gate line G2n in the gate driving circuit 810R from the first Although described as being driven in the order of the gate line G2, noise caused by the coupling capacitance between the gate line and the pixel may be prevented by driving the gate lines so that two adjacent gate lines do not overlap.

While the invention has been described using exemplary preferred embodiments, it will be understood that the scope of the invention is not limited to the disclosed embodiments. Rather, the scope of the present invention is intended to include all of the various modifications and similar configurations. Accordingly, the claims should be construed as broadly as possible to cover all such modifications and similar constructions.

According to the present invention, the gate line driving speed is improved by overlapping the interval where two gate lines are driven by the gate-on voltage Von by 1 / 2H in the dual bank structure. In addition, the noise phenomenon caused by driving of the adjacent gate line is reduced by preventing the two adjacent gate lines from being driven at the gate-on voltage Von overlapping each other.

Claims (12)

A plurality of gate lines; A plurality of data lines; An array of pixels arranged in regions where the gate lines and the data lines cross each other; A first gate driving circuit connected to a group of the gate lines and driving the group of gate lines; And A second gate driving circuit connected to another group of the gate lines and driving the gate lines of the other group; The first and second gate driving circuits drive the gate lines such that one of the group of gate lines and one of the other group of gate lines overlap for a predetermined time, but adjacent gate lines are not driven to overlap. And a liquid crystal display driving the gate lines. The method of claim 1, The first gate driving circuit includes a plurality of first gate driving units each connected to the group of gate lines; And The second gate driving circuit includes a plurality of second gate driving units connected to the gate lines of the other group, respectively. The method of claim 2, And the gate lines of the group and the gate lines of the other group are alternately arranged one by one. The method of claim 3, wherein The first gate driving circuit drives the group of gate lines in synchronization with a first vertical synchronizing start signal, And the second gate driving circuit drives the gate lines of the other group in synchronization with a second vertical synchronization signal. The method of claim 4, wherein The first vertical synchronization start signal is provided to a first first gate driving unit of the plurality of first gate driving units; And the second vertical synchronization start signal is provided to a last second gate driving unit of the plurality of second gate driving units. The method of claim 4, wherein Each of the plurality of gate lines is driven at a gate-on voltage for 1H (H is a horizontal period). The method of claim 6, And the first vertical synchronizing signal and the second vertical synchronizing signal have a phase difference by 1 / 2H. A plurality of gate lines; A plurality of data lines; An array of pixels disposed in regions where the gate lines and the data lines cross each other; A first gate driving circuit sequentially driving odd-numbered gate lines of the gate lines in a first direction; And And a second gate driving circuit which sequentially drives even-numbered gate lines of the gate lines in a second direction opposite to the first direction. The method of claim 8, The first gate driving circuit includes a plurality of first gate driving units respectively connected to the odd-numbered gate lines; And The second gate driving circuit includes a plurality of second gate driving units connected to the even-numbered gate lines, respectively. The method of claim 8, The first gate driving circuit sequentially drives the odd-numbered gate lines in the first direction in synchronization with a first vertical synchronization start signal; And the second gate driving circuit sequentially drives the even-numbered gate lines in the second direction in synchronization with a second vertical synchronization start signal. Sequentially driving a group of gate lines; And Sequentially driving other groups of gate lines; The group of gate lines and the other group of gate lines are alternately arranged one by one; And driving the gate lines such that adjacent gate lines of the plurality of gate lines do not overlap each other. Sequentially driving a group of gate lines; And Sequentially driving other groups of gate lines; The group of gate lines and the other group of gate lines are alternately arranged one by one; The gate line such that a voltage of a pixel connected to a gate line adjacent to the gate line of the other group of the gate lines when the gate line of any one of the gate lines of the other group is driven increases or decreases according to the driving of the gate line; Method of driving a liquid crystal display device for driving them.

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