KR101001052B1 - Liquid Crystal Display Panel And Driving Method Thereof - Google Patents

Abstract

The present invention relates to a liquid crystal display panel and a driving method thereof capable of realizing high resolution and reducing the number of signal lines.

According to an exemplary embodiment of the present invention, a liquid crystal display panel includes a data line supplied with data, a gate line supplied with two or more scan signals in succession, a plurality of sub pixels defined by the gate line and the data line, and the scan signal. At least one switch element for supplying said data to said subpixels in response to each one of said pixels, each pixel comprising at least four said subpixels and having a number of data lines smaller than the number of said subpixels; Data is supplied to the subpixels, and at least one of the gate lines is bent to surround a specific subpixel.

Description

Liquid Crystal Display Panel And Driving Method Thereof}             

1 is a block diagram showing the configuration of a conventional liquid crystal display device.

FIG. 2 is a plan view illustrating a liquid crystal cell structure of the liquid crystal panel shown in FIG. 1.

3 is a plan view showing each pixel composed of a general subpixel.

4 is a plan view illustrating each pixel for implementing a high resolution.

5 is a plan view illustrating a liquid crystal display panel according to the present invention.

6 is a plan view illustrating a driving waveform for driving the liquid crystal display panel illustrated in FIG. 5.

7A to 7C are diagrams illustrating various arrangements of subpixels included in each pixel according to the present invention.

<Description of Symbols for Main Parts of Drawings>

2 liquid crystal display panel 4 gate driver

6: Data driver 8: Gamma voltage generator

10: timing control unit 12: thin film transistor                 

14 storage capacitor 16 gate electrode

18: source electrode 20: drain electrode

22: pixel electrode

The present invention relates to a liquid crystal display panel, and more particularly, to a liquid crystal display panel and a driving method thereof capable of realizing high resolution and reducing the number of signal lines.

A conventional liquid crystal display device displays an image by adjusting the light transmittance of a liquid crystal using an electric field. To this end, the liquid crystal display includes a liquid crystal panel in which liquid crystal cells are arranged in a matrix and a driving circuit for driving the liquid crystal panel.

In fact, the liquid crystal display includes a liquid crystal panel 2 in which liquid crystal cells are arranged in a matrix as shown in FIG. 1, and a gate driver 4 for driving gate lines GL0 to GLn of the liquid crystal panel 2. ), A data driver 6 for driving the data lines DL1 to DLm of the liquid crystal panel 2, a gamma voltage generator 8 for supplying a gamma voltage to the data driver 6, and a gate. A timing controller 10 for controlling the driver 4 and the data driver 6 is provided.

The timing controller 10 controls the driving timing of the gate driver 4 and the data driver 6 in response to a clock signal, horizontal and vertical synchronization signals, etc. input from the outside. In other words, the timing controller 10 generates and supplies a gate shift clock GSC, a gate start pulse GSP, and the like to the gate driver 4 in response to the clock signal and the horizontal and vertical synchronization signals. In addition, the timing controller 10 generates a data clock signal, a data control signal, a polarity control signal, and the like in response to the input clock signal and the horizontal and vertical synchronization signals, and supplies the same to the data clock signal. The red (R), green (G), and blue (B) video data input from the outside are supplied to the data driver 6.

The gate driver 4 supplies the gate high voltage to the gate lines GL1 to GLn during the corresponding syringe period (1H) in response to the control of the timing controller 10 to drive the thin film transistors TFT. In the period, the gate low voltage is applied. In addition, the gate driver 4 applies a gate low voltage to the uppermost gate line GL0 formed for the storage capacitor Cst of the first scan line.

The data driver 6 converts a digital data signal from the timing controller 10 into an analog data signal in response to the control of the timing controller 10 to supply a gate high voltage to the gate lines GL1 to GLn for one horizontal period. The data signal for one horizontal line is supplied to the data lines DL1 to DLm every (1H). At this time, the gamma voltage generator 8 supplies the data driver 6 with a gamma voltage which is set in advance to have a different level according to the voltage level of the data signal. The data driver 6 converts the digital data signal into an analog data signal using a gamma voltage so that the gamma characteristic of the liquid crystal display device is corrected. In addition, the data driver 6 inverts the polarity of the data signals supplied to the data lines DL1 to DLm according to the polarity control signal from the timing controller 10.

The liquid crystal panel 2 is a thin film transistor TFT formed at intersections of liquid crystal cells arranged in a matrix form and n + 1 gate lines GL0 to GLn and m data lines DL1 to DLm. It is provided. The thin film transistor TFT supplies a data signal from the data lines DL1 to DLm to the liquid crystal cell in response to the gate high voltages from the gate lines GL1 to GLn. The liquid crystal cell may be equivalently represented by a liquid crystal capacitor Clc including a common electrode facing the liquid crystal and a pixel electrode connected to the thin film transistor TFT. A storage capacitor Cst is further formed in the liquid crystal cell to maintain the data voltage charged in the liquid crystal capacitor Clc until the next data voltage is charged, that is, while the gate low voltage is applied. The storage capacitor Cst is formed between the previous gate line and the pixel electrode.

In the liquid crystal panel 2, the thin film transistor array substrate that determines the shape of the liquid crystal cell is illustrated in FIG. 2.

Referring to FIG. 2, a pixel electrode 22 is provided in a cell region having a cross structure of gate lines GL0, GL1,..., And data lines DL1, DL2,. The pixel electrode 22 is connected to any one of the data lines DL1, DL2,... Through the source and drain electrodes 18, 20 of the thin film transistor 12. The gate electrode 16 of the thin film transistor 12 is connected to any one of the gate lines GL1, GL2,... The storage capacitor 14 is formed at an overlapping portion of the pixel electrode 22 and the previous gate line GLi-1. Each of the data lines DL1, DL2, ... is supplied with red, green, and blue data signals for color display.

Red, green, and blue color filters are formed to correspond to the cell region in which the pixel electrode 22 is formed, and the reference voltage is supplied to the thin film transistor array substrate and the upper substrate, which faces the liquid crystal layer. The common electrode is formed in front. Each of the liquid crystal cells in which the red, green, and blue color filters are formed corresponds to the subpixels (R, G, and B), and is a combination of the red, green, and blue subpixels (R, G, and B) arranged side by side. The pixel is represented.

In the conventional liquid crystal display device having such a configuration, the number of pixels is increasing as the resolution is increased to display a clear image. For example, as shown in FIG. 3, a liquid crystal display panel for a TV requires 1200 gate lines and 1900 data lines, and the size of each sub-pixel located in a pixel area formed at the intersection of each gate line and data line. Is relatively large. That is, three data lines and one gate line are required to implement one pixel shown in FIG. 3.

In order to implement such a liquid crystal display panel for a TV at high resolution, the number of pixels is increased by about 2 times by applying 2 × 1200 gate lines and 2 × 1900 data lines. At this time, the size of each sub-pixel positioned in the pixel area provided at the intersection of the gate line and the data line is about one quarter of the sub-pixels of the liquid crystal display panel for a general TV as shown in FIG. That is, four pixels (six data lines and two gate lines) are required to realize the same area as one pixel shown in FIG. 3 using the pixel shown in FIG. 4.

In order to implement such a high-resolution liquid crystal display panel, a TV image signal of 1200 × 1920 is inputted, one frame is divided into a first subframe and a second subframe, and the odd gate lines are sequentially driven during the first subframe. The even-numbered gate lines are sequentially driven during two subframes. In other words, pixels connected to the odd gate lines are provided by supplying scan pulses to the odd gate lines during the first subframe, and the even gate lines are sequentially supplied by supplying scan pulses to the even gate lines during the second subframe. The pixel connected to the is implemented. However, the liquid crystal display panel has a problem in that brightness is relatively decreased because pixels not implemented in each subframe are about 1/2 of all pixels.

In addition, an increase in the number of pixels doubles the number of data lines and gate lines, thereby increasing the number of integrated integrated circuits (ICs) for driving them, in particular, the number of expensive data drive ICs, thereby increasing the manufacturing cost.

Accordingly, an object of the present invention is to provide a liquid crystal display panel and a driving method thereof capable of realizing high resolution and reducing the number of signal lines.

In order to achieve the above object, the liquid crystal display panel according to the present invention includes a data line to which data is supplied, a gate line to which two or more scan signals are continuously supplied, and a plurality of subs defined by the gate line and the data line. Pixels and at least one switch element for supplying said data to said subpixels in response to said scan signal, each pixel comprising at least four said subpixels and having a number greater than the number of said subpixels; Data is supplied to the subpixels through a small number of data lines, and at least one of the gate lines is bent to surround a specific subpixel.

The data line may include first to third data lines, and the gate line may include first and second gate lines.

The at least four sub-pixels are formed in a pixel area formed by the first data line and the first gate line and are formed on one side of the first data line; A second subpixel formed in a pixel area formed by the first data line and the second gate line and formed at one side of the first data line; A third sub-pixel formed in the pixel area provided by the third data line and the first gate line and formed at one side of the third data line; A fourth sub-pixel formed in the pixel area provided by the third data line and the second gate line and formed on one side of the third data line; A fifth subpixel formed in the pixel region provided by the second data line and the second gate line; A sixth subpixel formed in the pixel area formed by the first data line and the first gate line and formed on the other side based on the first data line; A seventh sub-pixel formed in the pixel area formed by the third data line and the first gate line and formed on the other side of the third data line; An eighth sub-pixel formed in the pixel area formed by the first data line and the second gate line and formed on the other side of the first data line; And a ninth sub-pixel formed in the pixel area provided by the third data line and the second gate line and formed on the other side of the third data line.

Each of the first to fifth subpixels may include a first thin film transistor connected to any one of the first and second gate lines and any one of the first to third data lines.

Each of the sixth to ninth subpixels may include a second thin film transistor connected to one of the first and third data lines and an i th gate line; and a third thin film transistor connected to the i + 1 th gate line and the first thin film transistor to supply a video signal from the data line to the liquid crystal cell.

The second gate line of the gate line is bent to surround the fifth sub-pixel.

In order to achieve the above object, a method of driving a liquid crystal display panel according to the present invention includes first data supplied from a data line when first and second gate signals are supplied to an i th gate line and an i + 1 th gate line, respectively. And supplying second data supplied from the data line to the subpixels when the first gate signal is supplied to the i-th gate line. The liquid crystal display panel having the subpixels may include: a data line to which data is supplied; a gate line to which two or more scan signals are successively supplied; a plurality of sub pixels defined by the gate line and the data line; At least one switch element for supplying said data to said subpixels in response to a scan signal, each one pixel being at least Data is supplied to the subpixels through the data lines including the four subpixels and smaller than the number of the subpixels, and at least one of the gate lines is bent to surround a specific subpixel. It is done.

The pulse width of the first gate signal may be formed to be relatively wider than the pulse width of the second gate signal.

The first step is to supply one of the green and red data to the sixth and eighth sub-pixels connected to the data line through the j-th data line, and connect the data line through the j + 2 th data line. And supplying the remaining data of the red and green data to the seventh and ninth sub-pixels.

The second step may include supplying any one of red, green, and blue data to first through fifth subpixels connected to the data lines through the j th through j + 2 th data lines, respectively. It is done.

Other objects and advantages of the present invention in addition to the above objects will become apparent from the detailed description of the embodiments with reference to the accompanying drawings.                     

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to FIGS. 5 to 7C.

5 is a plan view illustrating a liquid crystal display panel according to the present invention.

Each of the pixels PXL illustrated in FIG. 5 has four subpixels R1, R2, R3, and R4 disposed between the B subpixel B positioned at the center of the pixel and the B subpixel B interposed therebetween. ) And four G subpixels G1, G2, G3, and G4 alternately formed with the R subpixels R1, R2, R3, and R4. Thus, each pixel PXL is composed of nine sub-pixels R1, G1, B1, R2, G2, and B2, and the area of each pixel is similar to that of the pixel shown in FIG.

In addition, a total of two first and second gate lines GLm1 and GLm2 are required for the gate line GL for supplying a gate signal for driving each pixel, and a data line DL for supplying data is first. To third data lines DLi1, DLi2, and DLi3.

The first gate line GLm1 is connected to gate electrodes of each of the first thin film transistor T1, the second thin film transistor T2, the third thin film transistor T3, and the fifth thin film transistor T5.

The second gate line GLm2 includes a fourth thin film transistor T4 connected to the third thin film transistor T3, a sixth thin film transistor T6 connected to the fifth thin film transistor T5, and a seventh thin film transistor T7. ), The eighth thin film transistor T8, the tenth thin film transistor T10, the twelfth thin film transistor T12, and the thirteenth thin film transistor T13. The second gate line GLm2 is branched to surround the B subpixel B, and is formed to intersect the first R subpixel R1 and the fourth G subpixel G4 facing up and down. For example, the second G subpixel G2 and the fourth R subpixel R4 face each other.

The first gate line GLn1 of the next stage is connected to the gate electrode of each of the ninth thin film transistor T9 connected to the eighth thin film transistor T8 and the eleventh thin film transistor T11 connected to the tenth thin film transistor T10. do.

The first data line DLi1 is connected to the source electrodes of each of the first thin film transistor T1, the third thin film transistor T3, the ninth thin film transistor T9, and the twelfth thin film transistor T12, and is connected to each of them. And at least one of the green data signal.

The second data lines DLi2 and DLj2 are connected to the source electrode of the seventh thin film transistor T7 to supply a blue data signal to the source electrode.

The third data lines DLi3 and DLj3 are connected to source electrodes of the second thin film transistor T2, the fifth thin film transistor T5, the eleventh thin film transistor T11, and the thirteenth thin film transistor T13, respectively. At least one of the green and red data signals is supplied to the.

Each of the subpixels R1, R2, R3, R4, G1, G2, G3, G4, and B has thirteen thin film transistors 30 connected to the gate line GL and the data line DL as switching elements. do.

That is, the first R subpixel R1 represents the first thin film transistor T1, the second R subpixel R2 represents the fifth and sixth thin film transistors T5 and T6, and the third R subpixel R3. ) Is the eighth and ninth thin film transistors T8 and T9, the fourth R subpixel R4 is the thirteenth thin film transistor T13, and the first G subpixel G1 is the third and fourth thin film transistors. (T3, T4), the second G subpixel G2 is the second thin film transistor T2, the third G subpixel G3 is the tenth and eleventh thin film transistors T10, T11, and the fourth The G subpixel G4 includes the twelfth thin film transistor T12 and the B subpixel B includes the seventh thin film transistor T7.

The first thin film transistor T1 of the first R subpixel R1 includes a gate electrode connected to the first gate line GLm1, a source electrode connected to the first data line DLi1, and a liquid crystal cell. A drain electrode is provided.

The fifth thin film transistor T5 of the second R subpixel R2 includes a gate electrode connected to the first gate line GLm1, a source electrode connected to the third data line DLi3, and a sixth thin film transistor (T5). A sixth thin film transistor T6 includes a gate electrode connected to the second gate line GLm2, a source electrode connected to the fifth thin film transistor T5, and a liquid crystal cell. A connected drain electrode is provided.

The ninth thin film transistor T9 of the third R subpixel R3 includes a gate electrode connected to the next gate line GLn1, a source electrode connected to the first data line DLi1, and an eighth thin film transistor T9. A drain electrode connected to the transistor T8; the eighth thin film transistor T8 includes a gate electrode connected to the second gate line GLm2, a source electrode connected to the ninth thin film transistor T9, and a liquid crystal. A drain electrode connected to the cell is provided.

The thirteenth thin film transistor T13 of the fourth R subpixel R4 includes a gate electrode connected to the second gate line GLm2, a source electrode connected to the third data line DLi3, and a liquid crystal cell connected to the liquid crystal cell. A drain electrode is provided.

The third thin film transistor T3 of the first G subpixel G1 includes a gate electrode connected to the first gate line GLm1, a source electrode connected to the first data line DLi1, and a fourth thin film transistor T3. And a drain electrode connected to the emitter T6, the fourth thin film transistor T4 includes a gate electrode connected to the second gate line GLm2, a source electrode connected to the third thin film transistor T3, and a liquid crystal. A drain electrode connected to the cell is provided.

The second thin film transistor T2 of the second G subpixel G2 includes a gate electrode connected to the first gate line GLm1, a source electrode connected to the third data line DLi3, and a liquid crystal cell connected to the liquid crystal cell. A drain electrode is provided.

The eleventh thin film transistor T11 of the third G subpixel G3 includes a gate electrode connected to the next gate line GLn1, a source electrode connected to the third data line DLi3, and a tenth thin film. And a drain electrode connected to the transistor T10, wherein the tenth thin film transistor T10 includes a gate electrode connected to the second gate line GLm2, a source electrode connected to the eleventh thin film transistor T11, and a liquid crystal. A drain electrode connected to the cell is provided.

The twelfth thin film transistor T12 of the fourth G subpixel G4 includes a gate electrode connected to the second gate line GLm2, a source electrode connected to the first data line DLi1, and a liquid crystal cell connected to the liquid crystal cell. A drain electrode is provided.

The seventh thin film transistor T7 of the B subpixel B includes a gate electrode connected to the second gate line GLm2, a source electrode connected to the second data line DLi2, and a drain electrode connected to the liquid crystal cell. It is provided.

The driving method of the liquid crystal display panel according to the present invention will be described in detail with reference to FIG. 6.                     

Referring to FIG. 6, the liquid crystal display panel according to the present invention supplies the second gate signal SP2 to the first gate line GLm1 and the second gate line GLm2 during the first horizontal period H1. The first gate signal SP1 is supplied. Here, since the width of the second gate signal SP2 is set to be wider than the width of the first gate signal SP1, the first gate signal SP1 and the second gate signal SP2 simultaneously operate during the first period P1. Only the second gate signal SP2 is applied during the second period P2 following the first period P1.

The third and third periods during the first period P1 during which the first gate signal SP1 is applied to the second gate line GLm2 and the second gate signal SP2 is applied to the first gate line GL1. 4 The thin film transistors T3 and T4 are turned on so that the green data is supplied to the first G subpixel G1 through the first data line DLi1, and the fifth and sixth thin film transistors T5 and T6 are turned on. The red data is supplied to the second R subpixel R2 through the third data line DLi3.

In detail, the third and fifth thin film transistors T3 and T5 are turned on by the second gate signal SP2 supplied to the first gate line GLm1, thereby being supplied from the first data line DLi1. Green data is supplied to the source electrode of the third thin film transistor T4, and red data supplied from the third data line DLi3 is supplied to the source electrode of the fifth thin film transistor T5. At this time, the fourth and sixth thin film transistors T4 and T6 are turned on by the first gate signal SP1 supplied to the second gate line GLm2, so that the green data of the first G subpixel G1 is turned on. The red data is supplied to the liquid crystal cell, and the red data is supplied to the liquid crystal cell of the second R subpixel R2.

That is, during the first period P1 during which the first gate signal SP1 is applied to the second gate line GLm2 and the second gate signal SP2 is applied to the first gate line GLm1. Red data is supplied to the 2R subpixel R2, and green data is supplied to the first G subpixel G1.

Subsequently, in the second period P2, the first and second thin film transistors T2 and T5 connected to the first gate line GL1 are turned on. When the first thin film transistor T5 is turned on, the red data supplied to the first data line DLi1 during the second period P2 is supplied to the first R subpixel R1, and the second thin film transistor T2 is When turned on, the green data supplied to the third data line DLi3 during the second period P2 is supplied to the second G subpixel G2.

The second gate signal SP2 is supplied to the second gate line GLm2 during the second horizontal period H2, and the first gate signal SP1 is supplied to the third gate line GLm3. Here, the first gate signal SP1 and the second gate signal SP2 are simultaneously applied to each of the third and second gate lines GLm3 and GLm2 during the third period P3, and during the fourth period P4. Only the second gate signal SP2 is applied to the second gate line GLm2.

The eighth and ninth periods during the third period P3 during which the first gate signal SP1 is applied to the third gate line GLm3 and the second gate signal SP2 is applied to the second gate line GLm2. The thin film transistors T8 and T9 are turned on so that red data is supplied to the third R subpixel R3 through the first data line DLi1, and the tenth and eleventh thin film transistors T10 and T11 are turned on to be green. The data is supplied to the third G subpixel G3 through the third data line DLi3.

In detail, the ninth and eleventh thin film transistors T9 and T11 are turned on by the first gate signal SP1 supplied to the third gate line GLm3 so that the red color is supplied from the first data line DLi1. Data is supplied to the source electrode of the eighth thin film transistor T8, and green data supplied from the third data line DLi3 is supplied to the source electrode of the tenth thin film transistor T10. At this time, the eighth and tenth thin film transistors T8 and T10 are turned on by the second gate signal SP2 supplied to the second gate line GLm2, so that the red data is the liquid crystal of the third R subpixel R3. The green data is supplied to the cell, and the green data is supplied to the liquid crystal cell of the third G subpixel G3.

That is, the first gate signal SP1 is applied to the (i + 1) th gate line GL (i + 1) 1 and the second gate signal SP2 is applied to the i2nd gate line GLi2. Red data is supplied to the second R subpixel R2 and green data is supplied to the second G subpixel G2 during the applied third period P3.

Subsequently, the seventh, twelfth, and thirteenth thin film transistors T7, T12, and T13 connected to the second gate line GLm2 are turned on in the fourth period P4. When the seventh thin film transistor T7 is turned on, the blue data supplied to the second data line DLi2 during the fourth period P4 is supplied to the B sub-pixel B. When the twelfth thin film transistor T12 is turned on, the green data supplied to the fourth data line DLi1 during the fourth period P4 is supplied to the fourth G subpixel G4. When the thirteenth thin film transistor T13 is turned on, red data supplied to the third data line DLi3 during the fourth period P4 is supplied to the fourth R subpixel R4.

As described above, the liquid crystal display panel and the driving method thereof according to the present invention are conventionally composed of three subpixels as each pixel is composed of nine subpixels R1, G1, B1, R2, G2, and B2. The same resolution may be realized by using fewer pixels than the liquid crystal display panel. In addition, since only three data lines are required for each pixel, the aperture ratio is improved by reducing the data lines, and the number of data lines is reduced, thereby reducing the number of expensive data drive ICs and further improving the yield.

Meanwhile, the liquid crystal display panel according to the present invention may change the arrangement and the area of the R, G, and B subpixels in various forms as shown in FIGS. 7A to 7C. For example, in the liquid crystal display panel illustrated in FIG. 7A, sub-pixels vertically and horizontally adjacent to each other except for B sub-pixels realize different colors. That is, the R subpixels and the G subpixels are formed alternately. In the liquid crystal display panel illustrated in FIG. 7B, the area of the B subpixel is made smaller than the B subpixel illustrated in FIG. 8A, so that the areas of the R subpixel and the G subpixel adjacent to the B subpixel are relatively wider. In the liquid crystal display panel illustrated in FIG. 7C, vertically adjacent subpixels except for B subpixels implement the same color, and horizontally adjacent subpixels implement different colors. In addition, although the sub-pixels of the liquid crystal display panel according to the present invention have been described to implement any one of R (Red), G (Green), and B (Blue), other colors other than R, G, and B, for example, Y (Yellow), C (Cyan), M (Magenta), W (White) may be implemented.

As described above, in the liquid crystal display panel and its driving method according to the present invention, each pixel is composed of nine sub-pixels, and each pixel is similar to the area of a conventional high-resolution pixel, thereby realizing the same resolution. In addition, the number of data lines can be reduced by driving up to nine sub-pixels with up to three data lines. As a result, an increase in the number of expensive data drive ICs that are increased to achieve high resolution can be prevented, thereby improving yield.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

Claims (10)

The data line supplied with data, A gate line to which two or more scan signals are continuously supplied; A plurality of sub pixels defined by the gate line and the data line; At least one switch element for supplying the data to the subpixels in response to the scan signal, Each pixel includes at least four of the subpixels, and data is supplied to the subpixels through a number of data lines smaller than the number of the subpixels, and at least one of the gate lines surrounds a specific subpixel. The liquid crystal display panel is formed so as to be bent. The method of claim 1, The data line includes first to third data lines, The gate line includes a first gate line and a second gate line. The method of claim 2, The at least four sub pixels A first subpixel formed in a pixel area formed by the first data line and the first gate line and formed at one side of the first data line; A second subpixel formed in a pixel area formed by the first data line and the second gate line and formed at one side of the first data line; A third sub-pixel formed in the pixel area provided by the third data line and the first gate line and formed at one side of the third data line; A fourth sub-pixel formed in the pixel area provided by the third data line and the second gate line and formed on one side of the third data line; A fifth subpixel formed in the pixel region provided by the second data line and the second gate line; A sixth sub-pixel formed in the pixel area provided by the first data line and the first gate line and formed on the other side of the first data line; A seventh sub-pixel formed in the pixel area formed by the third data line and the first gate line and formed on the other side of the third data line; An eighth sub-pixel formed in the pixel area formed by the first data line and the second gate line and formed on the other side of the first data line; And a ninth sub-pixel formed in the pixel area provided by the third data line and the second gate line and formed on the other side of the third data line. The method of claim 3, wherein Each of the first to fifth subpixels A first thin film transistor connected to any one of the first and second gate lines and any one of the first to third data lines, Each of the sixth to ninth subpixels may be connected to any one of the first and third data lines and the second thin film transistor connected to the first gate line, and the second gate line and the first thin film transistor. And a third thin film transistor for supplying a video signal from the data line to the liquid crystal cell. delete The method of claim 2, And a second gate line of the gate lines is bent to surround the fifth sub-pixel. When the first and second gate signals are supplied to the first gate line and the second gate line, the first data supplied from one of the first to third data lines is supplied to the subpixels. With the first step, And supplying second data supplied from the data line to subpixels when the first gate signal is supplied to the first gate line. The liquid crystal display panel having the subpixels includes a data line to which data is supplied, a gate line to which two or more scan signals are continuously supplied, a plurality of sub pixels defined by the gate line and the data line, and the scan At least one switch element for supplying said data to said subpixels in response to a signal, each pixel comprising at least four or more said subpixels and having fewer than the number of said subpixels Data is supplied to the subpixels through the at least one gate line, and at least one of the gate lines is bent to surround a specific subpixel. The at least four subpixels may include a first subpixel formed in a pixel area formed by the first data line and the first gate line and formed at one side of the first data line, the first data line and the first data line; A second subpixel formed in a pixel area formed by a second gate line and formed at one side of the first data line, and formed in a pixel area provided by the third data line and the first gate line; A third subpixel formed on one side of the data line, a fourth subpixel formed on the pixel region provided by the third data line and the second gate line, and formed on one side of the third data line; A fifth subpixel formed in the pixel area provided by the second data line and the second gate line, and the first data line and the first gate line. A sixth sub-pixel formed in the pixel area provided on the other side of the first data line, and formed in the pixel area provided by the third data line and the first gate line and based on the third data line. An eighth subpixel formed on the other side and a pixel area formed by the first data line and the second gate line, and the eighth subpixel formed on the other side of the first data line and the third data line And a ninth sub-pixel formed in the pixel area provided by the second gate line and formed on the other side of the third data line. The method of claim 7, wherein And the pulse width of the first gate signal is wider than the pulse width of the second gate signal. The method of claim 7, wherein The first step is Supplying any one of green and red data to the sixth and eighth sub-pixels connected to the data line through the first data line, and the seventh and ninth data connected to the data line through the third data line. And supplying the remaining data of the red and green data to the sub-pixels. The method of claim 7, wherein The second step is Supplying any one of red, green, and blue data to the first to fifth subpixels connected to the data lines through the first to third data lines, respectively. Driving method.

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