KR20060007681A - Method for forming capacitor of semiconductor device - Google Patents

Abstract

The present invention discloses a method for forming a capacitor of a semiconductor device capable of improving the yield of the device. The disclosed method includes providing a semiconductor substrate having a contact plug made of polysilicon; Sequentially forming an etch stop layer and a first oxide layer having a contact hole exposing the contact plug on the substrate; Selectively forming a silicide layer on a surface of the exposed contact plug; Sequentially forming a TiN film for a storage node electrode and a polysilicon film over the resulting structure; Forming a second oxide film on the polysilicon film to fill the entire second contact hole structure; Etching the second oxide film, the polycrystalline silicon film, and the TiN film until the first oxide film is exposed; Removing the remaining first and second oxide films by wet etching while protecting the TiN film by using the remaining polysilicon film as an etching barrier; Removing the remaining polysilicon layer by wet etching to form a storage node electrode; And sequentially forming a dielectric film and a conductive film for plate node electrodes on the entire structure of the resultant structure.

Description

METHODS FOR FORMING CAPACITOR OF SEMICONDUCTOR DEVICE

1A to 1C are cross-sectional views of respective processes for explaining a method of forming a capacitor of a semiconductor device according to the related art.

2 is a cross-sectional view for explaining a problem according to the prior art.

Figure 3 is an enlarged cross-sectional view of the penetration path of the chemical solution in the prior art.

4A to 4D are cross-sectional views of respective processes for explaining a method of forming a capacitor of a semiconductor device according to an embodiment of the present invention.

Explanation of symbols on main parts of drawing

40 semiconductor substrate 41 first interlayer insulating film

42: first contact hole 43: first contact plug

44: etching stop film 45: first oxide film

46: third contact hole 47: silicide layer

48 TiN film for storage node electrode 48a: Storage node electrode

49 polycrystalline silicon film 49a: remaining polycrystalline silicon film

50: second oxide film 51: dielectric film

52: conductive film for plate node electrode

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to preventing the occurrence of bunker-shaped circular defects in an interlayer insulating film formed under a storage node electrode made of a TiN film material, thereby yielding device yields. It relates to a method of forming a capacitor of a semiconductor device to improve the.

As the demand for semiconductor memory devices has soared, various techniques for obtaining high capacity capacitors have been proposed. The capacitor has a structure in which a dielectric film is interposed between a storage node electrode and a plate node electrode, the capacitance of which is proportional to the surface area of the electrode and the dielectric constant of the dielectric film, the spacing between the electrodes, That is, it is inversely proportional to the thickness of the dielectric film.

Therefore, in order to obtain a high capacity capacitor, it is required to use a dielectric film having a high dielectric constant, to enlarge the surface area of the electrode, or to reduce the distance between the electrodes. However, reducing the distance between the electrodes, that is, the thickness of the dielectric film has a limitation, and researches for forming a capacitor having a high capacity have been conducted by using a dielectric film having a high dielectric constant or increasing the surface area of the electrode. .

Here, as an example of increasing the surface area of the electrode, a storage node electrode may be formed into a concave type and a cylinder type, and recently, the surface area is enlarged by using the outer surface of the electrode rather than the concave type. There is a trend to prefer a cylindrical type.

1A to 1C are cross-sectional views illustrating processes of forming a capacitor of a semiconductor device according to the prior art, and a method of forming a capacitor of the semiconductor device according to the related art will be briefly described as follows.

A conventional method of forming a capacitor of a semiconductor device provides a semiconductor substrate 10 having a predetermined substructure (not shown), as shown in FIG. 1A. Then, an interlayer insulating film 11 having a first contact hole 12 exposing a predetermined portion of the substrate 10 is formed on the semiconductor substrate 10. Subsequently, the first contact hole 12 is filled with a conductive film made of polycrystalline silicon to form a contact plug 13.

Next, the etch stop layer 14 and the first oxide layer 15 having the second contact hole 16 exposing the contact plug 13 on the interlayer insulating layer 11 including the contact plug 13. Form in turn.

Subsequently, as illustrated in FIG. 1B, a silicide layer 17 is selectively formed on the surface of the contact plug 13. In this case, the silicide layer 17 serves to lower the contact resistance between the contact plug 13 and the storage node electrode to be formed later. Then, after forming the TiN film 18 for the storage node electrode on the entire structure of the resulting structure, a second oxide film 19 is formed on the TiN film 18 to form the entire structure of the second contact hole 16. Landfill.

Subsequently, as illustrated in FIG. 1C, the second oxide layer and the TiN layer are etched until the first oxide layer is exposed to form a cylindrical storage node electrode 18a. Then, the remaining first and second oxide films are removed by a dip-out process. At this time, the dip out step is performed using a BOE solution as a chemical solution.

Thereafter, a dielectric film and a conductive film for plate node electrodes are sequentially formed over the resulting structure.

2 is a cross-sectional view for explaining a problem according to the prior art, and FIG. 3 is an enlarged cross-sectional view showing a penetration path of the chemical solution in the prior art.

In the related art, as shown in FIGS. 2 and 3, the TiN film 18 used as the storage node electrode is grown in a columnar structure due to its crystal characteristics. At the time, a gap A occurs in the grain boundary of the portion where the crystal growth is weak.

Accordingly, as the dip-out process for removing the remaining first and second oxide films proceeds, a chemical solution used in the dip-out process is formed in the gap A in the TiN film 18. By penetrating into the interlayer insulating film 11 under the TiN film 18 through, the interlayer insulating film 11 is etched to generate a bunker-shaped circular defect (B). As a result, there occurs a problem that the yield of the device is lowered due to the occurrence of the defect (B).

Accordingly, the present invention has been made to solve the above problems, by preventing the chemical solution from penetrating into the interlayer insulating film under the TiN film through a gap generated in the TiN film, thereby preventing the interlayer insulating film from being etched. An object of the present invention is to provide a method for forming a capacitor of a semiconductor device capable of improving the yield of the device.

A method of forming a capacitor of a semiconductor device of the present invention for achieving the above object comprises the steps of providing a semiconductor substrate having a contact plug of polycrystalline silicon; Sequentially forming an etch stop layer and a first oxide layer having a contact hole exposing the contact plug on the substrate; Selectively forming a silicide layer on a surface of the exposed contact plug; Sequentially forming a TiN film for a storage node electrode and a polysilicon film over the resulting structure; Forming a second oxide film on the polysilicon film to fill the entire second contact hole structure; Etching the second oxide film, the polycrystalline silicon film, and the TiN film until the first oxide film is exposed; Removing the remaining first and second oxide films by wet etching while protecting the TiN film by using the remaining polysilicon film as an etching barrier; Removing the remaining polysilicon layer by wet etching to form a storage node electrode; And sequentially forming a dielectric film and a conductive film for plate node electrodes on the entire structure of the resultant structure.

Here, the etch stop film is formed to a thickness of 100 ~ 2000Å by using a nitride film, the first oxide film is formed of any one of a single film and a CVD multiple film, the etch stop film and the first oxide film is 6000 ~ 30000Å It is formed to the thickness of.

The forming of the silicide layer may include forming a barrier metal layer on an entire surface of the substrate including the contact hole structure; Performing an annealing process on the resultant to form a silicide layer on the surface of the contact plug; And removing the unreacted barrier metal film by wet etching in the annealing process, wherein any one of Ti, Co and Zr is used as the barrier metal film.

The TiN film is formed to a thickness of 50 to 1000 Pa by using any one of CVD and ALD, and the polysilicon film is formed to a thickness of 50 to 3000 Pa at a temperature of 300 to 600 ° C.

In addition, the step of removing the remaining first and second oxide film by wet etching, using a HF-based chemical solution is carried out a dip out process for 10 to 3600 seconds at a temperature of 4 ~ 80 ℃, the residual The step of removing the polysilicon film by wet etching may be performed using a mixed solution of NH ₄ OH and H ₂ O and a mixed solution of HF and HNO ₃ as an etching solution at a temperature of 4 to 100 ° C. for 5 to 3600 seconds. To be carried out. In this case, as the mixed solution of NH ₄ OH and H ₂ O, a solution in which NH ₄ OH and H ₂ O are mixed at a composition ratio of 10: 1 to a volume ratio of 1: 500 is used, and the HF and As a mixed solution of HNO ₃ , a solution in which HF and HNO ₃ are mixed at a composition ratio of 20: 1 to a solution mixed at a volume ratio of 1: 100 is used.

The dielectric film may be formed using any one or more of TaON, Ta ₂ O ₅ , TiO ₂ , Al ₂ O ₃ , HfO ₂ , HfN, SrTiO ₃ , (Ba, Sr) TiO _3, and (Pb, Sr) TiO ₃ . It is formed to a thickness of 50 ~ 400Å, the dielectric film is formed by any one of metal organic chemical vapor deposition method and ALD.

In addition, the conductive film for the plate node electrode is formed to a thickness of 500 ~ 3000Å by using any one of the TiN, Ru and polycrystalline silicon film, the conductive film for the plate node electrode by any one of sputtering, CVD and ALD method Form.

(Example)

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

4A to 4D are cross-sectional views of respective processes for explaining a method of forming a capacitor of a semiconductor device according to an embodiment of the present invention.

According to an embodiment of the present invention, a method of forming a capacitor of a semiconductor device provides a semiconductor substrate 40 having a predetermined substructure (not shown), as shown in FIG. 4A. Then, a first interlayer insulating film 41 having a first contact hole 42 exposing a predetermined portion of the substrate 40 is formed on the semiconductor substrate 40. Subsequently, the first contact hole 42 is filled with a conductive film made of polycrystalline silicon to form a first contact plug 43.

Subsequently, although not shown in the drawing, a second interlayer insulating film (not shown) is formed on the first interlayer insulating film 41 including the first contact plug 43, and then the second interlayer insulating film is selectively formed. Etching is connected to the first contact plug 43 to form a second contact hole (not shown) shifted by a predetermined distance in one direction of the first contact plug 43. Thereafter, the second contact hole is filled with a conductive film made of polycrystalline silicon to form a second contact plug (not shown).                     

Here, the forming of the second contact plug shifted by a predetermined distance in one direction of the first contact plug 43 on the first contact plug 43 may be achieved by implementing an arrangement of capacitors in a zigzag type. In order to maximize the area occupied by the capacitor on the layout, the memory cell area is gradually decreasing.

Next, an etch stop layer 44 and a first oxide layer 45 having a third contact hole 46 exposing the second contact plug are sequentially formed on the second interlayer insulating layer including the second contact plug. do. In this case, the etch stop layer 44 is formed to a thickness of 100 ~ 2000Å by using a nitride film, and the etch stop layer 44 and the first oxide layer 45 is formed to a thickness of 6000 ~ 30000Å. In addition, the first oxide layer 45 may be formed as a single layer or may be formed as a multilayer using a chemical vapor deposition (CVD) method.

Subsequently, as shown in FIG. 4B, a barrier metal film (not shown) is formed on the entire surface of the substrate including the contact hole 46 structure, and then an annealing process is performed on the resultant surface of the second contact plug. After the silicide layer 47 is formed, the unreacted barrier metal film in the annealing process is removed by wet etching. Here, any one of Ti, Co and Zr is used as the barrier metal film. In this case, the silicide layer 47 serves to lower the contact resistance between the second contact plug and the storage node electrode to be formed later.

Subsequently, the TiN film 48 for storage node electrodes 48 and the polysilicon film 49 are sequentially formed on the resulting structure. Here, the TiN film 48 for the storage node electrode is formed to have a thickness of 50 to 1000 mm by using any one of CVD and ALD (atomic layer deposition), and the polysilicon film 49 is 300 to 600 It is formed to a thickness of 50 ~ 3000Å at a temperature of ℃.

On the other hand, in relation to the TiN film 48 growing in a columnar structure due to its crystal characteristics, when the TiN film 48 is formed, there is a gap (not shown) at the grain boundaries of a portion where the crystal growth is weak. Is generated. In this case, the polysilicon film 49 has a property of not being etched by the chemical solution used in the dip out process of the first and second oxide films to be performed later. Accordingly, the polysilicon film 49 may include the second and first interlayer insulating films 41 through gaps in which a chemical solution used in a subsequent dip-out process occurs in a region in which crystal growth of the TiN film 48 is weak. ) To effectively block the penetration.

Thereafter, a second oxide film 50 is formed on the polysilicon film 49 to fill the entire structure of the third contact hole 46.

Next, as shown in FIG. 4C, the second oxide film, the polycrystalline silicon film, and the TiN film are etched to form a cylindrical storage node electrode 48a until the first oxide film is exposed. The etching process of the second oxide film, the polysilicon film, and the TiN film may be performed by one of etch back and chemical mechanical polishing (CMP).

Thereafter, the remaining first and second oxide layers are wet-etched by using the remaining polysilicon layer 49a as an etching barrier to protect the storage node electrode 48a formed of the TiN layer. . Here, each of the wet processes of the first and second oxide films is subjected to a dip-out process for 10 to 3600 seconds at a temperature of 4 to 80 ° C. using a HF-based chemical solution.

In this case, the remaining polysilicon film 49a penetrates into the second and first interlayer insulating films 41 through gaps generated in the weak portion of crystal growth of the TiN film. Block it. As a result, since the second and first interlayer insulating films 41 are not etched by the chemical solution, the bunker-shaped circular defects generated in the conventional interlayer insulating films are not generated.

Then, as shown in FIG. 4D, the remaining polysilicon film is removed by wet etching. Here, the wet etching process of the remaining polysilicon film, using a solution of the wet etching rate of the TiN film and the polycrystalline silicon film, the nitride film and the polycrystalline silicon film of 1:10 or more as an etching solution, respectively, wherein the etching solution is in the TiN film Proceed as short as you can not pass through the gap.

In other words, as the etching solution, a TiN film constituting the storage node electrode 48a and a nitride film constituting the etch stop layer 44 are not attacked and a solution which removes only the polysilicon film is used. do. For example, the wet etching process of the remaining polysilicon film may be performed using a mixed solution of NH ₄ OH and H ₂ O and a mixed solution of HF and HNO ₃ as an etching solution at a temperature of 4 to 100 ° C. Run for 3600 seconds.

In this case, as the mixed solution of NH ₄ OH and H ₂ O, a solution in which NH ₄ OH and H ₂ O are mixed in a composition ratio of 10: 1 to a volume ratio of 1: 500 is used. Further, a mixed solution of HF and HNO ₃ is, HF and HNO ₃ 20: Using the mixed solution in a volume ratio of 100: 1 to a solution mixed at a ratio of 1.

When the wet etching process of the remaining polysilicon film is performed under such a condition, the second and first interlayer insulating films 41 under the storage node electrode 48a may be prevented from being etched by the etching solution.

After that, the dielectric film 51 and the plate-node electrode conductive film 52 are sequentially formed on the entire structure. Here, the dielectric film 51 may be any one of TaON, Ta ₂ O ₅ , TiO ₂ , Al ₂ O ₃ , HfO ₂ , HfN, SrTiO ₃ , (Ba, Sr) TiO _3, and (Pb, Sr) TiO ₃ . Using the above film is formed to a thickness of 50 ~ 400Å, it is formed by any one of metal organic chemical vapor deposition method and ALD.

In addition, the conductive film 52 for the plate node electrode is formed to a thickness of 500 ~ 3000Å using any one of the TiN, Ru, and polycrystalline silicon film, by any one of sputtering, CVD and ALD method Form.

As described above, the present invention forms a polysilicon film on the TiN film for the storage node electrode, the interlayer below the TiN film through a gap in which a chemical solution may exist in the TiN film during the dip-out process for removing the oxide film. After preventing penetration into the insulating film, the polysilicon film is selectively wet etched and removed.                     

That is, the present invention can prevent the interlayer insulating film formed under the TiN film storage node electrode from being etched by the chemical solution during the dip-out process, thereby improving the yield of the device.

Claims (16)

Providing a semiconductor substrate having a contact plug made of polycrystalline silicon; Sequentially forming an etch stop layer and a first oxide layer having a contact hole exposing the contact plug on the substrate; Selectively forming a silicide layer on a surface of the exposed contact plug; Sequentially forming a TiN film for a storage node electrode and a polysilicon film over the resulting structure; Forming a second oxide film on the polysilicon film to fill the entire second contact hole structure; Etching the second oxide film, the polycrystalline silicon film, and the TiN film until the first oxide film is exposed; Removing the remaining first and second oxide films by wet etching while protecting the TiN film by using the remaining polysilicon film as an etching barrier; Removing the remaining polysilicon layer by wet etching to form a storage node electrode; And And sequentially forming a dielectric film and a conductive film for plate node electrodes on the entire structure of the resultant structure. The method of claim 1, wherein the etch stop layer is formed to have a thickness of about 100 to about 2000 microns using a nitride film. The method of claim 1, wherein the first oxide layer is formed of one of a single layer and a multiple layer of CVD. The method of claim 1, wherein the etch stop layer and the first oxide layer are formed to a thickness of 6000 ~ 30000Å. The method of claim 1, wherein forming the silicide layer, Forming a barrier metal film on an entire surface of the substrate including the contact hole structure; Performing an annealing process on the resultant to form a silicide layer on the surface of the contact plug; And And removing the unreacted barrier metal film by wet etching in the annealing process. 6. The method of claim 5, wherein any one of Ti, Co, and Zr is used as the barrier metal film. 2. The method of claim 1, wherein the TiN film is formed to a thickness of 50 to 1000 microseconds by using any one of CVD and ALD. The method of claim 1, wherein the polysilicon film is formed at a thickness of 50 to 3000 Pa at a temperature of 300 to 600 ° C. The method of claim 1, wherein the removing of the remaining first and second oxide layers by wet etching comprises performing a dip out process for 10 to 3600 seconds at a temperature of 4 to 80 ° C using a HF-based chemical solution. A method for forming a capacitor of a semiconductor device, characterized in that. The method of claim 1, wherein the removing of the remaining polysilicon film by wet etching is performed using any one of a mixed solution of NH ₄ OH and H ₂ O and a mixed solution of HF and HNO ₃ as an etching solution. Capacitor forming method of a semiconductor device, characterized in that carried out for 5 to 3600 seconds at a temperature of 100 ℃. 11. The method of claim 10, is a mixed solution of NH ₄ OH and H ₂ O, NH ₄ OH and H ₂ O of 10: to take advantage of the solution mixed at a weight ratio of 500: a solution to 1 mixed in a composition ratio of 1 A method of forming a capacitor of a semiconductor device, characterized in that. 11. The method of claim 10, with the HF and HNO ₃ mixed solution, HF and HNO ₃ 20: a semiconductor device characterized by using a solution mixed at a weight ratio of 100: a solution to 1 mixed in a composition ratio of 1 Capacitor Formation Method. The method of claim 1, wherein the dielectric film is any one of TaON, Ta ₂ O ₅ , TiO ₂ , Al ₂ O ₃ , HfO ₂ , HfN, SrTiO ₃ , (Ba, Sr) TiO ₃ and (Pb, Sr) TiO ₃ A capacitor forming method for a semiconductor device, which is formed to a thickness of 50 to 400 GPa using the above film. The method of claim 1, wherein the dielectric layer is formed by any one of metal organic chemical vapor deposition and ALD. 2. The method of claim 1, wherein the conductive film for plate node electrodes is formed to a thickness of 500 to 3000 kW using any one of a TiN, Ru, and polycrystalline silicon film. The method of claim 1, wherein the conductive film for plate node electrodes is formed by any one of sputtering, CVD, and ALD.

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