KR20050081758A - Cell block pattern of active recess channel transistor - Google Patents
Cell block pattern of active recess channel transistor Download PDFInfo
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- KR20050081758A KR20050081758A KR1020040010132A KR20040010132A KR20050081758A KR 20050081758 A KR20050081758 A KR 20050081758A KR 1020040010132 A KR1020040010132 A KR 1020040010132A KR 20040010132 A KR20040010132 A KR 20040010132A KR 20050081758 A KR20050081758 A KR 20050081758A
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- 239000000758 substrate Substances 0.000 claims abstract description 14
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 4
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 4
- 239000010703 silicon Substances 0.000 claims abstract description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 13
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 abstract description 11
- 229910021342 tungsten silicide Inorganic materials 0.000 abstract description 11
- 238000000151 deposition Methods 0.000 abstract description 7
- 230000007547 defect Effects 0.000 abstract description 5
- 238000003776 cleavage reaction Methods 0.000 abstract description 4
- 230000007017 scission Effects 0.000 abstract description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 20
- 229920005591 polysilicon Polymers 0.000 description 11
- 238000000034 method Methods 0.000 description 9
- 230000008021 deposition Effects 0.000 description 4
- 230000007423 decrease Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 230000003287 optical effect Effects 0.000 description 2
- BPQQTUXANYXVAA-UHFFFAOYSA-N Orthosilicate Chemical compound [O-][Si]([O-])([O-])[O-] BPQQTUXANYXVAA-UHFFFAOYSA-N 0.000 description 1
- PBZHKWVYRQRZQC-UHFFFAOYSA-N [Si+4].[O-][N+]([O-])=O.[O-][N+]([O-])=O.[O-][N+]([O-])=O.[O-][N+]([O-])=O Chemical compound [Si+4].[O-][N+]([O-])=O.[O-][N+]([O-])=O.[O-][N+]([O-])=O.[O-][N+]([O-])=O PBZHKWVYRQRZQC-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 238000005336 cracking Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 230000001678 irradiating effect Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
- H01L21/0274—Photolithographic processes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
- H01L21/76205—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
- H01L29/66333—Vertical insulated gate bipolar transistors
- H01L29/66348—Vertical insulated gate bipolar transistors with a recessed gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
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- General Physics & Mathematics (AREA)
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- Electrodes Of Semiconductors (AREA)
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Abstract
본 발명은 활성 리세스(recess) 채널 트랜지스터의 셀 블록 패턴에 관한 것으로, 실리콘 기판에 형성되는 바(bar) 형태로 배열된 다수개의 주 게이트(gate) 패턴들과, 상기 주 게이트 패턴들의 최외각에 다수의 슬릿에 의해 분할된 분할 더미 게이트 패턴들을 포함하는 더미 게이트 패턴으로 구성된 활성 리세스 채널 트랜지스터의 셀 블록 패턴을 제공하는 것이다. 이에 따르면, 더미 게이트 패턴의 리세스에 폴리실리콘(poly-Si)을 증착할 때 갭-필 (gap-fill) 능력이 향상되고, 나아가 더미 게이트 패턴에서의 게이트 텅스텐규화물(WSix) 쪼개짐 결함(fail)을 개선할 수 있다.The present invention relates to a cell block pattern of an active recess channel transistor, and includes a plurality of main gate patterns arranged in a bar shape formed on a silicon substrate, and an outermost portion of the main gate patterns. A cell block pattern of an active recess channel transistor including a dummy gate pattern including divided dummy gate patterns divided by a plurality of slits is provided. This improves the gap-fill capability when depositing poly-Si in the recesses of the dummy gate pattern, and furthermore, gate tungsten silicide (WSix) cleavage defects in the dummy gate pattern. ) Can be improved.
Description
본 발명은 활성 리세스(recess) 채널 트랜지스터의 셀 블록 패턴에 관한 것으로, 특히 다수의 슬릿(slit)에 의해 분할된 분할 더미 게이트 패턴들을 포함하는 더미 게이트(gate) 패턴을 갖는 활성 리세스 채널 트랜지스터의 셀 블록 패턴에 관한 것이다.The present invention relates to a cell block pattern of an active recess channel transistor, and more particularly to an active recess channel transistor having a dummy gate pattern including divided dummy gate patterns divided by a plurality of slits. It relates to a cell block pattern of.
반도체 장치의 고집적화로 인하여 하나의 칩에서 단위 셀이 차지하는 단위 면적이 아주 작은 미세 회로를 필요로 하게 되었다. 그리고 이러한 미세 회로에서 트랜지스터의 게이트 길이가 감소될 때 채널길이도 감소하므로, 유효채널길이를 충분히 증가시키기 위하여 게이트를 리세스한 트랜지스터 구조가 많이 연구되고 있다. Due to the high integration of semiconductor devices, a microcircuit having a very small unit area occupied by a single cell in a chip is required. In this microcircuit, since the channel length decreases when the gate length of the transistor decreases, many transistor structures having recessed the gate in order to sufficiently increase the effective channel length have been studied.
그러나 게이트를 형성하기 위하여 단위 셀 게이트의 연속형태로 사진공정을 수행하여 기판위의 포토레지스트 막에 패턴을 형성하고, 기판을 식각하여 리세스를 형성한 후, 기판에 폴리실리콘(poly-Si)과 텅스텐규화물(WSix)을 증착 할 때, 리세스 구조에 따른 갭-필(gap-fill)능력의 저하로 게이트 패턴의 텅스텐규화물이 쪼개지는 결함(fail)이 발생하고 있으며, 이러한 결함은 오픈 치수가 오픈 임계치수 (Critical Dimension; CD)보다 커지는 단위 셀 게이트의 연속형태인 셀 블록 패턴의 최외각 더미 게이트 패턴에서 더욱 심하게 발생하고 있다.However, in order to form a gate, a photolithography process is performed in a continuous form of a unit cell gate to form a pattern on the photoresist film on the substrate, and the substrate is etched to form a recess, followed by polysilicon (poly-Si) on the substrate. When depositing and tungsten silicide (WSix), the gap of the tungsten silicide in the gate pattern is broken due to the decrease of the gap-fill ability according to the recess structure. Is more severely generated in the outermost dummy gate pattern of the cell block pattern, which is a continuous form of the unit cell gate that is larger than the open critical dimension (CD).
이하 종래기술에 있어서, 오픈 치수가 큰 최외각 더미 게이트 패턴에서의 게이트 텅스텐규화물 쪼개짐 현상에 관하여 도면을 참조하여 설명한다.In the prior art, the gate tungsten silicide cleavage phenomenon in the outermost dummy gate pattern with a large open dimension will be described with reference to the drawings.
단, 이하 설명에서 종래기술의 셀 블록 패턴의 평면도와 셀 블록 패턴을 형성하기 위한 포토레지스트 막 패턴의 평면도는 동일하므로, 셀 블록 패턴의 평면도는 생략한다.However, in the following description, the plan view of the cell block pattern of the prior art and the photoresist film pattern for forming the cell block pattern are the same, and thus the plan view of the cell block pattern is omitted.
도 1은 종래기술에 따른 셀 블록 패턴을 형성하기 위한 포토레지스트 막 패턴을 나타낸 평면도이며, 도 2는 종래기술에 따른 셀 블록 패턴의 더미 게이트 패턴을 나타낸 부분절개도이다.1 is a plan view illustrating a photoresist film pattern for forming a cell block pattern according to the prior art, and FIG. 2 is a partial cutaway view illustrating a dummy gate pattern of the cell block pattern according to the prior art.
도 1 및 도 2를 참조하면, 실리콘 기판(20)에 활성 리세스 채널 트랜지스터의 미세한 셀 블록 패턴을 형성하기 위하여 기판(20) 위에 포토레지스트 막(10a)을 도포 한다. 그리고 포토레지스트 막(10a)을 셀 블록 패턴에 따라 패터닝하기 위하여 노광한다. 1 and 2, a photoresist film 10a is coated on the substrate 20 to form a fine cell block pattern of the active recess channel transistor on the silicon substrate 20. The photoresist film 10a is exposed for patterning according to the cell block pattern.
이때 셀 블록 패턴은 바 형태로 배열된 다수개의 주 게이트 패턴(도시되어 있지 않음)들과 주 게이트 패턴들의 최외각에 바 형태의 더미 게이트 패턴(26)을 포함하므로 노광되는 포토레지스트 막(10a) 역시, 바 형태의 주 게이트 패턴들에 대응하여 형성된, 바 형태의 주 패턴(12a)들과 그 주 패턴(12a)들의 최외각에, 바 형태의 더미 게이트 패턴 (26)에 대응하여 형성된, 바 형태의 더미 패턴(11a)을 포함한다.In this case, the cell block pattern includes a plurality of main gate patterns (not shown) arranged in a bar shape and a dummy gate pattern 26 in a bar shape at an outermost portion of the main gate patterns, thereby exposing the photoresist film 10a. Also formed in correspondence with the bar-shaped dummy gate pattern 26 at the outermost portions of the bar-shaped main patterns 12a and the main patterns 12a, which are formed corresponding to the bar-shaped main gate patterns. It includes a dummy pattern (11a) of the form.
그러나 더미 패턴(11a)은 노광시 포토레지스트 막 패턴의 기준점으로서, 더욱 명확히 보여질 수 있게 하기 위하여 주 패턴(12a)들에 비하여 상대적으로 큰 폭으로 형성되며, 나아가 마스크 또는 레티클(reticle)(도시되어 있지 않음)을 통하여 광이 포토레지스트 막(10a)위에 조사되어 패턴이 형성되는 과정에서 광학렌즈를 통한 초점조정 등의 어려움으로 인하여 더욱 큰 폭으로 된다. However, the dummy pattern 11a is a reference point of the photoresist film pattern at the time of exposure, and is formed in a relatively larger width than the main patterns 12a in order to be more clearly seen, and furthermore, a mask or a reticle (shown in FIG. Light is irradiated onto the photoresist film 10a and becomes wider due to difficulty such as focusing through an optical lens in the process of forming a pattern.
다음으로, 형성된 주 패턴(12a)들과 더욱 큰 폭의 더미 패턴(11a)에 대하여 현상공정을 수행하고, 현상된 주 패턴(12a)과 더미 패턴(11a)에 따라 기판(20)을 식각하여 셀 활성의 리세스(21)를 형성한다.Next, a developing process is performed on the formed main patterns 12a and the larger dummy pattern 11a, and the substrate 20 is etched according to the developed main patterns 12a and the dummy pattern 11a. A recess 21 of cell activity is formed.
이때 더미 게이트 패턴(26)의 리세스(21) 오픈 치수(22)는 더욱 큰 폭의 더미 패턴(11a)에 의해 오픈 임계치수(Critical Dimension ;CD)보다 커지게 된다.At this time, the opening 21 of the recess 21 of the dummy gate pattern 26 is larger than the open critical dimension CD by the larger dummy pattern 11a.
후속공정으로 포토레지스트 막(10a)을 제거하고, 기판(20)위에 폴리실리콘 (23)을 증착한다.In a subsequent process, the photoresist film 10a is removed, and polysilicon 23 is deposited on the substrate 20.
또한 증착된 폴리실리콘(23)위에 동일한 프로파일(Profile)을 따라서 텅스텐규화물(24)을 증착하여 셀 블록 패턴을 형성한다. In addition, the tungsten silicide 24 is deposited on the deposited polysilicon 23 along the same profile to form a cell block pattern.
이때 훨씬 큰 오픈 치수(22)를 가지는 더미 게이트 패턴(26)의 리세스(21)에 폴리실리콘(23)을 증착하면 사이드 스텝 커버리지(side step coverage)에 의한 갭-필 능력이 저하된다. 그러므로 증착된 폴리실리콘(23)층에서의 그루브(25a)의 각도 (도 2의 θ)와 깊이(도 2의 d)가 커지고, 아울러 텅스텐규화물(24)층에서의 증착 그루브(25b)의 각도와 깊이 역시 커지게 된다. 따라서 후속공정으로 텅스텐규화물 (24)층위에 질산실리콘(도시되어 있지 않음)을 증착하고, 마스크를 정렬하여 노광한 후 게이트 패턴들을 식각하고, 열 공정을 수행 할 때 더미 게이트 패턴(26)의 텅스텐규화물(24) 쪼개짐 결함이 발생 될 수 있다.At this time, depositing polysilicon 23 in the recess 21 of the dummy gate pattern 26 having a much larger open dimension 22 lowers the gap-fill capability due to side step coverage. Therefore, the angle (θ in FIG. 2) and the depth (d in FIG. 2) of the groove 25a in the deposited polysilicon 23 layer are increased, and the angle of the deposition groove 25b in the tungsten silicide 24 layer is therefore increased. And depth also increase. Therefore, in the subsequent process, silicon nitrate (not shown) is deposited on the tungsten silicide 24 layer, the masks are aligned and exposed, the gate patterns are etched, and the tungsten of the dummy gate pattern 26 is subjected to a thermal process. Silicate 24 cleavage defects may occur.
더욱이 발생된 텅스텐규화물(24) 쪼개짐 결함으로 더미 게이트 패턴(26)의 폴리실리콘(23)의 반쪽이 옆으로 쓰러지거나 기울 경우 자기정렬 컨택(Self Align Contact; SAC) 오픈시 숄더(shoulder)가 약해져서 더미 게이트 패턴(26)의 폴리실리콘(23)으로부터 자기정렬 컨택으로의 단락을 유발하거나, 심한 경우 자기정렬 컨택 오픈시 식각을 멈추게 하여 자기정렬 컨택이 오픈되지 않게 할 수도 있다. 따라서 하드-결함(hard-fail)의 증가로 심각한 수율 감소 및 공정 스텝의 증가 등의 장애요인이 된다.Furthermore, if the half of the polysilicon 23 of the dummy gate pattern 26 falls sideways or tilts due to the generated tungsten silicide 24 cracking defect, the shoulder becomes weak when the self alignment contact (SAC) is opened. The self-aligned contact may not be opened by causing a short circuit from the polysilicon 23 of the gate pattern 26 to the self-aligned contact or, in severe cases, stopping the etching upon opening the self-aligned contact. Therefore, the increase in hard-fails is a barrier to serious yield reduction and increase of process steps.
따라서 본 발명의 목적은, 셀 블록 패턴의 최외각 더미 게이트 패턴에서 폴리실리콘 증착에 의한 그루브의 발생을 억제하고, 이에 따라 더미 게이트 패턴에서의 결정화된 텅스텐규화물이 쪼개지는 결함을 개선하는데 있다.Accordingly, an object of the present invention is to suppress the occurrence of grooves due to polysilicon deposition in the outermost dummy gate pattern of the cell block pattern, thereby improving the defect that the crystallized tungsten silicide splits in the dummy gate pattern.
상기 목적을 달성하기 위하여 본 발명은, 바 형태로 배열된 다수개의 주 게이트 패턴들과 주 게이트 패턴들의 최외각에 다수의 슬릿에 의해 분할된 분할 더미 게이트 패턴들을 포함하는 더미 게이트 패턴을 갖는 활성 리세스 채널 트랜지스터의 셀 블록 패턴을 형성하는 것을 특징으로 한다.In order to achieve the above object, the present invention provides an active logic having a plurality of main gate patterns arranged in a bar shape and a dummy gate pattern including divided dummy gate patterns divided by a plurality of slits at the outermost portions of the main gate patterns. A cell block pattern of the set channel transistor is formed.
이하 첨부 도면을 참조하여 본 발명을 보다 상세하게 설명하고자 한다. Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings.
단, 이하 설명에서 본 발명의 셀 블록 패턴의 평면도와 셀 블록 패턴을 형성하기 위한 포토레지스트 막 패턴의 평면도는 동일하므로, 셀 블록 패턴의 평면도는 생략한다.However, in the following description, the plan view of the cell block pattern of the present invention and the photoresist film pattern for forming the cell block pattern are the same, and thus the plan view of the cell block pattern is omitted.
도 3은 본 발명에 따른 셀 블록 패턴을 형성하기 위한 포토레지스트 막의 패턴을 나타낸 평면도이다. 3 is a plan view showing a pattern of a photoresist film for forming a cell block pattern according to the present invention.
도 3을 참조하면, 셀 블록 패턴을 형성하기 위한 포토레지스트 막(10b)의 패턴 역시 바 형태로 배열된 다수개의 주 게이트 패턴들과 대응하여 형성된 주 패턴 (12b)들과, 주 패턴(12b)의 최외각에 다수의 슬릿에 의해 분할된 분할 더미 게이트 패턴을 포함하는 더미 게이트 패턴(36)에 대응하여 형성된 더미 패턴(11b)으로 형성된다.Referring to FIG. 3, the patterns of the photoresist film 10b for forming the cell block pattern also include the main patterns 12b formed corresponding to the plurality of main gate patterns arranged in a bar shape, and the main pattern 12b. The dummy pattern 11b is formed to correspond to the dummy gate pattern 36 including the divided dummy gate pattern divided by the plurality of slits at the outermost part of the substrate.
여기서, 분할 더미 패턴은 원형, 타원형 또는 사각형 중 하나의 형태를 갖는다.Here, the divided dummy pattern has a form of one of a circle, an oval or a rectangle.
또한 이하 설명의 편의를 위하여 분할 더미 패턴은 원형으로 형성한 예를 개시하였다.In addition, for the convenience of the following description, an example in which the split dummy pattern is formed in a circular shape is disclosed.
도 4는 본 발명에 따른 셀 블록 패턴의 더미 게이트 패턴을 나타낸 부분절개도이다. 4 is a partial cutaway view illustrating a dummy gate pattern of a cell block pattern according to the present invention.
도 3 및 도 4를 참조하면, 실리콘 기판(30)에 활성 리세스 채널 트랜지스터의 미세한 셀 블록 패턴을 형성하기 위하여 기판(30)위에 포토레지스트 막(10b)을 도포 한다. 그리고 포토레지스트 막(10b)을 셀 블록 패턴에 따라 패터닝하기 위하여 노광한다. 3 and 4, a photoresist film 10b is coated on the substrate 30 to form a fine cell block pattern of the active recess channel transistor on the silicon substrate 30. The photoresist film 10b is then exposed to pattern in accordance with the cell block pattern.
이때 분할 더미 패턴은 원형으로 되어있으므로 마스크 또는 레티클과 광학렌즈(도시되어 있지 않음)를 통하여 광을 조사하는 과정에서 바 형태보다 초점조정 등에서 유리하다. 따라서 더미 패턴(11b)을 형성할 때 더미 패턴 (11b)이 커지는 것을 방지할 수 있으므로, 종래기술보다 리세스(32)의 오픈 치수 (32)가 커지는 것을 감소시킬 수 있다.At this time, since the divided dummy pattern is circular, it is advantageous in focusing and the like in the process of irradiating light through a mask or a reticle and an optical lens (not shown). Therefore, since the dummy pattern 11b can be prevented from growing when the dummy pattern 11b is formed, it is possible to reduce the increase in the open dimension 32 of the recess 32 than in the prior art.
나아가 후속공정으로 노광된 포토레지스트 막(10b)의 패턴을 현상하고, 현상된 포토레지스트 막(10b)의 패턴에 따라 기판(30)을 식각하여 리세스(31)를 형성한다. 그 후 포토레지스트 막(10b)을 제거하고 기판(30)위에 폴리실리콘(33)을 증착 할 때, 더미 게이트 패턴(36)의 원기둥 형태의 리세스(31)에서는 원둘레의 내측 표면을 따라 증착이 이루어지므로 증착시 낮은 가스압력과 높은 이온 에너지를 이용하는 갭-필링에서 사이드 스텝 커버리지의 갭-필 부족을 보상하여, 종래 바 형태 더미 게이트 패턴(도 2의 26)에 의한 리세스(도 2의 21)에서보다 폴리실리콘(33) 증착시의 갭-필 능력이 향상되고 폴리실리콘(33)층에서의 그루브(35a)는 더미 게이트 패턴(36)의 중앙부분에서만 발생된다.Further, the pattern of the exposed photoresist film 10b is developed in a subsequent process, and the recess 30 is formed by etching the substrate 30 according to the developed pattern of the photoresist film 10b. Thereafter, when the photoresist film 10b is removed and the polysilicon 33 is deposited on the substrate 30, the cylindrical recesses 31 of the dummy gate pattern 36 deposit along the inner surface of the circumference. As a result, the gap-fill lack of side step coverage is compensated for in the gap-filling using low gas pressure and high ion energy during deposition, so that the recess by the conventional bar-shaped dummy gate pattern (26 in FIG. 2) (21 in FIG. The gap-fill capability at the time of polysilicon 33 deposition is improved, and the groove 35a in the polysilicon 33 layer is generated only at the center portion of the dummy gate pattern 36.
따라서 후속의 동일한 프로파일을 따라 증착된 텅스텐규화물(34)의 그루브 (35b) 역시 더미 게이트 패턴(36)의 중앙부분에서만 나타나며, 전체적으로는 더미 게이트 패턴(36)에서의 그루브(35b)를 국부적으로 발생하도록 제한할 수 있다.Thus, the groove 35b of the tungsten silicide 34 subsequently deposited along the same profile also appears only at the center portion of the dummy gate pattern 36 and overall generates the groove 35b in the dummy gate pattern 36. Can be restricted.
본 발명에 의하면, 활성 리세스 채널 트랜지스터 셀 블록 더미 게이트 패턴에서의 그루브를 국부적으로 발생하도록 제한하여, 게이트의 텅스텐규화물 쪼개짐 결함을 개선함에 따라 수율을 증가시키고 신뢰성 및 품질을 개선하는 이점(利點)이 있다.Advantageous Effects of Invention According to the present invention, there is an advantage in that the grooves in the active recess channel transistor cell block dummy gate pattern are restricted to occur locally, thereby increasing yield and improving reliability and quality by improving tungsten silicide cleavage defects in the gate. There is.
도 1은 종래기술에 따른 셀 블록 패턴을 형성하기 위한 포토레지스트 막 패턴을 나타낸 평면도.1 is a plan view showing a photoresist film pattern for forming a cell block pattern according to the prior art.
도 2는 종래기술에 따른 셀 블록 패턴의 더미 게이트 패턴을 나타낸 부분절개도.2 is a partial cutaway view showing a dummy gate pattern of a cell block pattern according to the prior art.
도 3은 본 발명에 따른 셀 블록 패턴을 형성하기 위한 포토레지스트 막 패턴을 나타낸 평면도.3 is a plan view showing a photoresist film pattern for forming a cell block pattern according to the present invention.
도 4는 본 발명에 따른 셀 블록 패턴의 더미 게이트 패턴을 나타낸 부분절개도4 is a partial cutaway view illustrating a dummy gate pattern of a cell block pattern according to the present invention.
* 도면의 주요부분에 대한 부호설명 ** Explanation of Signs of Major Parts of Drawings *
10a,10b:포토레지스트 막 11a,11b:더미 패턴10a and 10b photoresist films 11a and 11b dummy patterns
21,31:리세스 22,32:오픈 치수21, 31: recess 22, 32: open dimension
25a,25b,35a,35b:그루브 26,36:더미 게이트 패턴25a, 25b, 35a, 35b: groove 26,36: dummy gate pattern
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100650626B1 (en) * | 2005-11-15 | 2006-11-27 | 삼성전자주식회사 | Semiconductor device and method of manufacturing the same |
| KR100732771B1 (en) * | 2006-03-14 | 2007-06-27 | 주식회사 하이닉스반도체 | Method for preventing gate line leaning |
| KR100811415B1 (en) * | 2007-01-12 | 2008-03-07 | 주식회사 하이닉스반도체 | Method for manufacturing semiconductor device |
| KR100843886B1 (en) * | 2007-01-09 | 2008-07-03 | 주식회사 하이닉스반도체 | Semiconductor device and method for fabricating the same |
| US8049274B2 (en) | 2007-09-03 | 2011-11-01 | Samsung Electronics Co., Ltd. | Semiconductor integrated circuit and method of manufacturing the same |
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2004
- 2004-02-16 KR KR1020040010132A patent/KR20050081758A/en not_active Application Discontinuation
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100650626B1 (en) * | 2005-11-15 | 2006-11-27 | 삼성전자주식회사 | Semiconductor device and method of manufacturing the same |
| KR100732771B1 (en) * | 2006-03-14 | 2007-06-27 | 주식회사 하이닉스반도체 | Method for preventing gate line leaning |
| KR100843886B1 (en) * | 2007-01-09 | 2008-07-03 | 주식회사 하이닉스반도체 | Semiconductor device and method for fabricating the same |
| KR100811415B1 (en) * | 2007-01-12 | 2008-03-07 | 주식회사 하이닉스반도체 | Method for manufacturing semiconductor device |
| US8049274B2 (en) | 2007-09-03 | 2011-11-01 | Samsung Electronics Co., Ltd. | Semiconductor integrated circuit and method of manufacturing the same |
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