KR20040076300A - Method of forming a metal wiring in a semiconductor device - Google Patents

Abstract

PURPOSE: A method for forming a metal line of a semiconductor device is provided to reduce the number of processes and the manufacturing cost by forming simultaneously contact plugs on a source of a source select transistor and a drain of drain select transistor and a contact plug on a peripheral circuit region. CONSTITUTION: A source select transistor(203s), a drain select transistor(203d), and a flash memory cell(203m) are formed on a cell region. A PMOS transistor(203p) and an NMOS transistor(203n) are formed on a peripheral circuit region. The first insulating layer(204) is formed on an entire surface of a semiconductor substrate(201). The first contact holes are formed on a source of the source select transistor(203s) and a source/drain of an NMOS transistor. The first contact plugs(206a,206b) are formed in the first contact holes. The second contact hole is formed on the drain select transistor. The second contact plug is formed in the second contact hole. The third insulating layer(210) is formed on the entire surface of the resultant structure. The third contact hole is formed on a source/drain of the PMOS transistor. A trench is formed on the first and the second contact plugs. A metal line is formed by burying the third contact hole and the trench.

Description

Method of forming a metal wiring in a semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming metal wirings in semiconductor devices, and more particularly, to form flash memory cells in a cell region and semiconductor devices such as transistors in a peripheral circuit region, and then to form electrical wirings. It relates to a method for forming a metal wiring of a semiconductor device that can reduce the step of.

In general, a flash memory device is divided into a cell region and a peripheral circuit region, a flash memory cell is formed in the cell region, and a semiconductor element such as a transistor is formed in the peripheral circuit region. After devices such as flash memory cells and transistors are formed on a semiconductor substrate, contact plugs (or vias) are electrically connected to a junction formed on the semiconductor substrate below the insulating layer to form an insulating layer over the whole to electrically connect them. Plugs) and metal wiring.

1A to 1D are cross-sectional views of devices for describing a method for forming metal wirings of a semiconductor device according to the prior art.

Referring to FIG. 1A, a flash memory cell array includes a NOR type and a NAND type. When manufacturing a NAND type flash memory device, an NMOS transistor 103n and a PMOS are formed in a peripheral circuit region of the semiconductor substrate 101 through a predetermined process. Transistor 103p is formed, and flash memory cell 103m, source select transistor 103s, and drain select transistor 103d are formed in the cell region. Subsequently, the first insulating layer 104 is formed over the entirety.

Unexplained reference numeral 102a is n well, 102b is p well, 102c is triple n well, and 102d is triple p well.

Referring to FIG. 1B, a contact hole is formed by removing the first insulating layer 104 on the source of the source select transistor 103s by an etching process using a source contact mask. Subsequently, an impurity is implanted into the semiconductor substrate 101 exposed through the contact hole by an ion implantation process to form a high concentration of the ion implantation portion 105, and then the contact hole is filled with a conductive material to form the first contact plug 106. ). In this case, the junction ion implantation unit 105 is formed to lower the contact resistance between the source region of the source select transistor 103s, which is a junction of the semiconductor substrate 101, and the first contact plug 106. Meanwhile, the first contact plug 106 may be formed using N + polysilicon as the conductive material.

Referring to FIG. 1C, after the second insulating layer 107 is formed over the whole, the second and first insulating layers 107 and the upper part of the drain of the drain select transistor 103d are formed by an etching process using a drain contact mask. 104 is removed to form a contact hole. Subsequently, impurities are implanted into the semiconductor substrate 101 exposed through the contact hole by an ion implantation process to form a high concentration of the ion implantation unit 108, and then the contact hole is filled with a conductive material to form the first contact plug 109. ). In this case, the junction ion implantation unit 108 is formed to lower the contact resistance between the drain region of the drain select transistor 103d, which is the junction portion of the semiconductor substrate 101, and the second contact plug 109. Similarly, the second contact plug 109 may also be formed using N + polysilicon as the conductive material.

Referring to FIG. 1D, after the third insulating layer 110 is formed over the entirety, the third, second, and first insulating portions on the source / drain tops of the NMOS and PMOS transistors 103n and 103p formed in the peripheral circuit region. The layers 110, 107, and 104 are removed by an etching process to form contact holes. Subsequently, impurities are implanted into the source / drain regions of the NMOS transistor 103n exposed through the contact hole by an ion implantation process to form a high concentration of ion implanted portions 111.

Again, the third, second, and first insulating layers 110, 107, and 104 on the gate lines of the NMOS and PMOS transistors 103n and 103p are removed (not removed) after the etching process. A trench is formed in the third insulating layer 110 in the region where the wiring is to be formed. In this case, in order to prevent the lower second insulating layer 107 from being etched in the process of forming the trench, the third insulating layer 110 is formed. ), An etch stop layer (not shown) may be formed over the second insulating layer 107.

Subsequently, the contact hole and the trench are filled with a conductive material to form a third contact plug 112 in the contact hole at the top of the source / drain, and the metal wiring 113 is formed in the trench. In this case, the junction ion implantation part 111 is formed to lower the contact resistance between the source / drain regions of the PMOS and NMOS transistors 103p and 103n, which are the junctions of the semiconductor substrate 101, and the third contact plug 112. At this time, the Ti film for improving the adhesive properties and the TiN film for the diffusion prevention role are sequentially deposited with a conductive material, and then the trench and the contact hole are filled with tungsten to form the third contact plug 112 and the metal wiring 113. Can be formed. This electrically connects the flash memory cell with the peripheral circuitry. In this case, second and third metal wires may be further formed on the metal wire 113 as needed.

Looking at the above process, the contact hole on the top of the source of the source select transistor 103s, the contact hole on the drain of the drain select transistor 103d, and the source / source of the PMOS and NMOS transistors 103p and 103n in the peripheral circuit region. Contact holes on the drain are formed by different etching processes. In addition, the junction ion implantation portions 105, 108, and 111 must also be formed by different ion implantation processes, respectively. As a result, not only are there many steps in the process, but there is also a difficulty in increasing time and cost by increasing the number of masks.

Accordingly, in order to solve the above problem, the present invention provides a source of a source select transistor in a wiring forming process for forming a flash memory cell in a cell region and forming a semiconductor device such as a transistor in a peripheral circuit region and then electrically connecting them. When forming a contact plug in the upper portion or the drain of the drain select transistor at the same time to form a contact plug of the peripheral circuit region, thereby providing a method for forming a metal wiring of a semiconductor device that can reduce the process step, and the process time and manufacturing cost. The purpose is.

1A to 1D are cross-sectional views of devices for describing a method for forming metal wirings of a semiconductor device according to the prior art.

2A through 2D are cross-sectional views of devices for describing a method for forming metal wires in a semiconductor device according to an embodiment of the present invention.

3A to 3D are cross-sectional views of devices for describing a method for forming metal wires in a semiconductor device according to another embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

101, 201, 301: semiconductor substrates 102a, 202a, 302a: n well

102b, 202b, 302b: p well 102c, 202c, 302c: triple n well

102d, 202d, 302d: Triple p well

103s, 203s, 303s: source select transistor

103m, 203n, 303n: flash memory cell

103d, 203d, 303d: Drain Select Transistors

103p, 203p, 303p: PMOS transistors

103n, 203n, 303n: NMOS transistor

104, 204, 304: first insulating layer

105, 108, 111, 205a, 205b, 208, 305, 308a, 308b: junction ion implantation part

106, 206a, 206b, and 306: first contact plug

107, 207, 307: second insulating layer

109, 209, 309a, 309b: second contact plug

110, 210, 310: third insulating layer 112, 211, 311: third contact plug

113, 212, 312: metal wiring

In the method of forming a metal wiring of a semiconductor device according to an exemplary embodiment of the present invention, a source select transistor, a drain select transistor, and a flash memory cell are formed in a cell region, a PMOS transistor and an NMOS transistor are formed in a peripheral circuit region, and a first upper portion of the semiconductor device is formed. Providing a semiconductor substrate having an insulating layer, forming a contact hole over a source of the source select transistor and a source / drain top of the NMOS transistor, forming a first contact plug in the first contact hole; Forming a second insulating layer over the entirety, forming a second contact hole over the drain of the drain select transistor, forming a second contact plug in the second contact hole, and forming a third over all over Forming an insulating layer and forming a third contact hole on the source / drain of the PMOS transistor by an etching process. The stand of claim comprising the step, and a step of forming a metal wire by embedding the third contact holes and trenches with a conductive material to form a trench with a third insulating layer after the first and the exposed upper surface of the second contact plug.

In the above, after forming the first contact hole and before forming the first contact plug, impurities are implanted by an ion implantation process to simultaneously form a junction ion implantation portion in the source region of the source select transistor and the source / drain region of the NMOS transistor. It may be. In addition, after forming the second contact hole and before forming the second contact plug, impurities may be implanted by an ion implantation process to form a junction ion implantation portion in the drain region of the drain select transistor.

In the method of forming a metal wiring of a semiconductor device according to another embodiment of the present invention, a source select transistor, a drain select transistor, and a flash memory cell are formed in a cell region, a PMOS transistor and an NMOS transistor are formed in a peripheral circuit region, Providing a semiconductor substrate having a first insulating layer, forming a contact hole on a source of a source select transistor, forming a first contact plug in a first contact hole, and a second insulating layer on an entire top of the source select transistor Forming a second contact hole in the drain upper portion of the drain select transistor and the source / drain upper portion of the NMOS transistor; forming a second contact plug in the second contact hole; Forming an insulating layer, and forming a third contact hole on the source / drain of the PMOS transistor by an etching process And it includes a first step, and a step of filling the contact hole 3 and the trench with a conductive material to form a metal line forming the first and second trenches in the third dielectric layer after exposing the upper surface of the second contact plug.

In the above, after forming the first contact hole and before forming the first contact plug, impurities may be implanted by an ion implantation process to form a junction ion implantation portion in the source region of the source select transistor. In addition, after forming the second contact hole and before forming the second contact plug, impurities may be implanted by an ion implantation process to simultaneously form a junction ion implantation portion in the drain region of the drain select transistor and the source / drain region of the NMOS transistor. have.

The first contact plug or the second contact plug may be formed of polysilicon containing impurities of 1E20 to 1E21 atom / cm ² , and the junction ion implantation part may be formed of 1E14 to 5E14 atom / cm with an injection energy of 15keV to 20keV. ² It can be formed by injecting impurities.

Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the present invention. However, the present invention is not limited to the embodiments disclosed below, but may be embodied in various different forms, and only the embodiments are intended to complete the disclosure of the present invention and to those skilled in the art. It is provided for complete information. In the drawings, like reference numerals refer to like elements.

2A through 2D are cross-sectional views of devices for describing a method for forming metal wires in a semiconductor device according to an embodiment of the present invention.

Referring to FIG. 2A, a flash memory cell array includes NOR and NAND types. When manufacturing a NAND flash memory device, an NMOS transistor 203n and a PMOS are formed in a peripheral circuit region of a semiconductor substrate 201 through a predetermined process. The transistor 203p is formed, and a flash memory cell 203m, a source select transistor 203s, and a drain select transistor 203d are formed in a cell region. Subsequently, the first insulating layer 204 is formed over the whole.

Unexplained reference numeral 202a is n well, 202b is p well, 202c is triple n well, and 202d is triple p well.

Referring to FIG. 2B, a contact hole is formed by removing an upper portion of the source of the source select transistor 203s and an upper portion of the source / drain layer of the NMOS transistor 203n formed in the peripheral circuit region by an etching process. do. Subsequently, an impurity is implanted into the semiconductor substrate 201 exposed through the contact hole by an ion implantation process, thereby simultaneously forming high concentration of the ion implantation portions 205a and 205b in the cell region and the peripheral circuit region, and then conducting the contact hole. Buried in material to form first contact plugs 206a and 206b.

In the above, the junction ion implantation portion 205a of the cell region is formed to lower the contact resistance between the source region of the source selection transistor 203s, which is the junction portion of the semiconductor substrate 201, and the first contact plug 206a. The junction ion implantation portion 205b in the peripheral circuit region is formed to lower the contact resistance between the source / drain region of the NMOS transistor 203n, which is the junction portion of the semiconductor substrate 201, and the first contact plug 206b. The junction ion implantation portions 205a and 205b have 1E14 to 5E14 atom / cm with an implantation energy of 15keV to 20keV. ² It can be formed by injecting impurities, and phosphorus (Phosphorus) can be injected into the impurity. Meanwhile, the first contact plugs 206a and 206b may be formed using polysilicon containing impurities of 1E20 to 1E21 atom / cm ² as a conductive material, and may include phosphorus as an impurity.

Referring to FIG. 2C, after the second insulating layer 207 is formed over the entirety, the second and first insulating layers 207 and the upper part of the drain of the drain select transistor 203d are formed by an etching process using a drain contact mask. 204 is removed to form a contact hole. Subsequently, impurities are implanted into the semiconductor substrate 201 exposed through the contact hole by an ion implantation process to form a high concentration of the ion implantation unit 208, and then the contact hole is filled with a conductive material to form the first contact plug 209. ). In this case, the junction ion implantation part 208 is formed to lower the contact resistance between the drain region of the drain select transistor 203d, which is the junction part of the semiconductor substrate 201, and the second contact plug 209. Similarly, the junction ion implantation portion 208 is 1E14 to 5E14 atom / cm with an injection energy of 15keV to 20keV. ² It can be formed by injecting impurities, and phosphorus (Phosphorus) can be injected into the impurity. Meanwhile, the second contact plug 209 may be formed using polysilicon containing impurities of 1E20 to 1E21 atom / cm ² as a conductive material, and may include phosphorus as an impurity.

Referring to FIG. 2D, after the third insulating layer 210 is formed over the entirety, the third, second, and first insulating portions on the source / drain tops of the NMOS and PMOS transistors 203n and 203p formed in the peripheral circuit region. The layers 210, 207, and 204 are removed by an etching process to form contact holes. At this time, the second and third insulating layers 207 and 210 on the first contact plug 206a formed on the source of the source select transistor 203s are also removed. Although not shown in the drawing, NMOS and PMOS transistors are also removed. 203p and 203n, the flash memory cell 203m, the source select transistor 203s, and the third, second and first insulating layers 120, 207, and 204 over the gate line of the drain select transistor 203d together. You can also remove it.

A trench is then formed in the third insulating layer 210 in the region where the metal wiring is to be formed. In this case, in order to prevent the lower second insulating layer 207 from being etched in the process of forming the trench, an etch stop layer (not shown) is formed on the second insulating layer 207 before forming the third insulating layer 210. May not be used).

Subsequently, the contact hole and the trench are filled with a conductive material to form a third contact plug 211 in the upper portion of the source / drain of the NMOS transistor 203n, and the metal wiring 212 is formed in the trench. At this time, the Ti film for improving the adhesive properties and the TiN film for the diffusion prevention role are sequentially deposited with a conductive material, and then the trenches and contact holes are filled with tungsten to form the third contact plug 211 and the metal wiring 212. Can be formed. This electrically connects the flash memory cell with the peripheral circuitry. In this case, second and third metal wires may be further formed on the metal wires 212 as needed.

In the metal wiring forming method, the peripheral circuit is formed when the contact plug is formed on the source of the source select transistor 203s in the cell region, the contact ion implantation portion 205a is formed, and then the contact plug 206a is formed. In the region, a contact hole is formed on the source / drain of the NMOS transistor 203n, the junction ion implantation part 205b is formed, and then the contact plug 206b is formed at the same time. This reduces the steps of the process and saves time and costs. However, when forming a contact hole after forming a contact hole on the source of the drain select transistor 203d in the cell region and forming a junction ion implantation portion, the contact is formed on the source / drain of the NMOS transistor 203n in the peripheral circuit region. The contact plug 206b may be formed at the same time after the hole is formed and the junction ion implantation part 205b is formed. Hereinafter, another embodiment will be described with reference to the drawings.

3A to 3D are cross-sectional views of devices for describing a method for forming metal wirings of a semiconductor device in accordance with another embodiment of the present invention.

Referring to FIG. 3A, the process illustrated in FIG. 3A is the same as the method described with reference to FIG. 2A and will be omitted.

Referring to FIG. 3B, a contact hole is formed by removing the first insulating layer 304 on the source of the source select transistor 303s by an etching process. Subsequently, an impurity is implanted into the semiconductor substrate 301 exposed through the contact hole by an ion implantation process to form a high concentration of the ion implantation unit 305 in the source region of the source select transistor 303s in the cell region. Is embedded with a conductive material to form the first contact plug 306.

In the above, the junction ion implantation portion 305 of the cell region is formed to lower the contact resistance between the source region of the source select transistor 303s, which is the junction portion of the semiconductor substrate 301, and the first contact plug 306. The junction ion implantation unit 305 is 1E14 to 5E14 atom / cm with an injection energy of 15keV to 20keV ² It can be formed by injecting impurities, and phosphorus (Phosphorus) can be injected into the impurity. Meanwhile, the first contact plug 306 may be formed using polysilicon containing impurities of 1E20 to 1E21 atom / cm ² as a conductive material, and may include phosphorus as an impurity.

Referring to FIG. 3C, after the second insulating layer 307 is formed over the entire top, the source and drain portions of the NMOS transistor 303n formed in the drain upper portion of the drain select transistor 303d and the peripheral circuit region are formed by an etching process. The second and first insulating layers 307 and 304 are removed to form contact holes. Subsequently, impurities are implanted into the semiconductor substrate 301 exposed through the contact hole by an ion implantation process, and a high concentration of the impurities is injected into the drain region of the drain select transistor 303d and the source / drain region of the NMOS transistor 303n in the peripheral circuit region. After the junction ion implants 308a and 308b are formed at the same time, the contact holes are filled with a conductive material to form the first contact plugs 309a and 309b at the same time. In this case, the junction ion implantation part 308 is formed to lower the contact resistance between the drain region of the drain select transistor 303d, which is the junction part of the semiconductor substrate 301, and the second contact plug 309. In addition, the junction ion implantation portion 308b in the peripheral circuit region is formed to lower the contact resistance between the source / drain region of the NMOS transistor 303n, which is the junction portion of the semiconductor substrate 301, and the second contact plug 309b. Similarly, the junction ion implants 308a and 308b have 1E14 to 5E14 atom / cm with an implantation energy of 15keV to 20keV. ² It can be formed by injecting impurities, and phosphorus (Phosphorus) can be injected into the impurity. Meanwhile, the second contact plugs 309a and 309b may be formed using polysilicon containing impurities of 1E20 to 1E21 atom / cm ² as a conductive material, and may include phosphorus as an impurity.

Referring to FIG. 3D, after the third insulating layer 310 is formed on the entire upper portion, the third, second, and third portions of the first contact plug 306 and the second contact plugs 309a and 309b are exposed. 1 The insulating layers 310, 307, and 304 are removed by an etching process to form contact holes. Although not shown in the figure, the third, second, and upper portions of the gate lines of the NMOS and PMOS transistors 303p and 303n, the flash memory cell 303m, the source select transistor 303s, and the drain select transistor 303d are not shown. The first insulating layers 310, 307, and 304 may be removed together.

Thereafter, trenches are formed in the third insulating layer 310 in the region where the metal wiring is to be formed. In this case, in order to prevent the lower second insulating layer 307 from being etched in the process of forming the trench, an etch stop layer (not shown) is formed on the second insulating layer 307 before forming the third insulating layer 310. May not be used).

Subsequently, the contact hole and the trench are filled with a conductive material to form a third contact plug 311 at the top of the source / drain of the NMOS transistor 303n, and the metal wiring 312 is formed in the trench. At this time, the Ti film for improving the adhesion properties and the TiN film for the diffusion prevention role are sequentially deposited with a conductive material, and the third contact plug 311 and the metal wiring 312 are filled with the trench and the contact hole by tungsten. Can be formed. This electrically connects the flash memory cell with the peripheral circuitry. In this case, second and third metal wires may be further formed on the metal wires 312 as needed.

The invention is not limited to the specific field herein described with reference to the suitable embodiments, but rather the scope of the invention should be understood by the claims herein.

As described above, the present invention simultaneously forms contact plugs in the peripheral circuit area when forming contact plugs on the source top of the source select transistor or the drain top of the drain select transistor, thereby reducing process steps and reducing processing time and manufacturing cost. You can.

Claims (8)

Providing a semiconductor substrate in which a source select transistor, a drain select transistor, and a flash memory cell are formed in a cell region, a PMOS transistor and an NMOS transistor are formed in a peripheral circuit region, and a first insulating layer is formed on the whole; Forming a contact hole over a source of the source select transistor and a source / drain of the NMOS transistor; Forming a first contact plug in the first contact hole; Forming a second insulating layer over the whole; Forming a second contact hole on the drain of the drain select transistor; Forming a second contact plug in the second contact hole; Forming a third insulating layer over the whole; Exposing a top surface of the first and second contact plugs while forming a third contact hole on a source / drain of the PMOS transistor by an etching process and then forming a trench in the third insulating layer; And And forming a metal wiring by filling the third contact hole and the trench with a conductive material. The method of claim 1, wherein after forming the first contact hole and before forming the first contact plug, And forming a junction ion implantation portion simultaneously in a source region of the source select transistor and a source / drain region of the NMOS transistor by implanting impurities in an ion implantation process. The method of claim 1, wherein after forming the second contact hole and before forming the second contact plug, And implanting impurities in the drain region of the drain select transistor by implanting impurities in an ion implantation process. Providing a semiconductor substrate in which a source select transistor, a drain select transistor, and a flash memory cell are formed in a cell region, a PMOS transistor and an NMOS transistor are formed in a peripheral circuit region, and a first insulating layer is formed on the whole; Forming a contact hole on a source of the source select transistor; Forming a first contact plug in the first contact hole; Forming a second insulating layer over the whole; Forming a second contact hole over the drain of the drain select transistor and the source / drain of the NMOS transistor; Forming a second contact plug in the second contact hole; Forming a third insulating layer over the whole; Exposing a top surface of the first and second contact plugs while forming a third contact hole on a source / drain of the PMOS transistor by an etching process and then forming a trench in the third insulating layer; And And forming a metal wiring by filling the third contact hole and the trench with a conductive material. The method of claim 4, wherein after forming the first contact hole and before forming the first contact plug, And forming a junction ion implantation portion in the source region of the source select transistor by implanting impurities in an ion implantation process. The method of claim 4, wherein after forming the second contact hole and before forming the second contact plug, And implanting impurities in the drain region of the drain select transistor and the source / drain regions of the NMOS transistor simultaneously by implanting impurities in an ion implantation process. The method according to claim 1 or 4, The method of claim 1, wherein the first contact plug or the second contact plug is formed of polysilicon containing impurities of 1E20 to 1E21 atom / cm ² . The method according to claim 2, 3, 5 or 6, The junction ion implantation portion is 1E14 to 5E14 atom / cm with an injection energy of 15keV to 20keV ² And forming impurities by implanting the impurities therein.