KR20030055125A - Thin film transistor array panel and method for manufacturing the panel - Google Patents

Abstract

PURPOSE: A thin film transistor array panel and method for manufacturing the same are provided to reduce effectively the number of masks by forming opening portions at color filters and a contact hole at a protective layer. CONSTITUTION: A TFT LCD includes a plurality of gate lines(22), a gate insulating layer(30), a silicon island(40), a plurality of data lines(62), a drain electrode(66), a plurality of color filters, a protective layer(70), and a pixel electrode(82). The gate line is formed on an insulating substrate. The gate insulating layer is formed on the gate line. The semiconductor is formed on the gate insulating layer. The data line and the drain electrode are formed on the gate insulating layer. The color filters have the first openings and are formed on a pixel region. The protective layer has the first contact hole and is formed on the color filters. The pixel electrode is formed on the protective layer.

Description

Thin film transistor array panel for display device and manufacturing method thereof {THIN FILM TRANSISTOR ARRAY PANEL AND METHOD FOR MANUFACTURING THE PANEL}

The present invention relates to a method of manufacturing the thin film transistor array panel for a display device.

The liquid crystal display is one of the flat panel display devices most widely used at present, and includes two display panels on which a field generating electrode is formed and a liquid crystal layer interposed therebetween. Voltage is applied to both electrodes to generate an electric field in the liquid crystal layer, and the intensity of the electric field is changed to rearrange the liquid crystal molecules of the liquid crystal layer, thereby controlling the transmittance of transmitted light to display an image.

Among the liquid crystal display devices, a liquid crystal display device having a thin film transistor that has electrodes formed on each of two display panels and switches voltage applied to the electrodes is one of the liquid crystal display devices, and one of the two substrates includes a plurality of wirings such as a gate line and a data line. A thin film transistor is formed to remove the pixel electrode and the data signal transmitted to the pixel electrode (hereinafter referred to as a thin film transistor display panel), and the other display panel has a common electrode facing the pixel electrode, and red (R) and green (G). In general, a blue (B) color filter is formed.

Each of these substrates is generally manufactured by a photolithography process using a mask. A substrate on which a thin film transistor is formed is usually manufactured by a photolithography process using five or six masks, and a substrate on which a color filter is formed. Is prepared by a photolithography process using three or four masks.

In order to reduce the production cost of such a liquid crystal display device, it is preferable to reduce the number of masks, and to simplify the manufacturing process.

In addition, in order to improve the luminance of such a liquid crystal display device, it is important to secure a high aperture ratio. To this end, a color filter is formed on the same substrate as the thin film transistor, and a method of improving the aperture ratio by minimizing the process margin between the two substrates has been proposed. In order to form a good profile, an organic insulating film having excellent planarization characteristics is formed.

However, in the method of manufacturing the liquid crystal display device, contact holes must be formed in the color filter and the organic insulating film for connecting the drain electrode and the pixel electrode of the thin film transistor. The color filter and the organic insulating film are both organic films and their thicknesses are increased. Since it is too thick, there is a problem that it is difficult to form a contact hole having a good profile in the etching process, and to solve this problem can be added a photolithography process, but this method is very complicated manufacturing process.

It is an object of the present invention to provide a thin film transistor array panel for a liquid crystal display device and a method of manufacturing the same, which can simplify the manufacturing process.

1 is a layout view of a thin film transistor array panel for a liquid crystal display according to a first exemplary embodiment of the present invention.

FIG. 2 is a cross-sectional view of the thin film transistor array panel illustrated in FIG. 1 taken along the line II-II ′.

3A is a layout view of a thin film transistor array panel in a first step of manufacturing according to the first embodiment of the present invention;

3B is a cross-sectional view taken along line IIIb-IIIb 'of FIG. 3A.

4A is a layout view of a thin film transistor array panel in a second step of manufacturing according to the first embodiment of the present invention;

4B is a cross-sectional view taken along the line IVb-IVb 'of FIG. 4A.

5A is a layout view of a thin film transistor array panel in a third step of manufacturing according to the first embodiment of the present invention;

FIG. 5B is a cross-sectional view taken along the line Vb-Vb ′ of FIG. 5a;

6A is a layout view of a thin film transistor array panel according to a fourth step of manufacturing according to the first embodiment of the present invention;

FIG. 6B is a cross-sectional view taken along line VIb-VIb ′ in FIG. 6A.

7A is a layout view of a thin film transistor array panel in a fifth step of manufacturing according to the first embodiment of the present invention;

FIG. 7B is a cross-sectional view taken along the line VIIb-VIIb 'of FIG. 7A;

8 is a layout view of a thin film transistor array panel for a liquid crystal display according to a second exemplary embodiment of the present invention.

9 and 10 are cross-sectional views of the thin film transistor array panel illustrated in FIG. 8 taken along lines VIII-VIII 'and IX-IX',

11A is a layout view of a thin film transistor array panel in a first step of manufacturing according to an embodiment of the present invention;

11B and 11C are cross-sectional views taken along the lines XIb-XIb 'and XIc-XIc' of FIG. 11A, respectively.

12A and 12B are cross-sectional views taken along the lines XIb-XIb 'and XIc-XIc' of FIG. 11A, respectively, and are cross-sectional views of the next steps of FIGS. 11B and 11C;

FIG. 13A is a layout view of a TFT panel next to FIGS. 12A and 12B;

13B and 13C are cross-sectional views taken along the lines XIIIb-XIIIb 'and XIIIc-XIIIc' of FIG. 13A, respectively.

14A, 15A, 16A and 14B, 15B, 16B are cross-sectional views taken along the lines XIIIb-XIIIb 'and XIIIc-XIIIc' in FIG. 13A, respectively, illustrating the following steps in the order of the process. ,

17A is a layout view of a thin film transistor array panel in the next steps of FIGS. 16A and 16B.

17B and 17C are cross-sectional views taken along the lines XVIIb-XVIIb 'and XVIIc-XVIIc', respectively, in FIG. 17A;

18A is a layout view of a thin film transistor array panel in the next step of FIGS. 17A to 17C.

18B and 18C are cross-sectional views taken along the lines XVIIIb-XVIIIb 'and XVIIIc-XVIIIc', respectively, in FIG. 18A.

In order to achieve such a problem, the present invention forms an opening that exposes the drain electrode when the color filter is formed. At this time, when forming a contact hole for exposing the drain electrode in the protective film to be laminated later, the contact hole may be formed inside the opening or larger than the opening.

According to the present invention, a gate line is first formed on an insulating substrate. Subsequently, a gate insulating film covering the gate line, a semiconductor, and a data line and a drain electrode formed separately from each other and made of the same layer are formed. Next, a plurality of color filters having openings exposing drain electrodes are formed on the substrate. Subsequently, a protective film is stacked on the substrate and patterned to form a contact hole that exposes the drain electrode, and a pixel electrode connected to the drain electrode through the contact hole is formed on the protective film.

In this case, the contact hole may be formed to expose the opening larger than the opening so that the opening and the side wall of the contact hole have a step shape.

Here, an insulating film made of silicon nitride may be further formed before the color filter forming step, and the protective film may be formed by chemical vapor deposition with a low dielectric constant such as acrylic organic material having excellent planarization or SiOC or SiOF of 4.0 or less. It is preferably a dielectric constant insulating material.

In addition, the source and drain electrodes are separated by a photolithography process using a photoresist pattern, and the photoresist pattern is disposed between the source electrode and the drain electrode of the data line and is formed of a first portion having a first thickness and a thicker than the first thickness. It is preferred to include a second portion having two thicknesses and a third portion thinner than the first and second thicknesses.

In the liquid crystal display according to the present invention formed through such a manufacturing method, a gate line is formed on an insulating substrate. A semiconductor is formed on the gate insulating film covering the gate line, and thereon, a data line and a drain electrode formed from the same layer and separated from each other are formed thereon. In each pixel surrounded by the gate line and the data line, red, green, and blue color filters are formed with openings exposing drain electrodes. A protective film having a contact hole exposing the drain electrode is formed in the upper portion of the color filter, and a pixel electrode which is connected to the drain electrode through the contact hole is formed thereon.

In this case, the semiconductor pattern except for the channel portion may have substantially the same shape as the data line and the drain electrode.

Here, the contact hole may be formed to expose the opening larger than the opening so that the sidewalls of the opening and the contact hole may have a stepped shape.

DETAILED DESCRIPTION Embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification. When a portion of a layer, film, region, plate, etc. is said to be "on top" of another part, this includes not only when the other part is "right on" but also another part in the middle. On the contrary, when a part is "just above" another part, there is no other part in the middle.

Hereinafter, a thin film transistor array panel and a method of manufacturing the same according to an exemplary embodiment of the present invention will be described in detail with reference to the accompanying drawings.

First, a structure of a thin film transistor array panel for a liquid crystal display according to a first exemplary embodiment of the present invention will be described in detail with reference to FIGS. 1 to 2. First, the first embodiment of the present invention will be described with reference to FIGS. The structure of a thin film transistor array panel for a liquid crystal display according to an exemplary embodiment will be described in detail.

1 is a layout view of a thin film transistor array panel for a liquid crystal display according to a first exemplary embodiment of the present invention, and FIG. 2 is a cross-sectional view of the thin film transistor array panel illustrated in FIG. 1 taken along the line II-II ′.

A plurality of gate lines 22 extending mainly in the horizontal direction are formed on the insulating substrate 10. The gate line 22 may be made of a single film made of silver (Ag) or silver alloy (Ag) or aluminum (Al) or aluminum alloy (Al alloy) having a low resistivity, and in addition to the single film, It may be made of a multilayer film including other films made of materials such as chromium (Cr), titanium (Ti), and tantalum (Ta) having good electrical contact properties. A portion of each gate line 22 extends to form a gate electrode 26 of the thin film transistor. At this time, the side of the gate line 22 is inclined, the inclination angle is in the range of 30-80 ° from the horizontal plane.

According to another embodiment of the present invention, a plurality of storage electrodes (not shown) forming one electrode of the storage capacitor, which improves the charge storage capability of the liquid crystal capacitor, are formed on the substrate 10. The sustain electrode receives a predetermined voltage from the outside, such as the common electrode voltage (also referred to as "common voltage" for short). The common voltage is also applied to a common electrode (not shown) of another display panel (not shown).

A gate insulating layer 30 made of silicon nitride (SiNx) is formed on the gate line 22 and the storage electrode.

A plurality of linear islands 40 formed of hydrogenated amorphous silicon are formed on the gate insulating layer 30. A plurality of branches of each linear semiconductor 40 extends over the corresponding gate electrode 24 to form a channel of the thin film transistor. A plurality of sets of linear and island ohmic contacts 55 and 56 made of n + hydrogenated amorphous silicon doped with high concentration of silicide or n-type impurities are formed on the semiconductor 40. . Each of the islands of ohmic contact 56 is located opposite to the linear ohmic contact 55 and separated from the gate electrode 24. Sides of the semiconductor 40 and the ohmic contacts 55 and 56 have a tapered structure, and the inclination angle is in the range of 30 to 80 degrees.

On the ohmic contacts 55 and 56 and the gate insulating layer 30, a plurality of data lines 62, a plurality of drain electrodes 66 of the thin film transistor, and a plurality of conductors 64 for holding capacitors are provided. ) Is formed. The data line 62 and the drain electrode 66 may be formed of Al or Ag having a low specific resistance, and may include a conductive material having excellent contact properties with other materials, such as the gate line 22. The data line 62 mainly extends in the vertical direction to intersect the gate line 22 and forms a source electrode 65 having a plurality of branches extending from each data line 62. The pair of source and drain electrodes 65 and 66 are located at least partially on top of the respective ohmic contacts 55 and 56, and are separated from each other and located opposite to the gate electrode 26, respectively.

The storage capacitor conductor 64 overlaps the protrusion of the gate line 22.

Sides of the data line 62, the drain electrode 66, and the conductor 64 for the storage capacitor may have a tapered structure having an inclination angle in the range of 30 to 80 °.

The ohmic contacts 55 and 56 positioned between the semiconductor 40 and the data line 62 and the drain electrode 66 lower the contact resistance therebetween.

The red, green, and blue color filters R, G, and C are disposed on the data line 62, the drain electrode 65, and the conductor 64 for the storage capacitor, and the semiconductor 40 and the gate insulating film 30 that are not covered by the capacitor. B) is formed. Each color filter R, G, B extends in the longitudinal direction and has a plurality of openings C1, C2 exposing a part of the drain electrode 65 and the conductor 64 for the storage capacitor. In the present embodiment, the boundaries of the color filters R, G, and B are located above and coincident with the data lines 62, but according to another embodiment of the present invention, the color filters R, G, and B are connected to the data lines. 62) may have a function of blocking light leaking overlapping each other at the top. The color filters R, G, and B are not formed in the pad portion where the end portions 24, 68 of the gate line 22 and the data line 62 are located.

An interlayer insulating film (not shown) made of an insulating material such as silicon oxide or silicon nitride may be formed under the color filters R, G, and B.

On the color filters 81, 82, and 83, a protective film made of a low dielectric constant insulating material having a low dielectric constant of 4.0 or less, which is formed by chemical vapor deposition such as SiOC or SiOF or an acrylic organic insulating material having excellent planarization characteristics and low dielectric constant, 70) is formed. This protective film 90 has contact holes 76 and 72 exposing the drain electrode 66 and the conductor 64 for the storage capacitor. At this time, the contact holes 76 and 72 exposing the drain electrode 66 and the conductor 64 for the storage capacitor are located inside the openings C1 and C2 of the color filters R, G, and B. As described above, when the interlayer insulating film is added to the lower portion of the color filters R, G, and B, the interlayer insulating film has the same planar shape as the interlayer insulating film. The passivation film 70 also has a plurality of contact holes 78 exposing the end portion 68 of the data line 62, and together with the gate insulating film 30, exposing the end portion 24 of the gate line 22. It has a plurality of contact holes 74. The contact holes 74 and 78 are for electrical connection between the gate line 22 and the data line 62 and their driving circuits (not shown).

In this case, the contact holes 72, 74, 76, 78 of the passivation layer 70 and the sidewalls of the openings C1 and C2 are inclined, and the taper angles may be different from each other. It is preferable that the inclination angle of the side wall is gentler than the inclination angle of the side wall located below or outside, and particularly, these inclination angles are preferably in the range of 30 to 70 degrees. In another embodiment of the present invention, the contact hole 76 of the protective film 70 is preferable. , 72 is larger than the openings C1, C2 of the color filters R, G, B, so that the contact holes 72, 76 and the sidewalls of the openings C1, C2 have a stepped shape. This structure improves the profile of the top film of the contact holes 72, 74, 76, 78.

A pixel electrode 82 made of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO) is formed on the passivation layer 70. The pixel electrode 82 is physically and electrically connected to the drain electrode 66 through the contact hole 76, and is also connected to the conductor 64 for the storage capacitor through the contact hole 72. The protrusions of the < RTI ID = 0.0 >) < / RTI >

The pixel electrode 82 receives a data voltage from the thin film transistor to generate an electric field together with the common electrode of another display panel. When the applied voltage is changed, the molecular arrangement of the liquid crystal layer between the two field generating electrodes changes. In view of the electrical circuit, the pixel electrode 82 and the common electrode form a liquid crystal dielectric capacitor that stores electric charges.

The pixel electrode 82 overlaps the gate line 22 and the data line 62 to increase the aperture ratio, and form a plurality of storage capacitors connected in parallel with the liquid crystal capacitor to enhance the charge storage capability.

On the other hand, a plurality of contact assistants 84 and 88 are formed on the protective film 70. The contact auxiliary members 84 and 88 are connected to the exposed ends 24 and 68 of the gate line 22 and the data line 62 through the contact holes 74 and 78, respectively. The contact auxiliary members 84 and 88 are intended to protect the exposed ends 24 and 68 of the gate line 22 and the data line 62 and to compensate for the adhesion between the thin film transistor array panel and the driving circuit, but are not essential. . The contact auxiliary members 84 and 88 are formed of the same layer as the pixel electrode 82.

According to another embodiment of the present invention, a metal piece isolated in the same layer as the gate line 22 or the data line 62 adjacent to the end portions 24 and 68 of the gate line 22 and / or the data line 62. a metal island is formed, and a contact hole is formed in the gate insulating layer 30 and / or the lower insulating layer 70 thereon, and then connected to the contact auxiliary members 84 and 88.

Next, a method of manufacturing a thin film transistor array panel for a liquid crystal display according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 3A to 7B and FIGS. 1 and 2.

3A to 7A are layout views of thin film transistor array panels at each stage of the method of manufacturing a thin film transistor array panel for a liquid crystal display according to an exemplary embodiment of the present invention, and FIGS. 3B to 7B are thin films of FIGS. 3A to 7A, respectively. The transistor display panel is sectional drawing which cut | disconnected and shown along IIIb-IIIb, IVb-IVb, Vb-Vb, VIb-VIb, VIIb-VIIb.

First, as shown in FIGS. 3A to 3B, the gate line 22 is formed on the insulating substrate 10 by a photolithography process. Next, as illustrated in FIGS. 4A and 4B, three layers of the gate insulating layer 30, the amorphous silicon layer, and the doped amorphous silicon layer are successively stacked, and the two layers are photographed and etched on the gate insulating layer 30. A plurality of linear semiconductors 40 and a plurality of linear doped amorphous silicon islands 50 are formed.

Subsequently, as shown in FIGS. 5A and 5B, a plurality of data lines 62 including a plurality of source electrodes 65, a plurality of drain electrodes 66, and a plurality of storage capacitor conductors 64 are photographed. It is formed by an etching process. Subsequently, portions of the doped amorphous silicon 50 that are not covered by the data line 62 and the drain electrode 66 are removed to transfer each of the doped amorphous silicon 50 to the linear and island resistive contact members 55 and 56. While separating, the portion of semiconductor 40 between the two is exposed. Subsequently, in order to stabilize the surface of the exposed semiconductor 40, it is preferable to perform oxygen plasma.

Next, after forming an interlayer insulating film (not shown), as shown in FIGS. 6A to 6B, photosensitive organic materials including red, green, and blue pigments are sequentially applied, and the openings C1 and C2 are formed through a photographic process. Red, green, and blue color filters having R, G, and B are sequentially formed.

Next, as shown in FIGS. 7A and 7B, the protective films 70 are stacked and patterned together with the gate insulating film 30 by a photolithography process to form the contact holes 72, 74, 76, and 78 in a tapered structure. . The contact holes 76, 72 exposing the drain electrode 66 and the conductor pattern 64 for the storage capacitor are located inside the openings C1, C2 formed in the color filters R, G, B. As shown in FIG. As described above, in the present embodiment, the openings C1 and C2 are formed in advance in the color filters R, G, and B, and then the protective film 70 is patterned to form the contact holes 76 and 72 to form the contact holes 76. , 72) can improve the profile.

In addition, the size of the contact holes 76 and 72 is larger than the openings C1 and C2 so that the side walls of the contact holes 76 and 72 and the openings C1 and C2 are stepped to form a profile of another film to be formed later. It can also make it favorable.

Lastly, as shown in FIGS. 1 and 2, the ITO or IZO layer having a thickness of 400 kHz to 500 kHz is deposited and photo-etched to form the plurality of pixel electrodes 82 and the plurality of contact assistants 84 and 88. Form.

A thin film transistor array panel for a liquid crystal display according to another exemplary embodiment of the present invention will be described in detail with reference to FIGS. 8 to 10.

8 is a layout view of a thin film transistor array panel for a liquid crystal display according to an exemplary embodiment of the present invention, and FIGS. 9 and 10 are each cut along the lines IX-IX 'and XX' of the thin film transistor array panel shown in FIG. One cross section.

8 to 10, the thin film transistor array panel according to the second exemplary embodiment of the present invention includes a plurality of storage electrode lines 28 formed on the insulating substrate 10, and the plurality of gate lines 22. One of the features is that there is no extension part. The storage electrode line 28 is made of the same layer as the gate line 22, is substantially parallel to the gate line 22, and is electrically separated from the gate line 22. The storage electrode line 28 receives a voltage such as a common voltage and faces each other around the plurality of drain electrodes 66 and the gate insulating layer 30 connected to the plurality of pixel electrodes 82 to form a plurality of storage capacitors. . When the storage capacitor generated due to the overlap of the pixel electrode 82 and the gate line 22 is sufficient, the storage electrode line 28 may be omitted or may be disposed at the edge of the pixel region in consideration of the aperture ratio of the pixel region.

In addition, a plurality of linear and island semiconductors 42 and 48 and a plurality of ohmic contacts 55, 56 and 58 are provided.

The linear semiconductor 42 has a planar shape substantially the same as the plurality of data lines 62 and the plurality of drain electrodes 66 except for the channel region C of the thin film transistor. That is, although the data line 62 and the drain electrode 66 are separated from each other in the channel region C, the linear semiconductor 42 is connected to each other without being disconnected to form a channel of the thin film transistor. The island-like semiconductor 48 has a substantially same planar shape as the conductor 64 for the storage capacitor, and the ohmic contacts 55, 56, and 58 are each the data line 62, the drain electrode 66, and the storage conductor. It is the same shape as 68.

The gate line 22, the storage electrode line 28, the semiconductor 42, and the ohmic contacts 55 and 56 have a tapered structure.

Since the contact hole 76 is larger than the opening C1 and the sidewalls of the contact hole 76 and the opening C1 are inclined, the contact hole 76 may have a stepped shape of a tapered structure.

Next, a method of manufacturing a substrate for a liquid crystal display according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 11A to 18C and FIGS. 8 to 10.

11A is a layout view of a thin film transistor array panel in a first step of manufacturing according to an embodiment of the present invention, and FIGS. 11B and 11C are cross-sectional views taken along the lines XIb-XIb 'and XIc-XIc' in FIG. 11A, respectively. 12A and 12B are cross-sectional views taken along the lines XIb-XIb 'and XIc-XIc' of FIG. 11A, respectively, and are cross-sectional views of the next steps of FIGS. 11B and 11C, and FIG. 13A is a next step of FIGS. 12A and 12B. 13B and 13C are cross-sectional views taken along the lines XIIIb-XIIIb 'and XIIIc-XIIIc' in FIG. 13A, respectively, and FIGS. 14A, 15A, 16A, and 14B, 15B, and 16B. Are cross-sectional views taken along the lines XIIIb-XIIIb 'and XIIIc-XIIIc' in FIG. 13A, respectively, illustrating the steps of FIGS. 13B and 13C in the order of the process, and FIG. 17A is a thin film at the next steps of FIGS. 16A and 16B. FIG. 17B and 17C are layout views of the transistor panel. 17A is a cross-sectional view taken along lines XVIIb-XVIIb 'and XVIIc-XVIIc', and FIG. 18A is a layout view of the thin film transistor array panel in the next step of FIGS. 17A to 17C, and FIGS. 18B and 18C are XVIIIb in FIG. 18A, respectively. It is sectional drawing cut along the -XVIIIb 'line and XVIIIc-XVIIIc' line | wire.

First, as illustrated in FIGS. 11A to 11C, a conductive layer such as a metal is deposited to a thickness of 1,000 kV to 3,000 kV by a sputtering method, and patterned by photo and etching processes to form a plurality of gate lines 22 and a plurality of gate lines. The storage electrode line 28 is formed.

Next, as shown in FIGS. 12A and 12B, the gate insulating film 30, the semiconductor layer 40, and the intermediate layer 50 are respectively 1,500 mV to 5,000 mV, 500 mV to 2,000 mV, and 300 mV using chemical vapor deposition. Continuous deposition to a thickness of from about 600 kPa. Subsequently, a conductive layer 60 such as metal is deposited to a thickness of 1,500 kPa to 3,000 kPa by sputtering or the like, and then the photosensitive film 110 is applied thereon to a thickness of 1 μm to 2 μm.

Thereafter, the photoresist film 110 is irradiated with light through a photomask and then developed. As shown in FIGS. 13B and 13C, the photoresist film includes first and second portions 112 and 114 having different thicknesses. Patterns 112 and 114 are formed. In this case, the second portion 114 positioned in the channel region C of the thin film transistor is smaller than the first portion 112 positioned in the data region A, and the photosensitive layer 110 portion of the other region B is thinner. Remove all or have a very small thickness. At this time, the ratio of the thickness of the second portion 114 remaining in the channel region C and the thickness of the first portion 112 remaining in the data region A is determined according to the etching conditions in the etching step described later. The thickness of the second portion 114 is preferably 1/2 or less of the thickness of the first portion 112, for example, 4,000 kPa or less.

As such, there may be various methods of varying the thickness of the photoresist pattern according to the position. For example, a translucent area may be added to the photomask in addition to the transparent area and the light blocking area. There is a way to put it. The translucent region is provided with a slit pattern, a lattice pattern, or a thin film having a medium transmittance or a medium thickness. When using the slit pattern, it is preferable that the width of the slits and the interval between the slits are smaller than the resolution of the exposure machine used for the photographic process. Another example is to use a photoresist film that can be reflowed. That is, a thin portion is formed by forming a reflowable photoresist pattern with a normal mask having only a transparent region and a light shielding region and then reflowing so that the photoresist film flows into an area where no photoresist remains.

First, as shown in FIGS. 14A and 14B, an exposed portion of the conductor layer 60 in the other region B is removed to expose the underlying doped amorphous silicon layer 50. For the conductor layer 60 including aluminum or an aluminum alloy, both dry etching and wet etching methods may be used. For chromium, wet etching using CeNHO 3 as an etchant is preferable. In the case of dry etching, the photoresist patterns 112 and 114 may also be etched to reduce the thickness. Reference numeral 67 denotes a remaining portion of the conductor layer 60 and will be referred to as "conductor" in the future.

Subsequently, as shown in FIGS. 15A and 15B, the exposed doped amorphous silicon layer 50 portion of the other region B and the portion of the semiconductor layer 40 underneath are removed by dry etching to remove the conductive material below. 67). The second portion 114 of the photoresist pattern is removed simultaneously or separately from the exposed doped amorphous silicon layer 50 portion and the semiconductor layer 40 portion. Residue of the second part 114 remaining in the channel region C is removed by ashing. Reference numeral 42 denotes a remaining portion of the semiconductor layer 40, and reference numeral 57 denotes a remaining portion of the doped amorphous silicon layer 50.

Next, as shown in Figs. 16A and 16B, the exposed conductor 67 portion of the channel region C and the doped amorphous silicon 57 portion below it are removed. In this case, as shown in FIG. 16B, a portion of the upper portion of the semiconductor 42 of the channel region C may be removed to reduce the thickness, and the first portion 112 of the photoresist pattern may also be etched to some extent.

In this way, each of the conductors 67 of the channel region C is completed by separating the data line 62 and the plurality of drain electrodes 66, and each of the doped amorphous silicon 57 of the channel region C is formed. The linear resistive contact member 55 and the plurality of island resistive contact members 56 are divided and completed.

The first portion 112 of the photoresist pattern remaining in the data region A is removed after removing the exposed conductor 67 portion of the channel region C or after removing the doped amorphous silicon 57 thereunder. do.

After the data line 62 and the drain electrode 66 are completed in this manner, as shown in FIGS. 17A to 17C, a photosensitive material including red, green, and blue pigments is applied, and a photolithography process is performed through an exposure and development process. Patterning forms red, green, and blue color filters (R, G, B) in turn.

In this case, a light blocking layer made of a red or green color filter may be formed on the channel portion C of the thin film transistor, which may more completely block or absorb visible light having a short wavelength incident to the channel portion C of the thin film transistor. For sake.

Subsequently, a protective film 70 covering red, green, and blue color filters R, G, and B is deposited on the substrate 10 by chemical vapor deposition, and patterned together with the gate insulating film 30 by a photolithography process. Contact holes 74, 78, and 76 are formed to expose the end portions 24, 68 and the drain electrode 66 of the line 22 and the data line 62, respectively.

Finally, as shown in Figs. 8 to 10, the pixel electrodes 82 and the contact auxiliary members 84 and 88 having a thickness of 400 kHz to 500 kHz are formed.

In the second embodiment of the present invention, the data line 62 and the drain electrode 66 and the contact layer patterns 55 and 56 and the semiconductor pattern 42 below the data line 62 and the drain electrode 66 are not only the effects according to the first embodiment. It is formed using a mask and in this process, the source electrode 65 and the drain electrode 66 can be separated to simplify the manufacturing process.

The thin film transistor array panel may be manufactured in various modified forms and methods.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

According to the present invention, the number of masks can be effectively reduced by forming an opening in the color filter and then forming a contact hole in the protective film in the manufacturing process of the thin film transistor array panel for the liquid crystal display device having the red, green, and blue color filters. The manufacturing process can be simplified. In addition, when forming the color filter without adding a process, an opening is formed, and then a contact hole for exposing the drain electrode or the conductor for the storage capacitor is formed inside the opening or larger than the opening to form a contact hole for the drain electrode and the storage capacitor. It is possible to gently induce the profile of the conductive film connected to the conductor.

Claims (11)

A gate line formed over the insulating substrate, A gate insulating film covering the gate line, A semiconductor formed on the gate insulating film, A drain electrode formed on the gate insulating layer, the data line crossing the gate line and the drain electrode separated from the data line; A plurality of color filters each formed in a pixel region surrounded by the gate line and the data line and having a first opening exposing the drain electrode; A protective film covering the red, green, and blue filters and having a first contact hole inside the first opening or larger than the first opening and exposing the drain electrode; A pixel electrode formed on the passivation layer and connected to the drain electrode through the first contact hole; Thin film transistor array panel comprising a. In claim 1, A conductor for a storage capacitor formed on the same layer as the data line and overlapping the storage electrode connected to the gate line or formed on the same layer as the gate line to form a storage capacitor; The red, green, and blue color filters have a second opening that exposes the conductor for the storage capacitor, The passivation layer has a second contact hole overlapping the second opening and exposing the conductor for the storage capacitor. In claim 1, And a storage electrode line formed of the same layer as that before the gate, wherein the drain electrode overlaps the storage electrode line. In claim 1, The passivation layer is a thin film transistor array panel consisting of an acrylic organic material or a chemical vapor deposition film having a dielectric constant of 4.0 or less. In claim 1, The semiconductor except for the channel portion between the source electrode and the drain electrode, which is part of the data line, has a substantially same shape as the data line and the drain electrode. In claim 1, The sidewall of the passivation layer and the color filter defining the first contact hole and the first opening has a stepped shape. Forming a gate line on the insulating substrate, Forming a gate insulating film covering the gate line; Forming a semiconductor on the gate insulating film, Forming a data line and a drain electrode formed on the gate insulating layer to be separated from each other and made of the same layer; Forming a red, green, and blue filter using a photosensitive material including red, green, and blue pigments on the substrate, and forming a first opening exposing the drain electrode; Stacking a protective film covering the red, green, and blue filters, Patterning the passivation layer to form a first contact hole exposing the drain electrode inside the first opening or larger than the first opening, Forming a pixel electrode connected to the drain electrode through the first contact hole Method of manufacturing a thin film transistor array panel comprising a. In claim 7, Forming a conductor for the storage capacitor by overlapping the storage electrode connected to the gate line on the same layer as the data line or positioned on the same layer as the gate line; The red, green, and blue color filters have a second opening that exposes the conductor for the storage capacitor, And forming a second contact hole in the protective film to expose the conductor for the storage capacitor inside the second opening or larger than the second opening. In claim 7, The passivation layer may be formed by coating an acrylic organic material or by depositing a chemical vapor deposition on an insulating material having a dielectric constant of 4.0 or less. In claim 7, And forming an interlayer insulating film using silicon nitride or silicon oxide before the color filter forming step. In claim 7, Separation of the data line and the drain electrode is performed through a photolithography process using a photoresist pattern, wherein the photoresist pattern is positioned between a source electrode and a drain electrode which is part of the data line, and has a first thickness and a first thickness. A method of manufacturing a thin film transistor array panel including a second portion having a second thickness thicker than the thickness and a third portion thinner than the first and second thicknesses.