KR200298536Y1 - Semiconductor device test apparatus - Google Patents

Abstract

The present invention discloses a test apparatus for a semiconductor device. According to an aspect of the present invention, there is provided a test apparatus for a semiconductor device, including: a signal input unit configured to apply a predetermined signal to analyze signal characteristics of each electrode terminal of a memory device; A performance board for applying a signal input from the signal input unit to each electrode terminal of the memory device; And a test device for the semiconductor device having a socket in which the memory device is placed and having a plurality of pins for contacting the performance board, wherein the memory device has a rectangular plate shape disposed on the performance board. The pins of the socket are provided with a plurality of holes, respectively, and both sides of the hole is spaced apart from the hole further electrically connected to the holes and a plurality of grooves in which the connection portion of the display portion is inserted and fixed further includes Characterized in that.

Description

Test device of semiconductor device

The present invention relates to a semiconductor device, and more particularly, to a test device for a semiconductor device for analyzing signal characteristics of a memory device.

In general, semiconductor devices manufactured by a known process are packaged through a series of assembly processes, and the packaged semiconductor devices are mounted on a printed circuit board designed according to a consumer's request, and the modules are packaged. Is produced as.

On the other hand, packaged semiconductor devices, such as memory devices, are subjected to various tests and analyzes on their own before being manufactured as modules, for which a test apparatus such as Advanced is used, and more detailed analysis is performed. For this purpose, software simulation utilities such as Shmoo or Wave Tracer are used.

However, such a test apparatus has a problem that it is difficult to accurately analyze the timing of signals generated at each terminal of the memory element when the memory device is driven. Recently, an oscilloscope is connected to the test device. Therefore, timing analysis is performed on actual signals generated at each terminal of the memory device.

1 is a schematic diagram illustrating a test apparatus of a semiconductor device to which an oscilloscope is connected as described above. As illustrated, the test apparatus may include a signal input unit for applying a predetermined signal to analyze signal characteristics of each pin of a memory device. (1), a performance board (2) connected to the signal input unit 1 and having a circuit pattern to apply a signal input from the signal input unit 1 to a memory device, and the performance board 2 ), A center portion is provided with a groove 3a having a predetermined size in which a memory element in a package state is placed, and a plurality of pin grooves 3b connected to respective pins of the memory element (not shown) on both upper surfaces thereof. Is arranged, a socket 3 having pins 3c contacting the performance board 2 with each electrode terminal of the memory element inserted therein, and a groove 3b of the socket 3. Scope insert profile louvers that: the (Scope Prober 4a) is provided is made with an oscilloscope (4) for the display of signals for each pin of the memory device according to signals received via the loop scope louver (4a).

However, since the test apparatus of the semiconductor device as described above has to repeat and perform the process of inserting and releasing the prober into each of the grooves of the socket connected to each of the pins of the memory device to be tested. There was a problem in that the pin groove of the socket is damaged.

In addition, the test apparatus described above has a difficulty in maintaining the probe state since the operator must hold the prober inserted into the groove of the socket in order to maintain the probe state.

In addition, the test apparatus described above must use a temperature controller such as a thermo stream to test the memory device at a temperature other than room temperature. Since the thermo stream is operated in a vacuum state, insertion of a prober in such a vacuum state is required. And since it can not repeat and perform a release, there existed a problem that analysis other than normal temperature cannot be performed substantially.

Accordingly, the present invention has been made to solve the above problems, it is possible to maintain the probing state, and to prevent damage to the pin groove of the socket, and also to easily perform analysis other than room temperature To provide a test apparatus, the purpose is.

1 is a schematic diagram for explaining a test apparatus for a semiconductor device according to the prior art.

2 is a schematic view for explaining a test apparatus of a semiconductor device according to the present invention.

(Explanation of symbols for the main parts of the drawing)

1: signal input 2: performance board

3: socket 3c: pin

4: oscilloscope 4a: scope probe

10: interface board 10a: first contact portion

10b: second contact portion 12: hole

14: home

In order to achieve the above object, the present invention inserts an interface board for maintaining a probe state between the performance board and the socket in the test device of the semiconductor device. The interface board has a first contact portion including a plurality of holes through which pins of a socket without a memory element are installed at the center thereof and connected to the performance board, and both edges of each of the first contact portions are provided. A second contact portion is provided, which is electrically connected to the grooves and which consists of grooves to allow the scope's prober to be inserted and fixed.

According to the present invention, by performing the probe for each terminal of the memory element by inserting the scope's prober into the second contact portion provided in the interface board, it is possible to prevent the problem that the pin groove of the socket is damaged, It is easy to maintain the probing state because it is not necessary to hold the probe.

Hereinafter, a test apparatus for a semiconductor device of the present invention will be described in detail with reference to the accompanying drawings.

2 is a schematic diagram illustrating a test apparatus of a semiconductor device according to an embodiment of the present invention. Here, the same parts as in Fig. 1 are denoted by the same reference numerals.

As shown, the test apparatus of the semiconductor device of the present invention is provided with an interface board 10 interposed between the performance board 2 and the socket 3. The interface board 10 includes a first contact portion 10a provided with a plurality of holes 12 to which the pins 3c of the socket 3 contact each other, and both sides of the first contact portion 10a. And a second contact portion 10b which is electrically connected to the holes 12 and provided with a plurality of grooves 14 for inserting and fixing the scope probe 4a.

In the above, the first contact portion 10a has a thickness thinner than the length of the pin 3c so that the pins 3c of the socket can contact the performance board 2, and the second contact portion 10b It has a thickness thicker than the length of the scope prober 4a so that the scope prober can be inserted and fixed.

Therefore, the interface board 10 described above is disposed on the performance board 2, and the socket 3 in which the memory element (not shown) is placed is formed by the pins 3c thereof. The first contact portion 10a is contacted, and the pins 3c of the socket are contacted with the performance board 2 through the holes 12 provided in the first contact portion 10a. In addition, the scope prober 4a, which is drawn out from the oscilloscope 4 to probe the signal characteristics of the respective terminals of the memory device, may be provided with respective grooves provided in the second contact portion 10b of the interface board 10. It is inserted and fixed in 14).

Accordingly, when a signal applied from the signal input unit 1 is transmitted to the respective terminals of the packaged memory element which is placed in the socket 3 via the performance board 2, it is applied to the respective terminals of the memory element. The signal is passed through the hole 12 of the first contact portion 10a into which the pin 3c of the socket is inserted and the groove 14 of the second contact portion 10b electrically connected to the hole 12. Signals generated from the respective terminals of the memory element are displayed on the oscilloscope 4 via the scope prober 4a inserted into the groove 14 of the contact portion 10b.

Therefore, when using the interface board 10 described above, since the scope prober 4a is inserted into and fixed in the grooves 12 of the interface board 10, the pin groove 3a of the socket can be prevented from being damaged. In addition, since the operator does not need to hold in order to fix the scope prober 4a, the probing state can be maintained.

In addition, when the signal analysis for each terminal of the memory element at a temperature other than room temperature, the second contact portion 10b of the interface board 10 can be arranged outside the summer stream, so analysis other than room temperature is possible. Do.

As described above, the test apparatus for a semiconductor device of the present invention interposes an interface board between a performance board and a socket in which a memory device is placed, and a signal for each terminal of the memory device is scoped in a groove provided in the interface board. By inserting and analyzing the louvers, it is possible to prevent the socket grooves from being damaged.

In addition, since the scope prober is inserted into and fixed to the groove of the interface board, the probe state can be maintained, thereby preventing waste of test time and manpower on the memory device.

In addition, since the memory device can be tested at a temperature other than room temperature, the reliability of the commercialized memory device can be improved.

Meanwhile, although specific embodiments of the present invention have been described and illustrated, modifications and variations can be made by those skilled in the art. Therefore, hereinafter, the scope of the utility model registration request can be understood to include all modifications and variations as long as they fall within the true spirit and scope of the present invention.

Claims (4)

In the test device for semiconductor devices, With performance boards, An interface board installed on the performance board; The semiconductor device socket is detachably installed on the interface board and is equipped with a semiconductor device under test. Equipped, The interface board is A first contact portion in which the semiconductor element socket is installed and composed of a plurality of grooves; A second contact portion composed of a plurality of grooves for inserting and holding a prober Equipped, Each groove of the first contact portion is electrically connected while being spaced apart from a corresponding groove of the second contact portion. The test apparatus of claim 1, wherein the interface board is provided with a portion having holes thinner than a length of the pin of the socket so that the pins of the socket may contact the performance board. The test apparatus of claim 1, wherein the interface board has a thicker portion than a portion having the grooves. The test apparatus of claim 3, wherein the interface board has a thickness thicker than a length of a connection portion of the display unit.