KR20010024117A - Design rule checking system and method - Google Patents

Abstract

A method for realizing design rule checking for designs that have been calibrated with optical proximity calibration (OPC) or otherwise calibrated is described. The revised designs are accessed to produce a simulated image 2010. The simulated image corresponds to the simulation of an image to be taken on the wafer if the wafer is directly exposed to the light source through the calibrated design 2020. The characteristics of the light source are determined by the set of lithographic parameters. In creating the image, additional features can be used to simulate portions of the forming process. The simulated image can then be used in a design rule checker. It is important that the simulated image can be processed to reduce the number of vertices of the simulated image compared to the number of vertices of the OPC calibrated design layout 2020. In addition, the simulated image can be compared to an ideal layout, and the result can then be used to reduce the amount of information needed to perform design rule checking.

Description

DESIGN RULE CHECKING SYSTEM AND METHOD}

Related Applications

The present application relates to the inventors of Fang-Cheng Chang, Yao-Ting Wang and Patty Yasheng. (Yagyensh C. Pati), a US patent application filed on September 16, 1998, entitled "Method and Apparatus for Data Hierarchy Maintenance in a System for Mask Description." Related. The present application relates to the inventors of Fang-Cheng Chang, Yao-Ting Wang, Yagyensh C. Pati, and the name of the invention is "Mask with advanced data layer. US Patent No. 60 / 069,549, filed December 12, 1997, a Data Hierarchy Advanced Mask Correction and Verification Method, which claims priority to a provisional patent application. Are the inventors of Fang-Cheng Chang, Yao-Ting Wang, Yagyensh C. Pati, and the invention is named "Mask Verification, Calibration, and Design Rule Checking. US Provisional Patent Application No. 60 / 059,306, filed September 17, 1997, entitled "Mask verificationm Correction, and Design Rule Checking," and inventors Fang-Cheng Chang, Wang Yao-Ting ( Yao-Ting Wang, Yagyensh C. Pati, and the invention is entitled "Mask Verification, Calibration and De "Mask verification, Correction, and Design Rule Checking", filed September 16, 1997. The present application also relates to the inventors of Fang-Cheng Chang, Wang Yao-Ting. -Ting Wang, Yagyensh C. Pati, Linad Karklin, dated August 7, 1998, titled "Visual Inspection and Verification." The present application also relates to inventors Yao-Ting Wang and Yagyensh C. Pati, entitled “Phase Shifting Circuitry Manufacturing Method and US Patent Application No. 08 / 931,921, filed Sep. 17, 1997, "Phase Shifting Circuit Manufacure Method and Apparatus." All of these patent applications have been assigned to the assignee of the present application.

In designing integrated circuits, engineers typically rely on computer simulation tools that contribute to creating a schematic design of circuits consisting of individual devices that are coupled together to perform any function. To actually start such a circuit on a semiconductor substrate, the circuit must be translated into a physical representation, or layout, which can then be transferred to the silicon surface. Again, a computer aided design (CAD) tool supports layout designers in translating the discrete circuit elements into shapes that will be implemented into their own completed IC. These shapes constitute individual components of the circuit, such as gate electrodes, field oxide regions, diffusion regions, metal connections, and the like.

Software programs utilized by these CAD systems are generally configured to function according to certain design rules to create functional circuits. Sometimes these rules are determined by any processing and design limitations. For example, design rules define spatial tolerances between devices and interconnect lines so that these devices or lines do not interact in any unwanted way. Design rule restrictions are often referred to as critical dimensions. The critical dimension of a circuit is generally defined as the width of the smallest line or the spacing between the two smallest lines. Thus, the threshold determines the overall size and integration of the IC. The critical dimension of the circuit is generally defined as the minimum width of one line or the minimum space between two lines. As a result, the critical dimension determines the overall size and density of the IC. In current IC technology, the minimum critical dimension for advanced circuits is approximately 0.25 microns in line width and space.

Once the layout of the circuit is created, the next process for manufacturing the integrated circuit (IC) is to transfer the layout to the semiconductor substrate. Optical lithography is well known as a process for transferring geometric shapes to the surface of silicon wafers. This optical lithography process generally begins by forming a photoresist layer on the top surface of a semiconductor wafer. Subsequently, a mask having a fully light transmissive opaque region generally formed of chromium and a completely light transmissive transparent region generally formed of quartz is placed on a photoresist coated wafer. Thereafter, light is directed to the mask through a visible light source or an ultraviolet light source. This light is focused to generate a reduced mask image on the wafer, typically using an optical lens system comprising one or several lenses, filters and mirrors. This light passes through the transparent area of the mask to expose the lower photoresist layer and is blocked by the opaque area of the mask so that the lower portion of the photoresist is not exposed. The exposed photoresist layer is then developed typically by chemically removing the exposed / non-exposed areas of the photoresist layer. As a result, a photoresist layer is coated on the semiconductor substrate, which exhibits a desired pattern defining its geometry, features, lines, shapes. This pattern can be used to etch the lower regions of the wafer.

In addition to the above design rules, the resolution value of the exposure tool used in optical lithography is also a limiting factor for designers of integrated circuit layout. The resolution for the exposure tool is defined as the minimum characteristic by which the exposure tool can repeatedly expose on the wafer. Currently, the resolution of the most advanced optical exposure tools is about 0.25 micron. As the critical dimensions of the layout become smaller and approach the resolution value of the lithographic equipment, the correspondence between the mask and the actual layout pattern developed in the photoresist is significantly reduced. In particular, the difference in the pattern phenomenon of the circuit appearance depends on the similarity of the appearance between each other.

In view of the limitations in IC design, the inventors note that the data depicting the IC pattern is typically presented in a concise hierarchical manner as in a GDS-II data file. At higher levels in the pattern representation layer, the features are presented in a conceptual manner. For example, a memory array is depicted with certain cells repeated in any number of columns and rows. The next lower level in the layer depicts a basic memory cell consisting of subcells A and B. Finally, at the lowest level, the first subcells contain rectangles and polygons that are geometrically primitive. In order to form a physical mask, the hierarchical data must be flattened, enumerating all the geometry cases depicted in the hierarchical. As a typical result of layer flattening, the amount of data storage required to represent the pattern is somewhat increased.

Since the size of the file representing a given IC design is greatly increased as a result of the flattening of the layer, in the best case the flattening of the layer at the final point in the manufacture of the mask is the time when the mask design is loaded into the EB machine prior to physical fabrication. It is desirable to. At present, however, this planarization process is carried out in the earliest stages of the masking of some complex ICs. This is because the initial mask design of complex ICs is typically processed after the initial design is completed to perform one of a number of operations in the design. These operations are performed because of the precision required in masks of complex ICs when the critical dimensions of these ICs approximate the resolution limiting factor of optical lithography. Currently, these operations require some level of flattening of the initial design data, which results in earlier than the desired flattening of the design data. These operations include performing logical operations, generating optical approximation corrections, generating phase shifting masks, and checking the design rules for the masks undertaking these operations.

In particular, all modern modern integrated circuits with regular finite complexity require correction for the optical proximity effect of the initial mask design so that the desired shape after photolithography is accurately reproduced on the wafer. Proximity effects occur when lithographically transferred pattern images at very close spacing to a resist layer on the wafer. The wavelengths of light across the gaps of adjacent phases interfere with each other, distorting the last shifted pattern shapes. Another problem that arises when shape sizes and spacing approach the lithographic tool's marginal resolution is that corners (concave and convex) are overexposed by the concentration or lack of energy at each corner. Or underexposure tends to occur. Another kind of problem is that oversized or underexposed of the small image also occurs when large and small images are transferred to a mask pattern.

Many methods have been developed to overcome the proximity effect problem. These methods include: pre-compensated mask line widths, various photoresist layer thicknesses, processes using multilayer photoresist films, combining electron beam irradiation with optical irradiation, and finally adding additional images to the initial mask pattern to compensate for proximity effects. There is. This last method is known as "Optical Proximity Correction" (OPC).

The additional images added to the initial mask when applying OPC are generally less than the resolution (ie, having dimensions smaller than the resolution of the exposure machine) and are therefore not transferred to the resist layer. Instead, they compensate for proximity effects by improving the last shifted pattern that interferes with the initial pattern.

Recently, several products are known that can be applied to OPC software to define masks including OPC shapes. However, for the same reason as mentioned above, the valid products have some limitations in terms of accuracy, speed, data size and result verification of OPC calibrated mask design.

One problem with OPC is that it is difficult for design rule checkers to determine if an OPC revised design is verified with design rules. OPC generally introduces a number of serifs that greatly increase the number of vertices in the design. As the number of vertices increases, the time required to run a design rule check increases. Therefore, it is desirable to perform design rule checking for OPC calibrated designs more efficiently.

Accordingly, what is desired is a method and apparatus for inspecting OPC calibrated integrated circuit mask designs while solving the above mentioned problems.

The present invention relates to the field of integrated circuit fabrication. In particular, the present invention relates to concepts and implementation techniques for enabling fast and efficient integrated circuit layout multidesign rule checking.

The drawings illustrate the invention by way of example and not by way of limitation. Similar elements are denoted by the same reference numerals.

1 illustrates a simple integrated circuit design layout and a hierarchical tree representation of the layout.

2 illustrates a system level depiction of one embodiment of the present invention.

FIG. 3 illustrates a simple representation of a typical hierarchical data file to be output from the system of FIG. 2.

4 illustrates, in flowchart form, a method of performing logic or algebraic operations on a hierarchical integrated circuit design in which the hierarchical structure of the design layout is maintained in accordance with one embodiment of the present invention.

FIG. 5 illustrates a method in which the method of FIG. 4 provides a logical NOT operation for one of the parent cells of FIG. 1 in accordance with an embodiment of the present invention.

FIG. 6 illustrates a method in which the method of FIG. 4 generates a delta plane of one of the parent cells of FIG. 1 for a logical NOT operation in accordance with one embodiment of the present invention.

7 shows examples of optical proximity corrections that can be made for design layouts.

8 illustrates a system for providing OPC calibration to a design layout in accordance with one embodiment of the present invention.

FIG. 9 illustrates a method in which an embodiment of the FIG. 8 system provides OPC calibration of an initial geometry of one of the cells of FIG. 1.

10A-10B illustrate a method in which the method of FIG. 4 generates a correction layer for overlap regions within one of the parent cells of FIG. 1 for an OPC operation in accordance with an embodiment of the present invention.

FIG. 11 illustrates a method in which the method of FIG. 4 generates one delta plane of one of the parent cells of FIG. 1 for an OPC operation in accordance with one embodiment of the present invention.

12 illustrates another method of providing OPC calibration to an integrated circuit design layout using one embodiment of the present invention.

Figure 13 shows an exemplary screen snapshot of an input design layout from a computer system implementing one embodiment of the present invention to provide OPC calibration of the input design layout.

FIG. 14 shows an exemplary screen snapshot of final output from a computer system implementing one embodiment of the present invention to provide OPC calibration to the input design of FIG. 13.

15 is an enlarged view of an exemplary screen snapshot of the final output of FIG. 14.

16 shows an exemplary screen snapshot of a -1 OPC calibration layer from a computer system implementing one embodiment of the present invention to provide OPC calibration.

17 shows an example screen snapshot of a +1 OPC calibration layer from a computer system implementing one embodiment of the present invention to provide OPC calibration.

18 shows an exemplary screen snapshot of a -2 OPC calibration layer from a computer system implementing one embodiment of the present invention to provide OPC calibration.

19 shows an exemplary screen snapshot of individual cells OPC calibrated by a computer system implementing one embodiment of the present invention.

20 shows an example of a method of checking design rules in a calibrated layout.

21 illustrates a method of checking design rules using an ideal layout in a calibrated layout.

FIG. 22 illustrates a method of generating data to be moved using the example of FIG. 21 for a general design rule checker.

FIG. 23 illustrates a method of performing optical proximity correction based on the results of the inspection process shown in FIG. 21.

24 illustrates inspection and calibration based on inspection.

FIG. 25 illustrates generation of a design rule checker input through the inspection process of FIG. 21.

Although many details are included in the description and drawings, the invention is defined by the scope of the claims. Limitations can only be found in the above claims for the invention.

One embodiment of the present invention includes a method that can check OPC calibrated or otherwise calibrated designs with design rules. This method consists of accessing the calibrated design and generating a simulated image. The simulated image is consistent with simulating the image to be transferred onto the wafer if exposed on the wafer through a calibrated design directly from the light source. The properties of the light source are determined by a set of lithographic parameters. In the creation of the image, additional properties can be used to simulate part of the forming process. Either way, it is important that the result of the simulated image is generated. The simulated image can then be used in a design rule checker. It is important that the simulated image can be executed to reduce the number of vertices of the simulated image compared to the vertices of the OPC corrected design layout.

In some embodiments, the hierarchy of calibrated design is maintained after the process. This allows for a more efficient generation of the simulated image and a more efficient design rule checking process.

In other embodiments, a method of adding calibrations to a design is described. In such embodiments, the simulated image is compared with the required image. The design rule errors identified in the compensation can then be used to add corrections (eg, addition of OPC type corrections) to the initial design. In some embodiments, the hierarchy of design can thereby be maintained to increase the efficiency of the system.

Other embodiments can inspect all improved masks such as OPC, PSM and their derivatives in a single process layer, and inter-layer dependent inspection in the overall process between individual mask layers. This embodiment scans all the patterns of the initial mask design (or preferably the ideal layout) and newly corrected mask patterns (also corrects) by simulating the aerial image contrast of the corrected mask at all locations. The preferred layout). Aerial image simulation provides information on how the projected mask pattern will be taken when the physical mask is used in a photolithography stepper. Simulation of the aerial image can be enhanced by simulating resist and etching processes to provide additional prediction accuracy. The simulation process provides quantitative information about both comparative and absolute variations of simulated contrast or photoresist boundaries from the ideal layout.

The following heuristics represent the inspection procedure of this embodiment. If the corrected layout is "correct", the contrast boundary results from the lithography simulation will only deviate within a given distance from the boundary of the ideal layout. On the other hand, if the deviation in all boundaries between the ideal layout and the stepper contrast image of the calibrated layout is within a given set of tolerances, the calibrated layout may be considered "accurate".

There are several additional applications based on the boundary-checking technique. The geometry of the patterns imprinted in the calibrated layout is now conveniently created in a format suitable for input into the general design rule checker (eg GDS-II layout format), thereby solving the problem of inter-layer dependency checking. In addition, this inspection capability enables optical proximity corrections in two simple ways. First, if the corrected layout is the same as the ideal layout when the inspection described above is applied, the areas requiring corrections (e.g. OPC) are immediately apparent by indicating deviation regions of simulated boundaries in the ideal layout. Secondly, repeatedly checking the intermediate design calibrations against the ideal layout provides an efficient and complete way for automatic calibrations (eg OPC).

In one embodiment, the simulation of the designed mask produces an image designed for the physical image. The designed image is an image generated from a calibrated layout (or other initial mask layout). The physical image is an aerial image simulation generated from a physical mask photograph. Photographs of the physical masks are obtained, for example, using a microscope. The physical mask photograph is a gray scale digital image of a physical mask in the embodiment. The physical image can then be created with the same techniques as above to create a designed image. The designed image can then be compared against the physical image. The results of the comparison indicate whether the physical mask will produce the same structures as the designed mask forms.

In one embodiment, these techniques are executed on a computer using software. In various embodiments, the computer is, for example, a personal computer in a Sun workstation or Windows NT environment. The input of the ideal layout is a file format such as GDS-II, but other embodiments use other layout description formats and languages.

Although many details are included in the above description and shapes, the invention is defined by the scope of the claims. Limitations can only be found in the claims for the present invention.

Before giving a detailed description of the design rule checker, we describe how the hierarchy of designs is maintained in the performance of different types of calibrations and checks. Next, a description of how simplified design rule checking is performed is described.

a. Maintenance of Hierarchy in Designs

As described above, in manufacturing the photolithography mask, it is preferable to flatten the data representing the IC design at the last point in the actual manufacture of the mask. In some cases, however, this planarization occurs earlier than desired. This is because the initial layout of a complex IC is typically processed after the initial design is completed to be able to perform one of a number of operations on the design. Such operations include performing logical operations, generating optical proximity corrections, generating phase shifting masks, and performing design rule checking of masks that perform these operations. In general, these operations require some sort of initial design data flattening to be performed prior to the desired flattening of the design data. This initial flattening of data increases the size of the data storage required and, in response, slows the performance of these operations. In addition, because conventional verification systems typically require the same input data layers, operations that change the design in a non-hierarchical manner make it difficult to perform the critical steps of verifying these modified designs, if possible.

The present invention solves the above problems by providing operating performance, such as OPC calibration, on the input layer IC such that the correct layer at the beginning of the design is maintained. Various embodiments of the present invention are used in integrated circuit fabrication and include a computer system for verifying and correcting masks for performing logic operations on a design layout. These embodiments accept hierarchical mask definition data that defines the shape of a particular mask. These embodiments then generate an output set of data. In one embodiment, this output data includes an OPC calibrated mask definition. Other embodiments of the present invention include entity masks generated using systems that perform OPC correction or mask verification techniques. Still other embodiments of the present invention include computer readable media (eg, hard disks, CDs, and other computer program storage tools) having computer programs that execute OPC calibration or mask verification techniques.

Before describing the invention with reference to the drawings, an overview of one embodiment of the inventive concept is provided. Accordingly, one embodiment of the present invention is directed to receiving a layer definition of a layout and generating one or more additional data layers hierarchically including calibration information provided by an engine performing operations on a design layout. Use a hierarchy preserver. These additional layers are then stored so that they can be combined with each code in the layer definition of that layer.

The following definitions are used in this document. That is, the calibration plane is associated with any node (cell) in the hierarchy so that the output is a calibrated design for that node by applying the calibration plane to the flattened node. The delta plane is essentially the difference between the calibration plane of the node and the sum of all descendant delta planes adjacent to it. Thus, the correction plane of a cell is equal to the delta plane for that cell plus the delta planes of adjacent descendent cells of that cell. Since leaf cells of the hierarchy do not have any descendant cells, the calibration plane for all leaf cells is the same as the delta plane of that leaf cell. In this way, in one example of the present invention, the calibration plane for each cell need not be stored because the overall calibration for the layout can be provided by only storing the delta plane for each cell in the hierarchy.

The basic concept of one embodiment of the present invention is described in two steps, including compilation and linking. Calibration in the compilation phase occurs for all initial geometry in the hierarchy, depending on the operations performed on the design layout. In the linking step, extra correction will be made due to the optical overlap between the descendant cells of the parent cells and the initial geometry of the parent cells. Thus, only additional calibration is saved.

The delta algorithm calculates delta / additional information only considering overlaps of descendant cells and overlap between parent geometry and descendant cells. Only these areas are considered, since only overlaps affect the additional correction change required for the parent cell. The overlap region is not limited to the overlap of the geometry but also includes the proximity overlap. By using a more general definition, all proximity effects / corrections can be considered. The delta algorithm for the cell will now be called the delta plane. The leaves of the hierarchical tree thus have delta planes such as their calibration planes.

At compile time, correction planes for all leaves can be generated by providing the flattened data describing the primitive geometries for each leaf to the computational engine that performs the desired operation on the provided flattened data. At link time, if there is no subcell overlap, the calibration plane for that parent cell is equal to the sum of its descendant delta planes (and, as explained above, any additional delta plane information to be stored for that parent cell). If there is an overlap, the overlap area is flattened, and an intermediate calibration plane for that flattened overlap area is generated. As a result, the intermediate calibration region is used to subtract the sum of all calibration planes of its descendants, the difference being the delta plane stored hierarchically in correspondence with the cells being linked.

The current GDS-II, and most other design database formats describing the complete layout, include placing different mask and chip levels on separate layers. Introduced in various embodiments of the present invention is a layered twist that can be based on arithmetic layers capable of logic (eg, XOR, AND) and arithmetic operations. For example, in an OPC operation, a correction layer representing a particular OPC region may be based on an arithmetic layer. For example, “-1” means negative sheriff, “+1” means positive sheriff, and “-2” means end-butting with minimal overlap in one direction. ). During linking, all correction layers are arithmetically generated using an algorithm that calculates incremental or differential corrections throughout the structure. These delta planes, or arithmetic layers, are presented as separate layers (eg, +1, -1, -2, etc. that map layers 1, 2, and 3) within the database format. This allows the final correction layer for the parent cell to be equal to the increasing sum of the descendants and grandchildren and great-grandchildren of the parent cell from the delta plane of the parent cell and the compile-time correction layer of the leaves.

Hierarchical data management is also possible in the event of correction in a variant embodiment of the present invention in which the delta algorithm or arithmetic layers described above are not used. In this variant embodiment, instead of taking and storing the difference between the correction layers of the parent cell and its descendant cells, a logical operation may be used to compare the correction between the parent and its descendants, thus causing "arithmetic". Instead of the difference, the “logical” difference is stored in the parent cell.

Thus, as summarized above, the present invention provides a method and apparatus for maintaining data layers in a system for mask description. Reference will now be made in detail to the preferred embodiment of the present invention with reference to the drawings. 1 illustrates a hierarchical tree representation of a simple integrated circuit design layout 100 and layout 110. The circuit layout 100 has a destination cell A comprising parent cells B, C and D. The parent cell C includes the same cells G1, G2, G3, G4, G5, and G6. The parent cell D includes the same cells I1 and I2 as the cell H. The parent cell B includes the same parent cells E1 and E2 and the same parent cells F1 and F2. The parent cell E1 comprises leaf cells J1 and K1 comprising the primitive geometries illustrated in FIG. 1. The parent cell E2 includes leaf cells J2 and K2 that contain the same primitive geometry as the cells J1 and K1. The parent cell F1 includes leaf cells L1 and M1 including the primitive geometry illustrated in FIG. 1. The parent cell F2 includes leaf cells L2 and M2 including the same primitive geometry as the cells J1 and K1. The hierarchical tree layout 110 describes the aforementioned cells in a tree format with leaf cells at the bottom of the tree and target cells A at the top of the tree. In addition, each leaf cell herein is often referred to as a leaf node or descendant cell, and each cell above the leaf nodes herein is referred to as a parent cell or simply a node. The integrated circuit design layout 100 of FIG. 1 is provided as a reference IC design in a preferred embodiment of the present invention described below. The simple IC illustrated in FIG. 1 may be applied to all ICs described in a hierarchical format, for example, as an embodiment of the present invention described below.

2 illustrates in block diagram form a system incorporating one embodiment of the present invention. The system described is a system in which logic or arithmetic operations can be performed on an input IC design in which the hierarchical description is performed so that the modified IC design maintains the initial correct hierarchy of the input design. The basic elements of one embodiment of the system include a hierarchy maintainer 210 and a computation engine 240. The hierarchy maintainer 210 includes a compiler 220 and a linker 230.

The hierarchical maintainer 210 of the system accepts as input hierarchical design data 205 describing the integrated circuit design 200. In one embodiment, hierarchy maintainer 210 accepts hierarchical design data 205 in GDS-II format. In other embodiments, hierarchy maintainer 210 accepts hierarchical design data 205 described in all hierarchical file formats. Compiler 220 of hierarchy maintainer 210 works with computational engine 240 to provide a calibration data layer for the primitive geometry to each node of design data 205. The generated calibration data layers represent the changes made to the primitive geometry at each node according to the operations performed by the computational engine 240, which will be described more fully below. In one embodiment of the invention, the computational engine 240 performs logical operations, such as AND or NOT, for example on the input design data 205. In another embodiment of the present invention, the computational engine 240 performs optical proximity calibration on the input design data 205. In another embodiment of the present invention, the computational engine 240 performs design rule checking of the input design data 205.

After compiler 220 generates a calibration data layer for each node of input design data 205, linker 230 works with arithmetic engine 240 to generate a delta plane for each node of the design. The delta plane for each cell is generated to be equal to the difference between the calibration data layer information for a particular cell and the sum of all calibration data layers of the descendant cells of that particular cell. In one embodiment, the delta plane for each cell is generated by a delta algorithm processed by the linker 230 that computes delta / additional information by considering only the overlap in each cell. In one embodiment, these overlaps consist of an overlap between the descendant cells of the cell and an overlap between the parent cell's own primitive geometry and its descendant's geometry. In one embodiment, these overlap regions are not limited to geometric overlap, but also include proximity overlap. The process by which the linker 230 generates the delta plane for each node of the input design 205 is described more fully below.

After the linker 230 generates delta planes, the hierarchy maintainer 210 generates output data 250 representing the input design 205 that has changed in accordance with the operations performed by the computational engine 240, and the output data. 250 maintains an initial robust hierarchy of input design data 205. This output data 250 includes the initial unaltered hierarchical design data 205 and the hierarchical calibration data file 260. The hierarchical calibration data file 260 includes delta plane data for each node of the design data 205, which is initially initialized by the computation engine 240 when the design data 205 and the calibration data 260 are combined. An altered design is generated that represents the operation performed on the design data 205 of the.

The hierarchical output data 250 can then be used for a number of purposes. First, the hierarchical output data 250 may be provided to hierarchical maintainer 210 via online 262 for new logic or arithmetic operations performed on output data 250. Also, since it is hierarchical, it can be provided to a conventional design rule checker 270 that accepts hierarchical data, thereby verifying that the new modified output design is checked to satisfy the design rules for the particular integrated circuit being designed. You can do it. In addition, the output data 250 combines the design data 205 and the calibration data 260 to form a final data layout 275, flatten the combined data layout 280, and then flatten the flattened data. It can be used in mask fabrication 265 by fabricating a substantial physical mask that is provided to the electron beam device to implement modified design data 285.

Now, the generation of calibration data layers and delta planes for each node of design data 205 will be described in more detail. Referring to FIG. 1, one embodiment of the compiler 220 illustrates a depth wise traverse depending on the depth in which each branch of the final parent cell is accessed in sequence and each branch is accessed upward from its leaf nodes. Is accessed using. Thus, referring to FIG. 1, the present embodiment of the compiler 220 is described in the following order, that is, J1, K1, E1, L1, M1, F1, L2, M2, F2, J2, K2, E2, B, G1. The nodes of the integrated circuit 100 are accessed in the order of, G2, G3, G4, G5, G6, C, H, I1, I2, D, and A. As the compiler 220 traverses the tree, the compiler provides the computational engine 240 with flattened data corresponding to the primitive geometry of each cell. The operation engine 240 performs an operation on the flattened data and then returns a result of the operation to the hierarchy maintainer 210. For example, referring to FIG. 1, if leaf cell J1 is compiled, arithmetic engine 240 will return flattened data J '= J + ΔJ. In one embodiment, the amount of data storage is reduced by layer maintainer 210, which solves the above-mentioned equation for ΔJ and stores the value of ΔJ as the calibration layer for cell J. This process is repeated for every cell in the design until the entire tree is traversed. The design data 205 is then linked by the linker 230 in the following manner. The tree is traversed again in the manner described above, where overlap regions for each cell are found and flattened. The flattened overlap region is then input to a computation engine 240 which performs operations on the data in turn and returns the result to the hierarchy maintainer 210. The linker 230 uses the half data from the computational engine 240 to create an intermediate calibration layer, which is used by the linker 230 to generate a delta plane for each cell. Generation of the delta plane will be described more fully below with reference to FIGS. 6 and 10. The delta plane for each cell of the design is then stored in a hierarchical format corresponding to that of the input design data 205 in the hierarchical calibration data file 260.

In one embodiment of the invention shown in FIG. 2, layer maintainer 210 implements a computer system for executing program code stored on computer readable media performing the functions of compiler 220 and linker 230. FIG. It can also be provided. In one embodiment of the invention, the computational engine 240 may also include a computer system for executing program code stored on computer readable media. In one embodiment of the invention, layer maintainer 210 and computational engine 240 are on computer readable media that perform the functions of compiler 220, linker 230, and computational engine 230 together. It has a single computer system for executing stored program code. In another embodiment, hierarchy maintainer 210 and computational engine 240 may be a single computer system that executes two or more different program codes, or two or more other program codes, hierarchy maintainer 210. And a number of separate computer systems for executing the code for the functions of the < RTI ID = 0.0 > In this embodiment, the hierarchy maintainer 210 may optionally provide data to the computation engine 240 via an API. By this embodiment, the layer maintainer 210 of the present invention can be modified to operate in communication with the existing computational engine 240 to provide the advantages of hierarchical data output.

The above-mentioned computer readable media may include all computer storage tools, including but not limited to hard disks, CDs, floppy disks, and server memory. Computer systems that execute the program code include, for the computational engine 240 and the hierarchy maintainer 210, all desktop computers including, for example, a Windows NT operating system or a desktop computer operating a Sun Soulris workstation. Have a suitable computer system.

3 illustrates a simplified representation of typical hierarchical data output from one embodiment of the FIG. 2 system. The hierarchical data file of calibration data 320 represents a simplified variation of calibration data that occurs when the system of FIG. 2 is applied to operate with respect to the simplified integrated circuit layout 100 of FIG. As described above, hierarchical design data 205 is provided to a hierarchical maintainer 210 that operates with computational engine 240 to provide hierarchical calibration data 260. A simplified hierarchical data file of design layout 310 is shown to illustrate that the present invention has a minimal effect on data growth when performing operations. As shown, the hierarchical data file of calibration data 320 may be stored in a structure that corresponds one-to-one with input data file 310. This can quickly combine two data files 310 and 320 to perform other functions, such as mask fabrication and design rule checking, on an overall modified design.

Also note that when a cell is traversed by hierarchy maintainer 210, hierarchy maintainer 210 determines whether the cell matches a cell that has already been traversed. If so, hierarchy maintainer 210 does not have the processing time to immediately determine the delta plane for that cell. Instead, the hierarchy maintainer maintains a clear hierarchy by providing a pointer to the first case of a defined cell. For example, this is illustrated as a hierarchical data file of calibration data 320 by the same cells F1 and F2 as shown in FIG. 1. As previously described, in one embodiment of the present invention, hierarchy maintainer 210 traverses design data 205 in different ways in depth from leaf nodes to the final parent cell. In this way, F1 will be traversed before F2, so that calibration data ΔF1 is generated and stored for that cell. This is represented by label 325 within file 320. However, when cell F2 is traversed, only a pointer to calibration data for F1 is stored and no calibration data is processed for F2. This is represented by label 330. In this manner, processing time and data amount are reduced.

4 illustrates, in flowchart form, a method of performing logic or algebraic operations on a hierarchical integrated circuit design in which the hierarchical structure of the design layout is maintained in accordance with one embodiment of the present invention. Briefly described, the method includes a compilation process and a linking process. At block 400 a hierarchical design data layout is provided, and at block 410 the design tree is accessed in the manner described in FIGS. 2 and 3 above. At block 415 the compilation process begins, with hierarchical data for the first cell in the tree. Next, block 425 determines if the cell has been previously defined. If previously defined, the obtained cell is combined with the previously defined calibration data at block 427, and the next cell in the tree is obtained at block 415. If the next cell is not previously defined, at block 430 the planarized raw structural data of that cell is obtained and provided to block 435 to perform an arithmetic or logical operation on the planarized raw data. The modified and flattened raw data is then provided to block 440, which is processed at block 445 to separate the desired calibration data as previously described for ΔJ in FIG. 2. The separated calibration data is then stored in block 450 in a hierarchical format corresponding to the initial design data. In block 455, determine if all cells have been traversed. If all cells have been traversed, the linking process begins at block 460, and if all cells have not been traversed, the compilation process will continue at block 415 until all cells have been traversed and compiled.

In block 460, the linking process begins in the same manner as the compilation process for accessing the design tree. The process continues at block 465, where hierarchical data is obtained for the first cell in the tree. Then at block 470 it is determined if the cell has already been defined. If previously defined, the obtained cell is combined with the calibration data previously defined at block 427 and the next cell in the tree is obtained at block 465. If the cell has not been previously defined, determine the overlap of the cell at block 475 as described above with respect to FIG. These overlap regions are then flattened at block 480, and this flattened data is provided to block 435 to perform arithmetic or logical operations on the flattened data as previously described. This operation performed on the flattened data is then used to generate an intermediate calibration layer at block 483, and at 485 a delta plane is generated for that cell, which is layered at block 490. Data format is stored. The delta plane is the only data needed to keep each cell in the tree. As described above, if there is a parent cell and its descendant cells, the difference between the sum of the calibration information for the parent cell and the calibration data of all its descendants is equal to the delta plane. Thus, the leaves of the hierarchical tree will then have the same delta planes as their correction planes determined at compile time. In block 495, it is determined whether all cells in the tree have been traversed. If all cells have been traversed, the process may be stopped and the output data may be used for the various functions described previously, and if all cells have not been traversed, the linking process may be repeated until all cells of the tree have been traversed in step 465. Continues.

FIG. 5 shows how a particular embodiment of the present invention performs a logical operation on the parent cell F1 of FIG. 1. In this case, assume that it is preferable to perform a logical NOT operation on the parent cell F1. Preferred output is shown in FIG. 5 as F1 (NOT). To do this, the operation is performed on the NOT operation on the flattened data representing the leaf L1 and the flattened data representing M1 using the computational engine 240 of FIG. 2 in the manner described above for block 435 of FIG. 4. Will perform the NOT operation on the. The results of these operations are then stored in hierarchical form so that the calibration data is coupled to the appropriate nodes. These results are shown in FIG. 5 as L1 (NOT) and M1 (NOT). However, without the theory of the present invention, it is not possible to obtain the desired F1 (NOT) obtained by simply adding L1 (NOT) and M1 (NOT). This is represented by an inaccurate result 510 obtained by adding L1 (NOT) and M1 (NOT).

One embodiment of the present invention will act to obtain the exact result of F1 (NOT) as follows. Referring to FIG. 2, in a simple example, hierarchical design data 205 composed of data representing the parent cell F1 is provided to the compiler 220 of the hierarchy maintainer 210. Compiler 220 provides flattened data representing leaf L1 to arithmetic engine 240, which in this case performs a logical NOT operation on the supplied data and then Returns flattened data indicating NOT. As described above, compiler 220 generates calibration data for L1 and then stores this data in hierarchical calibration data file 260. The same process is repeated for the leaf M1. When there is no primitive geometry related to parent cell F1, compilation of parent F1 does not result in any calibration data for F1. After compilation of F1, the linker 230 operates to generate a delta plane 520 for the parent cell F1 during the linking phase, which will be described in more detail below with reference to FIG. When the delta plane 520 is generated and L1 (NOT) and M1 (NOT) are added, F1 (NOT), which is a desirable and accurate result, is obtained as shown in FIG. The delta plane data is then stored hierarchically in the hierarchical calibration data file 260 and combined with the parent cell F1. This example merely illustrates the use of an embodiment of the present invention in performing a particular logical operation on a sample IC layout. As such, it will be apparent that embodiments of the present invention may be used to perform all logical operations on all IC layouts described in a hierarchical manner.

6 heuristically illustrates how delta plane 520 is generated in accordance with one embodiment of the invention of FIG. 5. Referring back to FIG. 2, after the computational engine 240 performs a logical NOT operation on the flattened raw data of the respective leaf cells L1 and M1 during the compilation phase, the hierarchy maintainer 210 may execute the parent ( While F1) is linked, it operates to find overlap regions in the parent cell and to planarize these regions (600), which results in an overlap region 640. The flattened data for the overlap area 640 is then provided to the computational engine 240 at block 610, whereby the NOT 650 of overlap is generated by the computational engine 240. Thereafter, a logical NOT operation is performed on the parent F1 at block 620 to generate F1 (NOT) in a flattened form. Finally, the delta plane 520 is generated by taking the difference between the NOT 650 of the overlap area and the flattened F1 (NOT) and storing this delta data in the hierarchical calibration data file 260.

The use of the present invention in a system for generating OPC calibrated layouts is now described. As previously described, as the characteristics of integrated circuit designs become smaller and smaller, the resolution limit of optical lithography has an increasing effect during the exposure process. For example, it has been found that the difference in pattern development of circuit regions depends on the proximity of the regions to each other. Proximity effects occur when pattern areas that are very closely located are lithographically transferred to the resistive layer on the wafer. The light wavelengths of the closely located regions interact with each other, distorting the finally transferred pattern regions. Another problem that arises when the size and spacing of an area approaches the resolution limit of a lithography tool is that corners (concave and convex) are overexposed or insufficiently exposed due to concentration or lack of energy at each corner. There is a tendency. In addition, other forms of problems arise, such as excessive or insufficient exposure of small areas, for example when large and small areas are transferred from the same mask pattern.

Many methods have been developed to overcome the problem of proximity effects. These methods include: crossover of mask line widths, variations in photoresist layer thickness, use of multiple photoresist processes, use of electron beam imaging with optical imaging, and finally an initial mask to compensate for proximity effects. Includes adding additional regions to the pattern. This last method is known as “optical proximity calibration” (OPC).

7 illustrates an example of optical proximity correction that may be made for design layouts. Additional areas added to the initial mask when OPC is used are typically sub-lithography (ie, having dimensions below the resolution of the exposure tool) and are therefore not transferred to the resistive layer. Instead, they interact with the initial pattern to improve the pattern eventually transferred and compensate for the proximity effect. For example, as shown in FIG. 7, the preferred pattern 710 will look like the actual pattern 720 when lithographically transferred without compensating for the proximity effect. Using OPC techniques, positive sheriffs 732 and negative sheriffs 734 may be added to the desired pattern 710 to form a mask 730 necessary to compensate for the proximity effect. Similarly, FIG. 7 shows the effect of near distortion on a typical preferred transistor gate pattern 740 with substantially transferred patterns 750 and 752. When the OPC calibration represented by the hammerhead 762, assist bars 764 and bias bars 766 is added to the initial desired mask pattern, the initial desired shape will be transferred more accurately. For transistor gates, the hammerhead shapes 762 are designed to eliminate the line end shortening effect to ensure that the polysilicon portion of the gate extends beyond the active region 742. The assist bars 764 are designed to compensate for the insulated gate effect, which tends to reduce the width of the transferred gate pattern. Finally, bias bars 766 are designed to eliminate the effect of tightly filled gates represented by additional transfer pattern 752. In some cases, existing OPCs use a rule-based algorithm to generate proximity corrections for a given geometry. For this type of system, the design layout is decomposed into certain layout patterns and one of the above-mentioned types of OPC areas is generated for the area of the design layout. However, unlike one embodiment of the present invention, previous OPCs do not maintain a robust hierarchical data structure of the initial design layout.

An embodiment of the present invention that can generate OPC calibration for an IC design layout while maintaining a robust hierarchical data structure of the initial design layout is described below with reference to FIG. 8. This description is incorporated by reference to the descriptions of FIGS. 2 and 4 above, as the system of FIG. 8 is a particular embodiment of the systems and methods described in each of these figures.

Referring to FIG. 8, integrated circuit chip design 800 is represented by hierarchical design data 810, which in one embodiment is a GDS-II data format. Design data 810 is provided as input to a computer system operating an OPOC algorithm 840 incorporating one embodiment of the present invention. Computer system 840 operates to generate hierarchical calibration data 845 in the manner previously described with reference to FIGS. 2 and 4 above. In this regard, it can be seen that computer system 840 includes hierarchical maintainer 210 and computational engine 240 of FIG. 2, where computational engine 240 of computer system 840 performs optical proximity calibration. A specially defined OPC computation engine 240 that operates on historical design data 810 to provide.

As shown in FIG. 8, output hierarchical calibration data 845 may be provided to the conventional design rule checker 850 along with the initial design data 810 to check the design rules of the OPC calibrated design. Similarly, as shown at block 860, the output may be used to fabricate a lithographic mask by combining design data 810 and calibration data 845. The combined data is then flattened as in block 865 and then provided to the EB device, where the EB device operates to produce the mask.

In one embodiment of FIG. 8, computer system 840 executes computer program code stored on computer readable media that performs functions of compiler 220, linker 230, and OPC computation engine 240. . In another embodiment, computer system 840 is a single computer system that executes two or more other program codes, or two or more other program codes, program code for the functions of hierarchy maintainer 210, and The functions of the computational engine 240 include a number of individual computer systems that execute individual program code. In this embodiment, the hierarchy maintainer 210 may selectively provide data to the computational engine 240 via an API. It may be. By this embodiment, the layer maintainer 210 of the present invention can be modified to operate in communication with the existing computational engine 240 to provide the advantages of hierarchical data output.

The above-mentioned computer readable media may include all computer storage tools, including but not limited to hard disks, CDs, floppy disks, and server memory. Computer systems that execute the program code include any suitable computer system, including, for example, a computational engine 240 and a hierarchy maintainer 210, a desktop computer running a Windows NT operating system or a Sun Soulless workstation. It is provided.

Computation engines that simply provide a given layer input for OPC calibration are well known in the art. In one embodiment of the FIG. 8 system, the OPC engine 240 is a rule-based OPC engine that can generate OPC regions in a manner that can be controlled by the user of the system. For example, the user can define the size of the areas applied to the calibration rules and design layout applied. Further, in one embodiment of the system, the position and size of the bias lines 766 are calibrated and / or the size of the IC pattern regions that are limited to being used only in critical areas of the design, such as transistor gate regions, for example. And depends on the pitch. In addition, in another embodiment of the system, OPC engine 240 may apply assist regions 764 in a localized manner to critical regions such as transistor gates, or to the entire IC design as a whole. . Further, in other embodiments, the OPC engine may selectively place calibration regions only in critical regions and not in those regions that do not require accurate circuit performance. In one example of such an embodiment, the OPC engine may define placing biasing and assist regions in transistor gates while leaving the non-critical interconnect regions of the polysilicon gate layer uncorrected. In another example, the OPC engine distinguishes critical transistor gate line-ends and applies hammerhead calibration to these areas to reduce line-end shortening. Finally, in another embodiment of the present invention, the OPC computation engine was created by Mr. Zhang Fang-Sheng, Wang Yao-Ting and Patty Yashun, previously referred to herein as cited herein. OPC calibration of phase shifting masks disclosed in US patent application Ser. No. 08 / 931,921, filed May 17, entitled “Phase Displacement Circuit Fabrication Methods and Apparatuses.”

FIG. 9 shows how one embodiment of the FIG. 8 system provides OPC calibration of primitive geometries of leaf cells J1 and K1 of FIG. 1. Shown are the uncorrected leaf cells J1 and K1 of the parent cell E1. J's flattened raw geometry data is provided to the hierarchy maintainer 210, and the compiler 220 works with the OPC engine 240 to provide a calibration plane ΔJ1 in the manner previously described with respect to FIG. In this case, the OPC engine, based on its rule definitions, needs positive serifs 905 to provide proper results when J1's primitive geometry is used to mask and manufacture the wafer. I've decided to do it. The same process is performed for the planarized primitive geometry of K1, generating the correction plane ΔK1 while also including the positive serifs 905. Each of these cells are then linked by the linker 230 described previously to generate a delta plane for each cell. Since these cells are leaf nodes and have no overlap area, the individual delta planes are the same as their compiled calibration planes. Also shown are calibrated leaf cells 910 and 920, which represent J1 + ΔJ1 and K1 + ΔK1, respectively.

10A and 10B illustrate how the method of FIG. 4 generates an intermediate calibration layer for overlap regions in the parent cell E1 of FIG. 1 for an OPC operation in accordance with an embodiment of the present invention. 10B illustrates the overlap region 100 between the calibrated leaf cell J1 910 and the calibrated leaf cell K1 920. As described above with reference to FIGS. 2 and 4, during the linking process for the cell E1, this overlap region is determined and the data corresponding to the region is flattened. The planarized overlap area is then provided to the OPC computation engine 240 operating on the data to provide an intermediate calibration plane 1020. Note that in the case where the primitive structures are described herein where the discrete amounts overlap, negative serifs 1010 are provided for the intermediate calibration plane. In the case described below with reference to FIG. 10B, a modified parent E1 is shown that shows the corrected leaf cells K1 and K2 as 910b and 920b, respectively. This case illustrates a slight overlap between two calibrated primitive geometries. In one embodiment of the present invention, for these slight overlaps, an intermediate calibration plane 1020b is provided to provide -2 layers for compensation of the termination butting effect.

FIG. 11 illustrates how the method of FIG. 4 generates the delta plane of the parent cell E1 of FIG. 1 for OPC operation in accordance with one embodiment of the present invention. As described by block 1100, in the linking step for cell E1, overlap regions in E1 are determined and region data is flattened. This is illustrated by the overlap area 1000. Subsequently, as described by block 1110, an intermediate calibration plane 1020 for the overlap area 1000 is generated as described above with respect to FIG. 10A. At block 1120, the calibration planes 910 and 920 of all the progeny cells of E1 are summed to generate the summed progeny calibration data 1140. The final step, described by block 1130, generates a delta plane 1150 for cell E1 and stores this data hierarchically. This is accomplished by subtracting the aggregated progeny calibration data 1140 from the intermediate calibration plane 1020 to obtain the delta plane 1150. Also shown in FIG. 11 is a final calibration plane 1160 for cell E1, which has been described above in order to properly apply OPC to the cell in a particular operation, as described above. Represents total calibration needed to apply to design data. The calibration plane 1160 has a delta plane of E1 summed with the calibration planes 910 and 920 of the offspring J1 and K1, respectively.

12 illustrates another method of providing OPC calibration to a design layout using one embodiment of the present invention. In block 1200, an integrated circuit layout is first provided. Then, in block 1205, hierarchically formatted design data corresponding to the design layer is provided to the system performing rule-based OPC calibration on the design data according to the system of FIG. The system of FIG. 8 generates a hierarchical calibration data output as described above, and as shown at block 1210, the calibration data is hierarchically described in combination with the initial design data and then rules-based OPC calibrated design data. Generates. Using this corrected design data, a simulated image of a mask from which the corrected data will be generated is generated at block 1215. This simulation was applied, for example, by a US-patented patent titled “Mask Verification, Calibration and Design Rule Checking,” filed on September 17, 1997, by Jean Fang-Sheng, Wang Yao-Ting and Pat. United States Patent No. 60 / 059,306, entitled “Mask Verification, Calibration and Design Rule Checking,” filed September 16, 1998, by Jean Fang-Cheng, Wang Yao-Ting, and Pat. The application, and more specifically, Zhang Feng-cheng, Wang Yao-ting, Patty Yasheng. And generated using the Hopkins equation-based simulation apparatus described in the U.S. Patent Application entitled "Visual Inspection and Verification System," filed August 7, 1998, filed by Kachrin Linard, each of the aforementioned The patent applications of were previously incorporated by reference herein.

Then, at block 1220, the simulated image of the corrected mask is compared to the desired design image, and then, at block 1225, initial rule-based OPC correction to ensure that the design is within a user-defined set of parameters. Determine if is enough. Methods of performing such comparisons are disclosed in the aforementioned US Provisional Patent Application “Mask Verification, Calibration and Design Rule Checking,” and the same applicant's US Patent Application. If the design parameters are obtained as a result of the comparison, the corrected design data is entered into the design rule checker, which is corrected for any violation of the design rules specified for the particular integrated circuit design in block 1235. Analyze the design. If a calibrated design is included in the design rules, the calibrated design data is flattened and a mask is fabricated using an EB device, as indicated by block 1245. If the design rules do not match, then at block 1250 a decision should be made whether to redesign the mask.

If the decision is made to approach and solve the problem by continuing the iterative calibration procedures rather than the decision to redesign the mask, then the model-based OPC algorithm works on the calibrated design. Similarly, if initial calibration design data is not included in the design parameters of block 1225, the initial calibration design data is input to the model based OPC algorithm. The model-based OPC algorithm is used to perform more explicit calibration for the initial calibration design, as indicated by block 1230. The model-based OPC calibration design is then provided to block 1215, where a simulated image of the model-based OPC calibration design is generated and compared once again with the desired image. Before entering the OPC calibration design into a conventional design rule checker article for design analysis, the simulated image of the model-based OPC calibration design must be processed in a format acceptable by the conventional design rule checker. One way of doing this is the boundary checking described in more detail in the United States patent application “Mask Verification, Calibration and Design Rule Checking” mentioned above and previously referenced by reference herein, and the United States patent application of the same applicant. It generates a Manhattan geometry representation of a simulated image based on technology. All these processes can continue until a calibration design is produced that satisfies user-defined design parameters and circuit specific design rules.

In one embodiment of this process, the model based OPC algorithm may respond to user specified input. For example, in one embodiment, the user can control the complexity of the level of calibration desired to apply to the control of the amount of data and the overall process speed. Similarly, in another embodiment, the user can control the size of the correction regions applied by the model based algorithm. In another embodiment, the user can also determine the calibration criteria to be applied by the algorithm.

Remaining Figures FIGS. 13-19 illustrate screen snapshots from a computer system implementing one embodiment of the present invention providing OPC calibration for hierarchical input IC design layouts. For example, FIG. 13 shows an example screen snapshot of an OPC calibrated input design layout. The user interface 1300 of the design program has a design window 1330 showing the calibrated IC design layout. The design layout includes a diffusion layer 1390 and a polysilicon structure layer, such as the primitive structure 1320. Similar to the sample parent cells E1 and F1 of FIG. 1, cell 1310 is also shown within design window 1330.

FIG. 14 shows an exemplary screen snapshot of the last output from a computer system implementing one embodiment of the present invention providing OPC calibration to the input design of FIG. 13. Design window 330 of user interface 1300 shows cell 1310 containing OPC calibrated primitive structures 1320. The cell 1310 stores OPC regions, such as, for example, hammerheads 1410, assist lines 1420, bias lines 1430, positive serifs 1440 and negative serifs 1450. Include. The output shown in FIG. 14 represents all the calibrations that should be compensated for for all OPC effects for the overall design. Thus, these corrections represent the finally linked output of the embodiment of the present invention in which all overlaps between cells in the layer are resolved and compensated for. The OPC regions shown in FIG. 14 can be viewed in more detail in FIG. 15, which magnifies the example screen snapshot of FIG. 14. This layer includes calibration for cell 1310 including assist lines 1420, bias lines 1430, and negative serifs 1450.

Figure 16 shows an example screen snapshot of the -1 OPC calibration layer from a computer system implementing one embodiment of the present invention to provide OPC calibrations. This layer has calibrations for the cell 1310 including assist lines 1420, bias lines 1430 and negative serifs 1450.

FIG. 17 illustrates an example screen snapshot of a +1 OPC calibration layer from a computer system implementing one embodiment of the present invention to provide OPC calibrations. This layer has calibrations for the cell 1310 that includes hammerheads 1410, assist lines 1420, and positive serifs 1440.

Figure 18 shows an exemplary screen snapshot of the -2 OPC calibration layer from a computer system implementing one embodiment of the present invention performing OPC calibration. This layer includes a calibration for cell 1310 that includes termination butting calibration region 1810.

19 shows an exemplary screen snapshot of an individual cell 1310 calibrated by OPC by a computer system implementing one embodiment of the present invention. Design window 1330 includes cell 1310, to which a linked calibration layer of cell 1310 is applied. Calibration applied to cell 1310 includes hammerheads 1410, assist lines 1420, positive serifs 1440, and negative serifs 1450. It should be noted that the calibration for cell 1310 is different from those shown in FIG. 14, which is a representation of all calibrations for the overall design, and FIG. 19 is only needed individually for calibration cells 1310. This is because only a representation of the calibration is shown. That is, the calibrations shown in FIG. 19 do not take into account the interaction between cell 1310 and other cells adjacent thereto. For example, note that the bias lines of FIG. 14 are not in FIG. 19.

b. Design Rule Checking

As discussed above, various techniques can be used to maintain the hierarchy of design during mask inspection, image simulation, OPC addition, and design rule checking. However, it is important to understand that not all embodiments of the present invention require the preservation of hierarchical data. What is important in some embodiments of the present invention is that it is possible to perform design rule checking on calibrated designs, such as OPC calibrated designs.

20 illustrates one embodiment of a method of performing design rule checking for a revised design layout. Note that in this section, the terms design and design layout and design layout geometry all have the same meaning. In FIG. 20, the calibrated design proceeds at block 2010. Block 2010 generates a simulated image. The simulated image follows the simulation of the image to be taken on the wafer if the wafer is directly exposed to the light source through the calibrated design. The characteristics of the light source are determined by the set of lithographic parameters. In creating the image, additional features can be used to simulate portions of the forming process. However, the important thing is that the result of the simulated image is generated.

Then, at block 2020, the simulated image can be processed using a technique of boundary detection. The processed image thus has a smaller number of vertices than the simulated image and must have a smaller number of vertices for the number of vertices of the OPC corrected design layout.

Then, at block 2030, the processed image can be provided to a standard design rule checker.

21 illustrates the basic inspection method used in one embodiment when the ideal layout is compared to the simulated image. In one embodiment, the generation of the simulated image produces an outline for the contrast of light in the lithographic simulation. Multiple contours can also be used to examine other variables and do not use simple contrast variables (eg light gradient or algebraic gradient). In a given simulated image, Δ _O and Δ _I are outside and inside to examine whether the contour (s) for the light and shade of light are outside and inside the ideal geometry, respectively, in the region of + Δ _O and -Δ _I. Distance. These distances can be specified in non-absolute measurements (eg a percentage of width or a function of the dimensions of an ideal geometry). This boundary checking method is not limited by the Manhattan geometry. This can be extended and applied to non-Manhattan geometries.

The lithography simulator, in one embodiment, uses Hopkins equations to simulate the resulting image of a given mask layout. The input data representing the mask layout can be a GDS-II representation of the mask layout and can be a digital image of the physical mask or another representation of the mask. Important parameters of the photolithography equipment used in the Hopkins equation are the NA-numerical aperture, the wavelength of light used and associated with the value of the light in a sigma-photolithography system. Effectively, the Hopkins equations are separated into a number of lowpass filters applied to the input data. The resulting images are added to produce a simulated image. In some embodiments, the optical response of the photolithography system is determined by the scanned image of the resulting structures and the physical masks for producing such structures. The example mask and structural images are compared to determine lithographic characteristics of the photolithography system.

Figure 21 provides a simplified basic flowchart of a basic mask inspection process using an ideal mask layout. The system simulates, at block 2110, an aerial image of the input layout using parameters of steppers (photolithography equipment). At block 2120, the difference between the image of the ideal layout and the corrected layout for varying light contrasts is examined. Tolerance is used to determine the area outside the acceptable range of deviation between the image of the corrected layout and the ideal layout image. (In some embodiments, the image of the corrected layout is compared with the ideal layout itself. In block 2130, in some embodiments a deviation above the tolerance level is indicated. The corrected mask is then changed automatically or manually to compensate for the deviation. At block 2140, if the deviation is within tolerance, the result of the corrected mask is converted into a form that can be used in mask fabrication equipment or other tools. Alternatively, the result of the simulated image of the corrected mask can be converted back to the layout for use in other tools. This can be done with the conversion of the simulated image. The simulated image can be represented, for example, as a gray scale image and represented by a number of polygons. Circuit extraction tools can then be used in the layout result for better precision of the properties model of the formed circuits.

Figure 22 shows how the geometry of the simulation is created quickly and easily and entered into the general design rule checkers (see Figure 25). In this case, the maximum deviation of the contrast boundary is found to describe the geometry of the simulation (see blocks 2210, 2220 and 2230). In the case of FIG. 25, the result of the simulated image for the corrected mask is converted to polygons. After the transformed geometry is created, it can be the format used in the design rule checker (block 2240).

FIG. 23 shows a method similar to the flagging of calibrated designs (such as OPC calibrated designs) with repetitive inspection and location of flags that are not within preset boundaries by Δ _O and Δ _I (see FIG. 24). It shows what is achieved by. At block 2310, a basic check is performed. At block 2320, areas that are not considered necessary for the design rule check of the ideal image are excluded. At block 2330, the size and position of the area to be flagged is specified to add or subtract OPC shapes from the ideal layout to change the layout. The modified layout is then fed back and used to check against the ideal layout. This process is repeated until the entire layout satisfies the dead tolerance standard.

Note that the feedback arrows in FIGS. 22 and 23 convey the meaning of the feedback control and adaptation process.

24 shows a basic inspection method through some examples of OPC. The upper left of the figure is a simple mask layout. The lower left is a simulated aerial (stepper) image of the mask layout. The upper middle of the figure is the border drawn around the aerial image for the outer lines of the mask layout (this border may be for a certain level of contrast). The inspection ends as indicated in the middle of the lower end by indicating positions in the contrast outline deviations from the layout outline. It should be noted that, firstly, the contrast contour deviation with respect to the inside or outside of the ideal boundary is examined and displayed in different colors and positions, and secondly, the positions of the marked outlines indicate that the protruding contours The outlines, which are marked in, are placed oppositely (top right), as indicated outside the boundary. It is convenient to make optical proximity corrections (bottom right) with repeated inspections of the new design for ideal layouts and with repeated calibrations based on the inspected results. The upper right pattern of Figure 24 is obtained with only one iteration.

25 provides an example of how inner layer dependent inspection can be performed by feeding new geometry information from a simulated image to general design rule checkers. By repeatedly applying the basic inspection method depicted in FIG. 21, the geometry of the simulated stepper image contrast can be obtained in any format (eg GDS-II). This format is compatible with common design rule checking tools and can be used as input.

Note that the geometry is, for example, a polygon representing contrast level contours. The simple test method outlined above is useful, but will not be sufficient to explain the accuracy of the new design. This means that all geometry of the transferred shapes is depicted and the corrected layer cannot be considered "accurate" until the layer's design rules for the layer are examined. The polygonal transformation into new design data, shown in FIG. 25, uses relatively fine granularity during the transformation process (often the user wants to use coarser granularity). You can have points and overload some layout analysis tools, such as design rule checkers or circuit extraction tools (for example, the Dracula circuit extraction program).

In a multiple exposure mask process (e.g., double exposure (PSM)), the above mentioned inspection methods are used in automated design tools (e.g., by Numerical Technologies, Inc.). PSMShrinkIt ^™ )) can be applied in the same way, by creating the layout expected and by examining multiple exposure lithography simulations. One embodiment combines multiple exposure simulations into multiple exposure mask processes before inspection is applied. In one embodiment, simulated images from different mask layouts of a multiple exposure lithography process are merged into a given final simulated image. For example, the simulated image from the phase shifting mask and the simulated image from the trim mask can be merged (eg, added or averaged) to produce the final simulated image.

One more thing to note about the inputs to the design rule checkers and the OPD mask designs generated by the described methods is that the split geometry and grid size of the OPC shapes are a snapping of the check. Or easily adjusted by OPC design tolerance for a given size. The ability of the present invention to control grid size is important in at least two ways. First, the input to the general design rule checker and the data size of OPC designs can be reduced (eg, because there are fewer numbers of points in the polygon). If grid size is not scaled, data size can grow exponentially. Second, snapping OPC designs to any desired grid makes the mask fabrication process more convenient.

c. Conclusion

Although illustrative embodiments of the invention have been described in detail herein with reference figures, this is for understanding and is not intended to limit the invention to such precise embodiments. They are not intended to be exhaustive or to limit the invention to the precise form disclosed herein. In that position, many variations and changes become apparent to others. Accordingly, the scope of the invention is defined by the following claims and their equivalents.

Claims (10)

A method of performing design rule checking in a calibrated design that is part of a calibrated layout for an integrated circuit, the method comprising: Accessing the calibrated design; Generating a simulated image using the corrected design, wherein the simulated image corresponds to a simulation of an image to be transferred by irradiating a light source through a mask corresponding to the corrected design; And And performing design rule checking on a second image corresponding to the simulated image. 4. The method of claim 1, wherein the calibrated design includes optical proximity calibration for the calibrated design. 2. The method of claim 1, wherein the characteristics of the light source are determined by a set of photolithographic parameters. 2. The method of claim 1, wherein the simulated image is also generated using integrated circuit fabrication process characteristics. 2. The method of claim 1 wherein the second image is the simulated image. 2. The method of claim 1 wherein the second image corresponds to a polygonal representation of the contrast contour and the contrast contour corresponds to the first image. A method of generating a calibrated design corresponding to at least a portion of a calibrated layout of an integrated circuit design layout, the method comprising: Generating a simulated image from the portion, wherein the simulated image corresponds to an image that can be formed by exposing the portion to an imaging process of integrated circuit fabrication; Identifying areas to be corrected in the portion using the simulated image and one or more design rules; And Generating the calibrated design from the identified areas and the portion. 8. The method of claim 7, wherein distinguishing the areas to be corrected includes generating a second simulated image from a pre-calibrated design, the pre-calibrated design corresponding to the pre-calibrated design of the portion; And comparing the simulated image with the second simulated image to determine the regions to be corrected. 10. The method of claim 8, wherein generating the calibrated design comprises adding serifs to at least a portion of the area. 8. The method of claim 7, wherein simulating, verifying, and generating the calibrated design is iteratively performed until the calibrated design is within a preset tolerance.