KR20000075883A - An integrated circuit package including accompanying ic chip and coil and a method of production therefor - Google Patents

Abstract

An integrated circuit (IC) package is disclosed that includes a substrate layer, a coil located on a surface of the substrate layer, and an overmold layer surrounding the surface. No leads extend out of the IC package. Preferably, the substrate layer comprises a PCB. The IC package also includes a single sided encapsulated IC package. The coil preferably comprises an antenna operating in the radio frequency (RF) range. Coils mounted on the surface in a helical pattern typically follow the peripheral shape of the substrate layer surface. The IC package also includes an IC chip mounted on the surface of the substrate layer and having a plurality of bonding pads. The IC chip may be located inside, outside, or over the helical pattern. One or more underlying vias may be used, each used to connect the bonding pads to the ends of the coils. Preferably, the IC chip comprises an RF tag-type IC chip.

Description

An integrated circuit package in which an integrated circuit chip and a coil are simultaneously mounted and a method of manufacturing the same {AN INTEGRATED CIRCUIT PACKAGE INCLUDING ACCOMPANYING IC CHIP AND COIL AND A METHOD OF PRODUCTION THEREFOR}

The present invention relates to the general field of electrical engineering dealing with devices referred to by those skilled in the art as “tags”. In general terms, a tag includes a coil connected to an IC chip in a package that has no external leads. The tag uses its coil, which acts as an antenna to communicate with external devices using electromagnetic radiation transmission and / or emission from the tag. In the past, existing IC assemblies were used to generate tags. In more detail, operation will be initiated in the IC lead frame. Then, using stamping or etching techniques, the lead frame was formed in a coil-like shape, thereby creating a pseudo-coil (ie, a modified lead frame). The pseudo-coil was then connected to an IC chip. Wire bonding was required between the bonding pad of the IC chip and the end of the pseudo-coil. However, often due to how the tag is constructed, the wire lead will run over the pseudo-coil. Shortly after wire bonding, the device had to be encapsulated over the upper and lower regions of the device to fully include its internals.

There are several disadvantages associated with tags of the type described above. The first is that there are no true coils because the lead frame is altered by a stamping process, an etching process, or some other process to form a pseudo-coil. One of ordinary skill in the art, using one of these processes, to form a “coil” (ie, substantially pseudo-coil) substantially increases the likelihood of damage and destruction of the lead frame, thereby slowing down manufacturing and costing You will see that it increases. Note that for clarity, the coil is a coil, the lead frame is a lead frame, and for purposes of explanation herein, a lead frame modified to resemble a coil is referred to as a "pseudo-coil." A second disadvantage arises from the running out of one or more bonding wires on the pseudo-coil. As a result, when the device is encapsulated, the bonding wire is often shorted across the winding of the pseudo-coil, thereby rendering the device useless. The third disadvantage comes from the fact that the device starts with lead frames and IC chips. In more detail, in order to fully encapsulate the interior of the device and physically separate it from the outside world, it is necessary to encapsulate or mold the upper and lower regions of the lead frame and IC chip connections. This increases the manufacturing cost of the structure since it is more expensive to fully encapsulate and physically separate the tag with single-sided encapsulation of the upper or lower area of the device.

Accordingly, there is a need to provide an improved IC package and method of manufacturing the same that provide additional benefits and overcome the respective disadvantages described above.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the field of integrated circuit (hereinafter referred to as IC) packages and methods of manufacturing the same, and more particularly, to an IC package and a method of manufacturing the IC chip and coil mounted at the same time.

1A is a simplified exploded perspective view of an IC package.

FIG. 1B is a cross-sectional view taken along line 1A-1A of FIG. 1A showing an underlying via. FIG.

2 is a simplified plan view of the substrate layer upper surface of the IC package showing another position with respect to the IC chip of the package.

3 is a simplified plan view of the substrate layer upper surface of the IC package showing another position with respect to the IC chip of the package.

4 is a perspective view illustrating the assembled IC package of FIG. 1A with a single sided encapsulated arrangement.

FIG. 5 is a perspective view illustrating the assembled package of FIG. 1A with a double sided encapsulated arrangement. FIG.

It is an object of the present invention to provide an improved IC package and its manufacturing method.

Another object of the present invention is to provide an improved tag and a method of manufacturing the same.

Another object of the present invention is to provide an improved tag having a coil not manufactured from a lead frame and a method of manufacturing the same.

It is yet another object of the present invention to provide an improved tag having one or more underlying vias and a method of making the same.

Another object of the present invention relates to an improved tag having a coil and an IC chip mounted on a substrate and a method of manufacturing the same.

Another object of the present invention is to provide an improved tag and a method of manufacturing the same that are completely separated using single-sided encapsulation.

According to a first embodiment of the present invention, an IC package is disclosed that includes a substrate layer, a coil located on a surface of the substrate layer, and an overmolded layer surrounding the surface. No wires extend outside the IC package (ie, outside the IC package). Preferably, the substrate layer comprises a printed circuit board (hereinafter referred to as a PCB), and the IC package comprises a single sided encapsulated IC package. The coil also preferably comprises an antenna operating in the radio frequency (RF) range. Typically, the coil is mounted on the surface in a helical pattern usually along the periphery of the substrate layer surface. However, note that the coil may be mounted directly on the surface in the form of any pattern or mounted in an indentation in the surface. The IC package also includes an IC chip mounted on the surface of the substrate layer and having a plurality of bonding pads. The IC chip may be located at a portion of the boundary line surface formed by the innermost periphery of the spiral pattern. In addition, the IC chip may be located on top of the spiral pattern or on a portion of the boundary outer surface formed by the outermost periphery of the spiral pattern. A first lead is provided between the first bonding pad of the plurality of bonding pads and the first end of the coil, and a second lead is provided between the second bonding pad of the plurality of bonding pads and the second end of the coil. . The IC package also includes a first undering via included in the substrate to replace the first lead when the placement of the chip on the substrate differently forms the first lead extending over a portion of the coil, and on the substrate. A second under via is included in the substrate to replace the second lead when the placement of the IC chip differently forms a second lead extending over a portion of the coil. The phrase "stretching over a portion of a coil" herein means any part of the coil that is not one of the ends of the coil. Using an underlying via generally means using another bonding pad on the surface to operate the lead from one of the bonding pads of the IC pad. Preferably, the IC chip comprises an RF tag-type IC chip. Note that the IC package may also include a double sided encapsulated IC package. Note also that one or more coils and one or more IC chips may be implemented in the present invention.

According to another embodiment of the invention, providing a substrate layer, mounting an IC chip having a plurality of bonding pads without a lead frame on the surface of the substrate layer, and mounting a coil on the surface of the substrate layer An IC package manufacturing method is disclosed. Preferably, the substrate layer comprises a PCB. The method also includes overmolding the surface of the substrate layer to provide a single sided encapsulated IC package that does not include any leads extending out of the single sided encapsulated IC package. The method also adds an overmolding surface opposite the substrate layer located opposite the surface described above to provide a double-sided encapsulated IC package with no conductors extending out of the double-sided encapsulated IC package. It may also include significant steps. Note that the coil preferably comprises an antenna operating in the RF range. The coil may typically be mounted on the surface in a spiral pattern that typically follows the peripheral form of the substrate layer surface. However, note that the coil may be mounted directly on the surface in the form of any pattern or mounted in an indentation in the surface. The IC chip may be located at a portion of the boundary line surface formed by the innermost periphery of the spiral pattern. In addition, the IC chip may be located on top of the spiral pattern or on a portion of the boundary outer surface formed by the outermost periphery of the spiral pattern. The method also connects a first lead between the first bonding pad of the plurality of bonding pads and the first end of the coil, and between the second bonding pad of the plurality of bonding pads and the second end of the coil. Connecting the two wires. In addition, the method replaces the first lead with a first underlying via included in the substrate when the placement of the chip on the substrate differently forms the first lead that extends over a portion of the coil, and the placement of the IC chip on the substrate Replacing the second lead with a second underlying via included in the substrate when differently forming a second lead extending over a portion of the coil. Note again that the phrase "stretching over a portion of a coil" means any part of the coil that is not one of the ends of the coil. Using an underlying via generally means using another bonding pad on the surface to operate the lead from one of the bonding pads of the IC pad. Note also that one or more coils and one or more IC chips may be implemented in the present invention. Finally, note that the IC chip preferably comprises an RF tag-type IC chip.

The above and other objects, features, and advantages of the present invention will become apparent from the following, particularly from the description of the preferred embodiment of the present invention described in conjunction with the accompanying drawings.

Figure 1A discloses an integrated circuit (IC) package of the present invention, generally referred to as 10, hereinafter simply referred to as "IC package" or "package." Preferably, the package 10 includes a substrate layer 12, a coil 14 located on the surface 12a of the substrate layer 12, and an overmolded layer 16 surrounding the surface 12a. . Package 10 is generally defined as the IC package that can be most reliably, but in a preferred embodiment, package 10 includes an RF tag-type IC chip. Those skilled in the art will appreciate that RF tag-type IC chips generally include IC chips that communicate with an external transmitter / receiver in the RF range without the aid of connecting leads. In addition, those skilled in the art will appreciate that tag-type IC chips that may operate outside the RF range can be implemented in the present invention. Note that no conductors extend outside the package 10 (which can also be seen in FIGS. 4 and 5).

Referring again to FIG. 1A, element 2 is generally defined as substrate layer 12, but in a preferred embodiment, substrate layer 12 includes a PCB 12. In a single-sided encapsulated variant of package 10, no matter what surface layer or PCB 12 is implemented, no lead or conductive portion protrudes from the surface, but from surface 12a. For this reason, the single-sided encapsulated deformation of the package 10 (such as shown in FIG. 4) does not have any leads or conductive portions extending out of the package 10. If substrate layer 12 has one or more leads or conductive portions protruding from a surface other than surface 12a, a double-sided encapsulated package 64 (see FIG. 5) may be implemented. For example, in package 64 from FIG. 5, there are one or more conductors or conductive portions on the surface of substrate layer 12 located on opposite surface 12a, which overmolded layer 66 may have. If not inserted, it can make electrical contact with the outside world. However, in a preferred embodiment of the present invention, the lead or conductive portion remains only on the surface 12a of the substrate layer 12, thus encapsulating the single side of the IC package 10 (see FIGS. 1A and 4). The deformation will be sufficient to retain all of the leads or conductive portions included in the package 10. However, FIG. 5 shows a double-sided encapsulated variant that, if necessary, creates the package 64 to separate all leads or conductive portions within the package from making physical contact with everything outside the package 64. It is pointed out that this can be used in the present invention.

Referring again to FIG. 1A, the coil 14 preferably includes an antenna 14, if the package 10 operates in the RF range (ie, if the tag-type IC chip 20 of the package 10 is present). ) Operates in the RF range, the same is true of the coil or antenna 14. Those skilled in the art will appreciate that a coil, such as coil 14 in a tag, essentially acts as an antenna. The coil 14 is generally mounted on the surface 12a in a helical pattern that follows the peripheral shape of the surface 12a of the substrate layer 12. Preferably, the surface of the substrate layer 12 will be provided with a coil trace (not visible because the coil 14 is therein) that is indented into the surface 12a so that the coil 14 can be present. . The surface 12a will also have a die attach paddle 18 (ie, indentation into the surface 12a) for mounting the IC chip 20 by adhesive. Note that the IC chip 20 has a plurality of bonding paddles 22 and 24. Those skilled in the art will appreciate that the bonding pads 22, 24 are connected to portions of the IC chip 20 (not shown for clarity of the drawings) that allow for the feasibility of the package 10. Preferably, IC chip 20 comprises an RF tag-type IC chip. For clarity, an RF tag-type IC package such as package 10 in the preferred embodiment includes an RF tag-type IC chip such as IC chip 20. The coil 14 has bonding pads 26, 28 at its ends. The conductive wire 30 connects the bonding pad 22 from the IC chip 20 to one end of the coil 14 through the bonding pad 26. The other lead 32 connects the bonding pads 24 of the IC chip 20 to other bonding pads 34, which are bonded to the other side of the coil 14 using an underlying conductive via 36. It is connected to a bonding pad 28 connected to one end (see FIG. 1B).

Referring to FIG. 1B, it can be seen that the underlying via 36 connects the bonding pads 34, 28. Those skilled in the art will appreciate that an underlying via 36 may be provided in the substrate layer or PCB 12 as shown. The use of the underlying vias 36 may have connected the bonding pads 24 from the IC chip 20 to the bonding pads 28 of the coil 14 if the underlying vias 36 were not implemented. This prevents the coil 14 from shorting. Short circuits that may have occurred if the underlying vias 36 were not used result from the overmold layer 16 encapsulated across the surface 12a, thereby leading to the above-mentioned conductors for one or more coil windings. Moves potentially). Referring to FIG. 1A, note that the conductor 30 is used between the bonding pads 22, 26 because there is substantially no way for the conductor to short across the coil 14. However, conductors (not shown) directly between the bonding pads 24, 28 will probably short across the coil 14 when the package 10 is encapsulated. Thus, in order to connect the bonding pads (eg, 24) of the IC chip 20 directly to the ends of the bonding pads (eg, 28) or the coils 14, the conductors must flow out over the coils 24. Every time, it is contemplated within the scope of the present invention that the underlying via 36 will eliminate potential shorting problems. The object of the present invention will be applied regardless of the position of the IC chip 20 relative to the coil 14. For example, as shown in FIG. 1A, when the IC chip 20 is located at a portion of the surface 12a in the boundary formed by the innermost periphery of the spiral pattern of the coil, the underlying via 36 (FIG. 1B). Will be accompanied by the purpose of avoiding any potential short circuit across the coil 14.

In addition, in FIG. 2, the IC chip 20 is located in the boundary outer surface 12a region formed by the outermost periphery of the spiral pattern of the coil. In other words, the use of an underlying via (not shown) prevents all shorts across the coil 14. Similar to the embodiment of the package 10 shown in FIG. 1A, the package 10 of FIG. 2 includes a substrate layer or PCB 12 having a surface 12a. Surface 12a has an etch pattern (not shown) that generally forms a helical shape to include coil 14. A die attach paddle 18 is formed in surface 12a so that the IC chip 20 may be outside the boundary formed by the outermost periphery of the spiral pattern of the coil. One of the bonding pads 46 of the IC chip is connected to one of the ends of the coil by the bonding pad 50 and the conductive wire 48. Here, the conductive wire 48 has no possibility of shorting across the coil 14. Thus, no underlying vias are required, however, the IC chip bonding pad 38 and the coil bonding pad 44. Leads (not shown) connecting between them have the potential to short across the coil 14. Underlying vias (not shown) are used, in particular, the bonding pads 38 of the IC chip are connected to the lead wires 40. Is connected to the bonding pads 42, and the conducting wire 40 has no possibility of short circuiting through the coil 14. In this case, the bonding pads 42 are provided with the underlying vias, as shown in Fig. 1A. Will be connected to the bonding pad 44, thereby eliminating all potential short-circuit problems in this embodiment of the package 10. The package 10 here is required as well as those shown in Figs. Depending on the encapsulation, single or double.

Referring to FIG. 3, the package 10 has an IC chip 20 positioned over a spiral pattern of coils. There will also be a substrate layer or PCB 12 having a surface 12a having a pattern etched to receive the coil 14. In this case as in the other cases, the substrate shown is generally in the form of a spiral, but those skilled in the art will be able to design the coil 14 in an indented pattern having any other shape on the surface 12a within the scope of the present invention. It will be appreciated. For example, the helical pattern may not have an edge as shown (ie, the pattern may be rounded or bent). The IC chip 20 uses non-conductive adhesive materials that are well known to those skilled in the art, in order to separate the IC chip 20 from the coil 14 except for the preferred end connections described below. Will be connected to surface 12a and coil 14. In particular, one of the bonding pads 58 of the IC chip will be connected to one end of the coil 14 through the bonding pad 62 and the lead 60. The other bonding pads 52 of the IC chip 20 will be connected to the other end of the coil 14 through the bonding pads 56 and the lead 54. In this embodiment of the package 10, there is little possibility that the leads 60 or 64 are shorted across the coil 14, so no underlying vias are used. However, one or two underlying vias similar to those shown in FIG. 1B may be used to ensure against the possibility of shorting across the coil 14 by leads 60 or 54. In addition, the package 10 herein is single or double encapsulated as needed, similar to those shown in FIGS. 4 and 5.

With reference to FIGS. 4 and 5, all embodiments of the package 10 described above can be implemented using single-sided encapsulation (as shown in FIG. 4) or double-sided encapsulation (as shown in FIG. 5). Note that If the substrate layer or PCB 12 only exposed the conductors or circuits on the surface 12a, typically single-sided encapsulation by the overmold layer 160 will be used. Double sided encapsulation may not be necessary or desirable in terms of cost, since the single sided encapsulation will completely separate the interior of the package from the outside world by means of the overmolded layer 16 rather than through electromagnetic radiation. On the other hand, if the substrate layer or PCB 12 has conductors or circuits exposed on the surface 12a as well as on an additional surface (eg, opposite surface 12a), the double-sided encapsulation is a package. It will be necessary to separate 10. Here, overmold layers 16, 66 will be used on top of the substrate layer or PCB 12 to form a fully separated package 64. In other words, Built-in element of the member (64) will be accessible to the desired electromagnetic radiation to the tag operation.

action

First, a suitable substrate layer or PCB material 12 must be provided. "Suitable" depends not only on the number of coils 14 and IC chips 20 used, but also their relative positions and whether one or more sides of the substrate layer or PCB 12 have exposed conductors or circuits. . For the sake of consideration, assume the case of a single coil 14 and a single IC chip 20 having conductors or circuits exposed only on the substrate layer or surface 12a of the PCB 12. In this case, the substrate layer or PCB 12 will have a curved pattern for accommodating the coil 14 and a curved die attach paddle for accommodating the IC chip 20. In addition, depending on the position of the IC chip 20 relative to the coil 14, there may be one or more vias in the substrate layer or the PCB 12. Once again for review, assuming the case shown in FIGS. 1A and 1B, a single underlying via 36 will be provided in the substrate layer or PCB 12.

The coil 14 may be manufactured in a particular manner and then attached to the curved pattern in the surface 12a or formed in its curved pattern using deposition processes well known to those skilled in the art. Note that the curved pattern of the coil 14 may take one of several different forms, but assume again the form shown in FIG. 1A for review. To attach the IC chip 20 to the surface 12a, an adhesive will be applied to the curved die attach paddle area, and the IC chip 20 will then typically be thermally cured in place. For example, if IC chip 20 is positioned across coil 14 (see, eg, FIG. 3), a nonconductive adhesive may be needed. In this case, suitable conductors (eg, 30 and 32 of FIG. 1A) are wire bonded into place. This arrangement takes advantage of the underlying via 36 (see FIG. 1B). Finally, the substrate layer or PCB 12 will be encapsulated in a manner well known to those skilled in the art using the overmold layer 16 to form the package 10. Those skilled in the art will appreciate whether one or more coils 14 or IC chips 20 are used, whether single or double-sided encapsulation is used, and coil (s) 14 for IC chip (s) 20. Regardless of its relative position, it will be appreciated that this general approach, or a slightly modified variant thereof, may be performed to manufacture the package 10 or 64 (see FIGS. 4 and 5). The finished packages 10, 64 then operate in a manner well known to those skilled in the art of tag operation.

While the invention has been shown and described with respect to particularly preferred embodiments, it will be apparent to those skilled in the art that the foregoing and other modifications in form and detail may be made without departing from the spirit and scope of the invention. For example, as shown herein, as opposed to using a single coil 14 per package 10, a similar package 10 using one or more coils 14 can be considered, in which case one or more of them. The above IC chip 20 may be located anywhere on the surface 12a, and one or more under vias (similar to 36 in FIG. 1B) may be used.

Claims (32)

Substrate layer; A coil positioned on a surface of the substrate layer; And And an overmolded layer surrounding the surface. The IC package of claim 1 wherein no leads extend out of the IC package. The IC package of claim 1 wherein the substrate layer comprises a printed circuit board (PCB). The IC package of claim 1 wherein the IC package comprises a single sided encapsulated IC package. The IC package of claim 1 wherein the coil comprises an antenna. 6. The IC package of claim 5, wherein the antenna operates in a radio frequency (RF) range. The IC package of claim 1 wherein the coil is mounted on the surface in a helical pattern. 8. The IC package of claim 7, wherein the helical pattern generally follows a peripheral shape of the surface of the substrate layer. 8. The IC package of claim 7, further comprising an IC chip mounted on the surface of the substrate layer and having a plurality of bonding pads. 10. The IC package of claim 9, wherein the IC chip is located at a portion of the surface within a boundary formed by the innermost periphery of the spiral pattern. 10. The IC package of claim 9, wherein the IC chip is located above the spiral pattern. 10. The IC package of claim 9, wherein the IC chip is located at a portion of the surface outside the boundary formed by the outermost periphery of the spiral pattern. 10. The method of claim 9, wherein a first conductive wire is provided between the first bonding pad of the plurality of bonding pads and the first end of the coil, and the second conductive wire is connected to the second bonding pad of the plurality of bonding pads. And an IC package provided between the second ends of the coils. 10. The method of claim 9, further comprising an under via having a single connection to the coil inserted into the substrate layer and comprising a connection from a coil end of the underlying via to one of the first and second ends of the coil. Include, And the underlying via is connected to a bonding pad of one of the plurality of bonding pads at the other end of the underlying via. 14. The first underlay of claim 13, wherein an arrangement of the IC chip on the surface is included in the substrate layer to replace the first lead when differently forming the first lead extending over a portion of the coil. A via, and a second underlying via included in the substrate layer to replace the second lead when the placement of the IC chip on the surface differently forms the second lead extending over a portion of the coil. IC package comprising a. 10. The IC package of claim 9 wherein the IC chip comprises an RF tag-type IC chip. The IC package of claim 1 wherein the IC package comprises a double sided encapsulated IC package. Providing a substrate layer; Mounting an IC chip without a lead frame but having a plurality of bonding pads to the surface of the substrate layer, and And mounting a coil to the surface of the substrate layer. 19. The method of claim 18 wherein the substrate layer comprises a PCB. 19. The single sided encapsulated IC package of claim 18, further comprising overmolding the surface of the substrate layer, the single sided encapsulated IC package having no conductors extending out of the single sided encapsulated IC package. IC package manufacturing method. 21. The method of claim 20, further comprising: overmolding an opposite surface of the substrate layer positioned opposite the surface of the substrate layer, wherein the duplex is free of any conductors extending outward of the double-sided encapsulated IC package. An IC package manufacturing method comprising providing a cotton encapsulated IC package. 19. The method of claim 18 wherein the coil comprises an antenna. 23. The method of claim 22 wherein the antenna operates in a radio frequency (RF) range. 19. The method of claim 18 wherein the coil is mounted on the surface in a helical pattern. 25. The method of claim 24, wherein the spiral pattern generally follows a peripheral shape of the surface of the substrate layer. 25. The method of claim 24 wherein the IC chip is located at a portion of the surface within a boundary formed by the innermost periphery of the spiral pattern. 25. The method of claim 24 wherein the IC chip is located on the spiral pattern. 25. The method of claim 24 wherein the IC chip is located at a portion of the surface outside the boundary formed by the outermost periphery of the spiral pattern. The method of claim 18, Connecting a first lead between a first bonding pad of the plurality of bonding pads and a first end of the coil; And And connecting a second lead between a second bonding pad of the plurality of bonding pads and a second end of the coil. The method of claim 18, Providing the under via having a single connection to the coil that is included in the substrate layer and includes a connection from a coil end of the underlying via to one of a first end and a second end of the coil; And Connecting the other end of the underlying via to a bonding pad of one of the plurality of bonding pads. The method of claim 29, Replacing the first lead with a first undering via contained in the substrate when the placement of the IC chip on the surface differently forms the first lead extending over a portion of the coil; And Replacing the second lead with a second underlying via contained in the substrate when the placement of the IC chip on the surface differently forms the second lead extending over a portion of the coil. An IC package manufacturing method characterized by the above-mentioned. 19. The method of claim 18 wherein the IC chip comprises an RF tag-type IC chip.