KR20020055687A - Semiconductor package - Google Patents
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- KR20020055687A KR20020055687A KR1020000084888A KR20000084888A KR20020055687A KR 20020055687 A KR20020055687 A KR 20020055687A KR 1020000084888 A KR1020000084888 A KR 1020000084888A KR 20000084888 A KR20000084888 A KR 20000084888A KR 20020055687 A KR20020055687 A KR 20020055687A
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- heat sink
- chip
- circuit film
- wire
- grounding
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/49105—Connecting at different heights
- H01L2224/49109—Connecting at different heights outside the semiconductor or solid-state body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- Engineering & Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
Description
본 발명은 반도체 패키지에 관한 것으로서, 히트싱크가 적용된 반도체 패키지에 있어서, 반도체 칩의 그라운딩을 히트싱크에 직접 와이어로 본딩하여 이루어지도록 하되, 상기 히트싱크에 그라운딩용 솔더볼을 직접 부착하거나, 히트싱크의 모서리와 변에 접지단을 일체로 형성하여, 마더보드의 접지영역에 부착되도록 한 구조의 반도체 패키지에 관한 것이다.The present invention relates to a semiconductor package, wherein in a semiconductor package to which a heat sink is applied, the grounding of the semiconductor chip is directly bonded to the heat sink with a wire, but a grounding solder ball is directly attached to the heat sink, The present invention relates to a semiconductor package having a structure in which a ground end is integrally formed at a corner and a side thereof so as to be attached to a ground region of a motherboard.
일반적으로, 그라운딩(접지:Grounding)의 목적은 전기/전자장치로 유도되는 과전류를 차단하거나 방전시킴으로써, 전기적인 잡음을 줄이고, 전기회로 및 장치를 보호하는데 있다.In general, the purpose of the grounding (grounding) is to reduce the electrical noise, to protect the electrical circuits and devices by blocking or discharging the overcurrent induced by the electrical / electronic device.
이에, 반도체 패키지 내부의 반도체 칩도 파워용, 신호교환용 등의 전기적인 신호들이 계속 입출력되기 때문에 전기적으로 그라운딩을 해주는 것은 필수적 사항이고, 특히 반도체 칩의 전기적인 성능을 향상시킬 수 있도록 그라운딩을 여러곳에 처리해주는 것이 바람직하다.Therefore, the grounding of the semiconductor chip inside the semiconductor package is also essential since electrical signals such as power and signal exchange are continuously inputted and outputted. In particular, the grounding may be improved to improve the electrical performance of the semiconductor chip. It is desirable to treat it somewhere.
대개, 반도체 칩의 그라운딩은 반도체 패키지를 제조하기 위한 리드프레임, 인쇄회로기판, 회로필름등의 각종 부재에 와이어로 본딩하여서 이루어지는데, 상기 부재에는 그라운딩을 위한 다수개의 영역이 설계 당시부터 미리 설정되어져, 이곳으로 그라운딩용 와이어 본딩이 실시되어 이루어진다.Usually, the grounding of a semiconductor chip is performed by bonding wires to various members such as a lead frame, a printed circuit board, and a circuit film for manufacturing a semiconductor package, and a plurality of areas for grounding are set in advance from the design time. Here, the ground bonding is carried out.
한편, 동 재질의 히트싱크를 이용한 반도체 패키지의 경우에는 히트싱크를 그라운딩의 대상으로 하여, 미리 설정된 그라운딩 영역에 은도금을 해주게 된다.On the other hand, in the case of a semiconductor package using a heat sink made of the same material, the heat sink is subjected to the grounding, and silver plating is performed on the predetermined grounding region.
여기서 상기 히트싱크를 이용한 반도체 패키지와, 그라운딩 구조를 첨부한 도 8을 참조로 설명하면 다음과 같다.Herein, the semiconductor package using the heat sink and the grounding structure will be described with reference to FIG. 8.
소정의 크기와 두께를 갖으며 상면 중앙에는 칩 부착용 홈(34)이 에칭 처리에 의하여 형성된 동재질의 히트싱크(10)와; 상기 칩 부착용 홈(34)을 제외한 히트싱크(10)의 표면에 접착수단(22)으로 부착된 회로필름(18)과; 상기 히트싱크(10)의 칩 부착용 홈(34)에 접착수단(22)에 의하여 부착된 반도체 칩(20)과; 상기 반도체 칩(20)의 본딩패드와 상기 회로필름(18)의 와이어 본딩용 전도성패턴간에 연결된 와이어(24)와; 상기 반도체 칩(20)과, 와이어(24)와, 와이어 본딩용 전도성패턴등을 인캡슐레이션 하고 있는 코팅재(26)와; 상기 회로필름(18)의 인출단자 부착용 전도성패턴에 융착된 전도성의 솔더볼(32)로 구성되어 있다.A heat sink 10 of the same material having a predetermined size and thickness and having a chip attaching groove 34 formed in the center of the upper surface by etching; A circuit film 18 attached to the surface of the heat sink 10 except for the chip attaching groove 34 by an adhesive means 22; A semiconductor chip 20 attached to the chip attaching groove 34 of the heat sink 10 by an adhesive means 22; A wire 24 connected between the bonding pad of the semiconductor chip 20 and the conductive pattern for wire bonding of the circuit film 18; A coating material 26 encapsulating the semiconductor chip 20, the wire 24, and a conductive pattern for wire bonding; Consists of a conductive solder ball 32 fused to the conductive pattern for attaching the lead terminal of the circuit film 18.
이때, 상기 회로필름(18)은 베이스층으로서 절연체인 수지필름(28)과; 이 수지필름(28)상에 에칭 처리된 전도성패턴(30)과; 이 전도성패턴(30)들중 와이어 본딩용과 인출단자 부착용 전도성패턴을 노출시키면서 수지필름(28)상에 도포된 커버코트(36)로 구성되어 있다.At this time, the circuit film 18 includes a resin film 28 which is an insulator as a base layer; A conductive pattern 30 etched on the resin film 28; The conductive pattern 30 is composed of a cover coat 36 coated on the resin film 28 while exposing a conductive pattern for wire bonding and a lead terminal attachment.
특히, 상기 칩 부착용 홈(34)과 인접한 히트싱크(10)의 상면에는 그라운딩 영역이 되는 은도금부(38)가 형성되어 있어서, 상기 반도체 칩(20)의 그라운딩용 본딩패드와 상기 은도금부(38)간을 와이어(24)로 본딩함으로써, 그라운딩이 이루어진다.In particular, a silver plating part 38 serving as a grounding area is formed on an upper surface of the heat sink 10 adjacent to the chip attaching groove 34, so that the grounding bonding pad and the silver plating part 38 of the semiconductor chip 20 are formed. The bonding is performed by bonding the wires 24 with each other.
또한, 상기 솔더볼(32)중 몇개는 마더보드의 접지영역에 융착되는 그라운딩용으로 사용하게 되는데, 이 그라운딩용 솔더볼(40)과 상기 히트싱크가 서로 접촉되어야 그라운딩이 이루어지게 된다.In addition, some of the solder balls 32 are used for grounding that is fused to the ground area of the motherboard, and grounding is performed when the grounding solder balls 40 and the heat sink are in contact with each other.
따라서, 상기 그라운딩용 솔더볼(40)이 융착되는 위치와 일치되는 회로필름의 수지필름층에 히트싱크(10)면이 노출되게 비아홀(42)을 가공하여 형성하고, 이 비아홀(42)에 전도성물질(44)을 채움으로써, 상기 그라운딩용 솔더볼(40)과 히트싱크면(10)이 상기 비아홀(42)에 채워진 전도성물질(44)에 의하여 전기적으로 연결되어진다.Accordingly, the via hole 42 is formed by exposing the heat sink 10 surface to the resin film layer of the circuit film corresponding to the position where the grounding solder ball 40 is fused, and the conductive material is formed in the via hole 42. By filling the 44, the grounding solder ball 40 and the heat sink surface 10 are electrically connected by the conductive material 44 filled in the via hole 42.
이때, 상기 비아홀(42)을 통하여 노출되어 전도성물질(44)과 접촉되는 히트싱크(10)면에도 은도금부(38)가 형성된 상태이다.In this case, the silver plating part 38 is formed on the surface of the heat sink 10 exposed through the via hole 42 and in contact with the conductive material 44.
그에따라, 반도체 칩(20)의 그라운딩 신호가 와이어(24)와, 히트싱크(10)의 은도금부(38)와, 히트싱크(10)의 몸체와, 상기 비아홀(42)에 채워져 있는 전도성물질(44)과, 그라운딩용 솔더볼(40)을 차례로 거쳐서, 이 솔더볼(40)이 융착되는 마더보드(16)의 접지영역에 까지 닿음으로써, 반도체 칩(20)의 그라운딩이 이루어지게 된다.Accordingly, the grounding signal of the semiconductor chip 20 is filled with the wire 24, the silver plated portion 38 of the heat sink 10, the body of the heat sink 10, and the conductive material filled in the via hole 42. The semiconductor chip 20 is grounded by touching 44 and the grounding solder ball 40 to the ground region of the motherboard 16 to which the solder ball 40 is fused.
그러나, 상기와 같이 히트싱크를 이용한 반도체 패키지의 그라운딩 구조는 다음과 같은 문제점이 있다.However, the grounding structure of the semiconductor package using the heat sink as described above has the following problems.
첫째, 히트싱크상에 미리 은도금부를 형성한 후, 회로필름을 히트싱크상에 접착수단으로 부착할 때, 상기 은도금부와 회로필름의 비아홀을 정확하게 상하로 일치시키기 어려워 불량을 초래하는 단점이 있다.First, after the silver plated portion is formed on the heat sink in advance, when the circuit film is attached to the heat sink with adhesive means, it is difficult to exactly match the via hole of the silver plated portion and the circuit film up and down, resulting in a defect.
둘째, 상기 비아홀에 전도성물질을 채우는 공정이 들고, 그에 따른 비용이 소모되는 단점이 있다.Secondly, there is a disadvantage in that a process of filling a conductive material in the via hole takes place, and thus a cost is consumed.
셋째, 상기 은도금부와 일치되도록 회로필름에 비아홀을 형성하는 드릴링 작업은 비아홀이 매우 미세한 직경이기 때문에 작업이 매우 어려운 단점이 있다.Third, the drilling operation for forming a via hole in the circuit film to match the silver plated part has a very difficult disadvantage because the via hole is a very fine diameter.
따라서, 본 발명은 상기와 같은 점을 감안하여, 그라운딩용 솔더볼을 직접 히트싱크상에 융착시키거나, 히트싱크의 모서리 부분을 절곡시켜, 마더보드의 접지영역에 부착되도록 함으로써, 종래에 회로필름상에 별도의 비아홀을 가공하는 공정과 비아홀에 전도성물질을 채우는 공정등을 배제하여 비용을 절감하는 동시에 작업성을 향상시킬 수 있도록 한 반도체 패키지를 제공하는데 그 목적이 있다.Therefore, in view of the above, the present invention allows the grounding solder ball to be directly fused to the heat sink, or bent the corner portion of the heat sink to be attached to the grounding area of the motherboard. The purpose of the present invention is to provide a semiconductor package that can reduce work costs and improve workability by eliminating the process of processing a separate via hole and a process of filling a conductive material in the via hole.
도 1은 본 발명에 따른 반도체 패키지의 일실시예를 나타내는 단면도,1 is a cross-sectional view showing an embodiment of a semiconductor package according to the present invention;
도 2는 도 1의 그라운딩 구조가 적용된 반도체 패키지가 마더보드에 실장된 상태를 나타내는 단면도,FIG. 2 is a cross-sectional view illustrating a semiconductor package in which the grounding structure of FIG. 1 is applied to a motherboard; FIG.
도 3는 도 1의 반도체 패키지의 그라운딩 구조에 적용된 히트싱크를 나타내는 평면도,3 is a plan view illustrating a heat sink applied to the grounding structure of the semiconductor package of FIG. 1;
도 4은 본 발명에 따른 반도체 패키지의 다른 실시예를 나타내는 단면도,4 is a cross-sectional view showing another embodiment of a semiconductor package according to the present invention;
도 5는 도 4의 그라운드 구조가 적용된 반도체 패키지가 마더보드에 실장된 상태를 나타내는 단면도,5 is a cross-sectional view illustrating a semiconductor package to which a ground structure of FIG. 4 is applied to a motherboard;
도 6은 도 4의 반도체 패키지의 그라운딩 구조에 적용된 히트싱크를 나타내는 평면도,6 is a plan view illustrating a heat sink applied to the grounding structure of the semiconductor package of FIG. 4;
도 7은 도 4의 반도체 패키지를 싱귤레이션하는 과정을 보여주는 단면도,7 is a cross-sectional view illustrating a process of singulating a semiconductor package of FIG. 4;
도 8은 종래의 반도체 패키지의 그라운딩 구조를 나타내는 단면도.8 is a cross-sectional view showing a grounding structure of a conventional semiconductor package.
<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>
10 : 히트싱크12 : 은도금된 홈10: heat sink 12: silver plated groove
14 : 접지단16 : 마더보드14: ground terminal 16: motherboard
18 : 회로필름20 : 반도체 칩18: circuit film 20: semiconductor chip
22 : 접착수단24 : 와이어22: bonding means 24: wire
26 : 코팅재28 : 수지필름26 coating material 28 resin film
30 : 전도성패턴32 : 솔더볼30: conductive pattern 32: solder ball
34 : 칩 부착용 홈36 : 커버코트34: chip mounting groove 36: cover coat
100 : 반도체 패키지100: semiconductor package
상기한 목적을 달성하기 위한 본 발명은:The present invention for achieving the above object is:
상면 중앙에는 칩 부착용 홈이 형성된 히트싱크와; 상기 칩 부착용 홈을 제외한 히트싱크의 표면에 접착수단으로 부착된 회로필름과; 상기 히트싱크의 칩 부착용 홈에 접착수단에 의하여 부착된 반도체 칩과; 상기 반도체 칩의 본딩패드와 상기 회로필름의 와이어 본딩용 전도성패턴간에 연결된 와이어와; 상기 반도체 칩과, 와이어와, 와이어 본딩용 전도성패턴등을 인캡슐레이션 하고 있는 코팅재와; 상기 회로필름의 인출단자 부착용 전도성패턴에 융착된 전도성의 솔더볼로 구성되어 있는 반도체 패키지에 있어서, 상기 히트싱크의 가장자리 부분을 바깥쪽으로 연장하고, 이 연장된 히트싱크의 상면에 전도성금속이 도금된 다수개의 홈을 가공하고, 이 홈에 그라운딩용 솔더볼을 직접 융착시켜서 이루어진 것을 특징으로 한다.A heat sink having a chip attaching groove formed at the center of the upper surface thereof; A circuit film attached to the surface of the heat sink except for the chip attaching groove by adhesive means; A semiconductor chip attached to the chip attaching groove of the heat sink by an adhesive means; A wire connected between the bonding pad of the semiconductor chip and the conductive pattern for wire bonding of the circuit film; A coating material encapsulating the semiconductor chip, the wire, and the conductive pattern for wire bonding; In a semiconductor package consisting of a conductive solder ball fused to a conductive pattern for attaching the lead terminal of the circuit film, a plurality of conductive metal plated on the upper surface of the extended heat sink extending outwardly the edge portion of the heat sink The grooves are processed, and the grounding solder balls are directly fused to the grooves.
상기 전도성금속은 은을 사용하는 것이 바람직하다.The conductive metal is preferably silver.
바람직한 구현예로서, 상기 그라운딩용 솔더볼 대신에 히트싱크의 모서리와 변에는 위쪽으로 이중 절곡된 다수개의 접지단이 일체로 성형된 것을 특징으로 한다.In a preferred embodiment, instead of the grounding solder ball, a plurality of ground ends, which are double bent upwards, are integrally formed at edges and sides of the heat sink.
이에, 상기 반도체 패키지의 그라운딩은 상기 그라운딩용 솔더볼과 상기 접지단은 마더보드의 접지영역에 부착되어 이루어진다.Thus, the grounding of the semiconductor package is made of the grounding solder ball and the ground end is attached to the ground region of the motherboard.
여기서 본 발명의 실시예를 첨부한 도면에 의거하여 보다 상세하게 설명하면 다음과 같다.Hereinafter, the embodiments of the present invention will be described in detail with reference to the accompanying drawings.
첨부한 도 3은 본 발명에 적용되는 히트싱크를 나타내는 단면도로서, 상기히트싱크(10)는 다수개가 스트립 단위로 프레임(46)에 연결된 상태로서, 각각의 모서리 부분이 프레임(46)과 연결되어 있고, 그 중앙면에는 반도체 칩 부착용 홈(34)이 에칭에 의하여 형성되어 있다.3 is a cross-sectional view illustrating a heat sink applied to the present invention, wherein the heat sink 10 is connected to the frame 46 in a plurality of strips, and each corner portion thereof is connected to the frame 46. In the center surface, grooves 34 for attaching semiconductor chips are formed by etching.
특히, 상기 히트싱크(10)의 가장자리면에는 다수개의 홈(12)이 가공되는데, 이 홈(12)의 표면을 전도성의 금속을 도금하되, 전도성이 우수한 은을 사용하여 도금하는 것이 바람직하다.In particular, a plurality of grooves 12 are processed on the edge surface of the heat sink 10. The surface of the grooves 12 is preferably plated with a conductive metal, but using a silver having excellent conductivity.
이때, 상기 홈(12)의 가공방법은 에칭(Etching) 또는 스탬핑(Stamping) 방법을 사용하여 가공하는 것이 바람직하다.At this time, it is preferable that the groove 12 is processed by using an etching or stamping method.
여기서, 상술한 구조의 히트싱크를 이용하여 제조된 반도체 패키지를 첨부한 도 1을 참조로 설명한다.Here, the semiconductor package manufactured using the heat sink having the above-described structure will be described with reference to FIG. 1.
먼저, 상기 칩 부착용 홈(34)이 에칭 처리에 의하여 형성된 동재질의 히트싱크(10)상에 회로필름(18)을 접착수단(22)으로 부착하되, 상기 칩 부착용 홈(34)과 은도금된 홈(12)이 형성되어 있는 가장자리면을 제외하고 부착시킨다.First, the chip attaching groove 34 attaches the circuit film 18 to the heat sink 10 of the same material formed by the etching process with the adhesive means 22, and the chip attaching groove 34 and silver plated. Except the edge surface where the groove 12 is formed is attached.
다음으로, 상기 히트싱크(10)의 칩 부착용 홈(34)에 접착수단(22)으로 반도체 칩(20)을 부착하고, 상기 반도체 칩(20)의 본딩패드와 상기 회로필름(18)의 와이어 본딩용 전도성패턴간에 파워용과 신호교환용등으로 사용되는 와이어(24)를 연결시킨다.Next, the semiconductor chip 20 is attached to the chip attaching groove 34 of the heat sink 10 by the adhesive means 22, and the bonding pad of the semiconductor chip 20 and the wire of the circuit film 18 are attached thereto. The wire 24 used for power and signal exchange is connected between the conductive patterns for bonding.
또한, 상기 칩 부착용 홈(34)과 인접한 히트싱크(10)의 상면에는 그라운딩 영역이 되는 은도금부(38)가 형성되어 있는 바, 상기 반도체 칩(20)의 그라운딩용 본딩패드와 상기 히트싱크(10)의 은도금부(38)간을 그라운드용 와이어(24)로 연결시킨다.In addition, a silver plating part 38 serving as a grounding area is formed on an upper surface of the heat sink 10 adjacent to the chip attaching groove 34. The bonding pad for grounding the semiconductor chip 20 and the heat sink ( The silver plating parts 38 of 10 are connected with the ground wire 24.
다음으로, 상기 반도체 칩(20)과, 와이어(24)와, 와이어 본딩용 전도성패턴등을 코팅재(26)로 인캡슐레이션하는 단계를 진행시키게 된다.Next, the step of encapsulating the semiconductor chip 20, the wire 24, and the conductive pattern for wire bonding with the coating material 26 is performed.
마직막으로, 상기 회로필름(18)의 인출단자 부착용 전도성패턴에 전도성의 솔더볼(32)을 융착시키는 단계를 진행하게 되는데, 상기 히트싱크상의 은도금된 홈(12)에도 그라운딩용 솔더볼(40)을 직접 융착시키게 된다.Finally, the step of fusing the conductive solder ball 32 to the conductive pattern for attaching the lead terminal of the circuit film 18 is carried out, and the grounding solder ball 40 is directly applied to the silver plated groove 12 on the heat sink. Fused.
이때, 상기 은도금된 홈(12)에 융착된 그라운딩용 솔더볼(40)은 상기 회로필름(18)의 인출단자 부착용 전도성패턴에 융착된 솔더볼의 크기보다 큰 것을 융착시키되, 회로필름(18)의 두께만큼 큰 것을 융착시켜서, 상단끝이 다른 솔더볼(32)들의 최대 높이와 평행을 이루도록 한다.At this time, the grounding solder ball 40 fused to the silver-plated groove 12 is fused to larger than the size of the solder ball fused to the conductive pattern for attaching the lead terminal of the circuit film 18, the thickness of the circuit film 18 As large as possible, the upper end is parallel to the maximum height of the other solder balls (32).
상기와 같이 제조된 반도체 패키지(100)를 마더보드(16)에 실장하게 되면, 첨부한 도 2에 도시한 바와 같이 상기 그라운딩용 솔더볼(40)이 마더보드(16)의 접지영역에 부착되어진다.When the semiconductor package 100 manufactured as described above is mounted on the motherboard 16, the grounding solder ball 40 is attached to the ground region of the motherboard 16 as shown in FIG. 2. .
이에따라, 상기 반도체 칩(20)의 그라운딩 신호는 그라운딩용 와이어(24)와, 상기 히트싱크(10)의 은도금부(38)와, 히트싱크(10)의 몸체와, 상기 은도금된 홈(12)과, 상기 그라운딩용 솔더볼(40)을 거쳐, 이 그라운딩용 솔더볼(40)이 융착된 마더보드(16)의 접지영역에서 그라운딩 처리가 된다.Accordingly, the grounding signal of the semiconductor chip 20 is the grounding wire 24, the silver plating part 38 of the heat sink 10, the body of the heat sink 10, and the silver plated groove 12. Then, the grounding process is performed in the ground area of the motherboard 16 to which the grounding solder ball 40 is fused through the grounding solder ball 40.
여기서 첨부한 도 4 내지 도 6을 참조로 본 발명에 따른 반도체 패키지의 다른 실시예를 설명하면 다음과 같다.Hereinafter, another embodiment of the semiconductor package according to the present invention will be described with reference to FIGS. 4 to 6.
첨부한 도 6은 본 발명에 적용되는 또 다른 구조의 히트싱크를 나타내는 단면도로서, 상기 히트싱크(10)는 다수개가 스트립 단위로 프레임에 연결된 상태로서, 각각의 모서리 부분과 변에는 소정의 길이를 갖는 접지단(14)이 일체로 형성되어 프레임(46)과 연결되어 있고, 그 중앙면에는 반도체 칩 부착용 홈(34)이 형성되어 있다.6 is a cross-sectional view showing a heat sink of another structure applied to the present invention, the heat sink 10 is a state in which a plurality of heat sinks are connected to the frame in units of strips, each corner portion and side has a predetermined length The ground end 14 which is provided is integrally formed and connected to the frame 46, and a groove 34 for attaching the semiconductor chip is formed in the center surface thereof.
여기서, 상술한 구조의 또 다른 히트싱크를 이용하여 제조된 반도체 패키지를 첨부한 도 4를 참조로 설명한다.Here, the semiconductor package manufactured by using another heat sink having the above-described structure will be described with reference to FIG. 4.
먼저, 상기 칩 부착용 홈(34)이 에칭 처리에 의하여 형성된 동재질의 히트싱크(10)상에 회로필름(18)을 부착하고, 상기 히트싱크(10)의 칩 부착용 홈(34)에 접착수단(22)으로 반도체 칩(20)을 부착하며, 상기 반도체 칩(20)의 본딩패드와 상기 회로필름(18)의 와이어 본딩용 전도성패턴간에 파워용과 신호교환용등으로 사용되는 와이어(24)를 본딩하는 단계를 진행시킨다.First, the chip attaching groove 34 attaches the circuit film 18 to the same heat sink 10 formed by etching, and attaches the chip 34 to the chip attaching groove 34 of the heat sink 10. The semiconductor chip 20 is attached to the wire 22, and a wire 24 used for power and signal exchange is connected between the bonding pad of the semiconductor chip 20 and the conductive pattern for wire bonding of the circuit film 18. Proceed with the bonding step.
물론, 상기 칩 부착용 홈(34)과 인접한 히트싱크(10)의 상면에 형성된 은도금부(38)와, 상기 반도체 칩의 그라운딩용 본딩패드간에도 그라운드용 와이어(24)를 연결시킨다.Of course, the ground wire 24 is also connected between the silver plating portion 38 formed on the upper surface of the heat sink 10 adjacent to the chip attaching groove 34 and the grounding bonding pad of the semiconductor chip.
다음으로, 상기 반도체 칩(20)과, 와이어(24)와, 와이어 본딩용 전도성패턴등을 코팅재(26)로 인캡슐레이션하는 단계를 진행한 다음, 상기 회로필름(18)의 인출단자 부착용 전도성패턴에 전도성의 솔더볼(32)을 융착시키는 단계를 진행하게 된다.Next, the step of encapsulating the semiconductor chip 20, the wire 24, the conductive pattern for wire bonding, etc. with the coating material 26, and then the conductive material for attaching the lead terminal of the circuit film 18 A conductive solder ball 32 is fused to the pattern.
마지막으로, 상기와 같이 제조된 반도체 패키지를 싱귤레이션하는 공정을 진행하게 되는데, 첨부한 도 7에 도시한 바와 같이 상기 접지단(14)을 상방향으로 이중 절곡시킨 후, 그 끝단을 펀칭수단(48)으로 절단하여 줌으로써, 첨부한 도 4와 같은 구조의 반도체 패키지(200)로 제조된다.Lastly, a process of singulating the semiconductor package manufactured as described above is performed. As shown in FIG. 7, the double end of the ground end 14 is bent upwards, and the end of the semiconductor package is punched. 48), the semiconductor package 200 is manufactured as shown in FIG.
한편, 상기와 같이 제조된 반도체 패키지(200)를 마더보드(16)에 실장하게 되면, 첨부한 도 5에 도시한 바와 같이 상기 히트싱크(10)의 접지단(14)이 마더보드(16)의 접지영역에 부착되어진다.Meanwhile, when the semiconductor package 200 manufactured as described above is mounted on the motherboard 16, the ground end 14 of the heat sink 10 is attached to the motherboard 16 as shown in FIG. 5. It is attached to the ground area of.
이에따라, 상기 반도체 칩(20)의 그라운딩 신호는 그라운딩용 와이어(24)와, 상기 히트싱크(10)의 은도금부(38)와, 히트싱크(10)의 몸체와, 상기 접지단(14)을 거쳐, 이 접지단(14)이 부착된 마더보드(16)의 접지영역에서 그라운딩 처리가 된다.Accordingly, the grounding signal of the semiconductor chip 20 is connected to the grounding wire 24, the silver plating part 38 of the heat sink 10, the body of the heat sink 10, and the ground end 14. Then, the grounding process is performed in the ground area of the motherboard 16 to which the ground end 14 is attached.
이상에서 본 바와 같이, 본 발명에 따른 반도체 패키지의 그라운드 구조에 의하면, 히트싱크상에 그라운딩용 솔더볼을 직접 융착시키거나, 히트싱크의 모서리와 변에 상향 절곡된 접지단을 일체로 형성하여 마더보드에 부착되도록 함으로써,종래에 히트싱크를 포함하는 반도체 패키지의 그라운드 구조에서 회로필름상에 별도의 비아홀을 형성하는 공정과 비아홀에 전도성물질을 채우는 공정등을 배제하여 그에따른 비용을 절감할 수 있는 장점을 제공하게 된다.As described above, according to the ground structure of the semiconductor package according to the present invention, the grounding solder ball is directly fused on the heat sink, or the motherboard is formed by integrally forming a ground end bent upward at the corners and sides of the heat sink. It is possible to reduce the cost by eliminating the process of forming a separate via hole on the circuit film and the process of filling the conductive material in the via hole in the ground structure of the semiconductor package including the heat sink. Will be provided.
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| KR100723497B1 (en) * | 2005-08-11 | 2007-06-04 | 삼성전자주식회사 | Substrate having a different surface treatment in solder ball land and semiconductor package including the same |
| US7317247B2 (en) | 2004-03-10 | 2008-01-08 | Samsung Electronics Co., Ltd. | Semiconductor package having heat spreader and package stack using the same |
| CN113725181A (en) * | 2020-03-27 | 2021-11-30 | 矽磐微电子(重庆)有限公司 | Chip packaging structure |
| CN113725180A (en) * | 2020-03-27 | 2021-11-30 | 矽磐微电子(重庆)有限公司 | Chip packaging structure and manufacturing method thereof |
| CN113725089A (en) * | 2020-03-27 | 2021-11-30 | 矽磐微电子(重庆)有限公司 | Manufacturing method of chip packaging structure |
| CN113725182A (en) * | 2020-03-27 | 2021-11-30 | 矽磐微电子(重庆)有限公司 | Chip packaging structure |
| CN113725088A (en) * | 2020-03-27 | 2021-11-30 | 矽磐微电子(重庆)有限公司 | Manufacturing method of chip packaging structure |
| CN113725183A (en) * | 2020-03-27 | 2021-11-30 | 矽磐微电子(重庆)有限公司 | Chip packaging structure and manufacturing method thereof |
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| US7317247B2 (en) | 2004-03-10 | 2008-01-08 | Samsung Electronics Co., Ltd. | Semiconductor package having heat spreader and package stack using the same |
| KR100723497B1 (en) * | 2005-08-11 | 2007-06-04 | 삼성전자주식회사 | Substrate having a different surface treatment in solder ball land and semiconductor package including the same |
| CN113725088A (en) * | 2020-03-27 | 2021-11-30 | 矽磐微电子(重庆)有限公司 | Manufacturing method of chip packaging structure |
| CN113725180A (en) * | 2020-03-27 | 2021-11-30 | 矽磐微电子(重庆)有限公司 | Chip packaging structure and manufacturing method thereof |
| CN113725089A (en) * | 2020-03-27 | 2021-11-30 | 矽磐微电子(重庆)有限公司 | Manufacturing method of chip packaging structure |
| CN113725182A (en) * | 2020-03-27 | 2021-11-30 | 矽磐微电子(重庆)有限公司 | Chip packaging structure |
| CN113725181A (en) * | 2020-03-27 | 2021-11-30 | 矽磐微电子(重庆)有限公司 | Chip packaging structure |
| CN113725183A (en) * | 2020-03-27 | 2021-11-30 | 矽磐微电子(重庆)有限公司 | Chip packaging structure and manufacturing method thereof |
| CN113725183B (en) * | 2020-03-27 | 2024-02-27 | 矽磐微电子(重庆)有限公司 | Chip packaging structure and manufacturing method thereof |
| CN113725088B (en) * | 2020-03-27 | 2024-02-27 | 矽磐微电子(重庆)有限公司 | Manufacturing method of chip packaging structure |
| CN113725182B (en) * | 2020-03-27 | 2024-02-27 | 矽磐微电子(重庆)有限公司 | Chip packaging structure |
| CN113725180B (en) * | 2020-03-27 | 2024-02-27 | 矽磐微电子(重庆)有限公司 | Chip packaging structure and manufacturing method thereof |
| CN113725089B (en) * | 2020-03-27 | 2024-02-27 | 矽磐微电子(重庆)有限公司 | Manufacturing method of chip packaging structure |
| CN113725181B (en) * | 2020-03-27 | 2024-02-27 | 矽磐微电子(重庆)有限公司 | Chip packaging structure |
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| KR100649878B1 (en) | 2006-11-24 |
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