KR20000065437A - Method of Forming a Plenty of Contact Structures Having Different Contact Hole Depth - Google Patents

Abstract

PURPOSE: A method for manufacturing a plurality of contact structures having different depths is provided to guarantee stable contact resistance in contacting a gate electrode and a conductive material, and to prevent a second layer material of a multi-layered gate electrode from being severely recessed in forming a contact hole. CONSTITUTION: Contact holes exposing a plurality of conductive regions except a contact hole exposing a gate electrode(34) are simultaneously formed. A plurality of plugs respectively filling the contact holes are formed. A contact hole exposing the gate electrode is formed. A conductive layer pattern for filling up the contact hole exposing the gate electrode is formed while conductive layer patterns respectively connected to the plugs are formed.

Description

Method of Forming a Plenty of Contact Structures Having Different Contact Hole Depth}

In the process of manufacturing a semiconductor device, a plurality of contact holes having different depths may be formed simultaneously. For example, a bit line contact pad 16 formed on the semiconductor substrate 10 and self-aligned by the gate electrode 14 and the sidewall spacers 15 as shown in FIG. 1 (Self-Aligned Contact Pad). In the interlayer insulating film 17, contact holes 18, 19 and 20 exposing SAC PAD, the active region 12 into which conductive impurities are introduced, and the gate electrode 14 are simultaneously formed. At this time, since the depths of the contact holes 18, 19, and 20 are different from each other, the upper portion of the gate electrode 14 may be formed while the contact hole 19 exposing the deepest active region 12 is completed. 14b) also cannot withstand etching and is etched to form a recess 21.

In general, the gate electrode 14 is formed of a polyside structure. In the polyside structure, the lower layer of the gate electrode is formed of the polysilicon layer 14a, and the silicide layer 14b (eg, WSix, TiSix, CoSix, etc.) is formed on the polysilicon layer 14a. The silicide film 14b is formed to lower the resistance of the gate electrode. However, as shown in FIG. 1, when the recess 21 is formed in the upper silicide layer 14b of the gate electrode 14 when the contact hole 20 exposing the gate electrode 14 is formed, the following problem occurs. This happens.

After forming the plurality of contact holes 18, 19, and 20, the ohmic layer 22 and the barrier layer are respectively formed in the contact holes 18, 19, and 20, respectively. 24 and the conductive film pattern 26 (e.g., tungsten pattern) are formed in this order. After completing the conductive layer pattern 26 having the contact structures having different depths, various processes are performed to complete the semiconductor device, and among these various processes, a heat treatment process (for example, a COB (capacitor over bit-line) structure) is performed. Capacitor formation process). However, during the subsequent heat treatment process, impurities in the conductive film pattern (for example, fluorine in the case of tungsten pattern) diffuse into the lower film (for example, the ohmic film 22 or the silicide film 14b) to deteriorate the contact resistance. Such deterioration of the contact resistance becomes more severe when a recess occurs in the upper silicide layer 14b of the gate electrode 14. However, when a plurality of contact structures having different depths are formed according to the related art, depths for forming contact structures on the SAC PAD 16, the active region 12, and the upper portion of the gate electrode 14b are different from each other. Since the contact holes 18, 19, and 20 are formed at the same time, the optimization of the process for minimizing the recess of the silicide layer 14b and minimizing the degradation of the contact resistance is recognized as a problem in the semiconductor industry.

An object of the present invention is to provide a method for minimizing deterioration of contact resistance when forming a plurality of contact structures having different depths in manufacturing a semiconductor device, particularly a DRAM.

Another technical problem to be solved by the present invention is to minimize the recesses seen in the etching process for forming a contact hole in a silicide film mainly used as a second layer film in a multi-layered gate electrode, particularly a two-layered gate electrode. To provide a way.

1 to 2 are cross-sectional views illustrating a method of forming a plurality of contact structures having different depths according to the prior art.

3 to 8 are cross-sectional views illustrating a method of forming a plurality of contact structures having different depths according to a preferred embodiment of the present invention.

In order to achieve the above technical problem, a method of forming a plurality of contact structures each having a different depth and contacting a gate electrode and a plurality of conductive regions in a predetermined region on a semiconductor substrate of the present invention proceeds as follows.

Contact holes exposing the plurality of conductive regions are formed simultaneously except for the contact holes exposing the gate electrode. Subsequently, after forming a plurality of plugs respectively filling the contact holes, a contact hole exposing the gate electrode is formed. Lastly, conductive layer patterns filling the contact holes exposing the gate electrode and conductive layer patterns respectively connected to the plugs are simultaneously formed. The plurality of conductive regions may be active regions in which bit line contact plugs and conductive impurities are introduced.

Before forming the plurality of plugs, forming an ohmic film on the bottom of the contact holes, and forming a barrier film for the conductive material constituting the plugs on each inner surface of the contact holes where the ohmic film is formed. It can be provided.

After forming the contact hole exposing the gate electrode, forming an ohmic layer on a bottom surface of the contact hole exposing the gate electrode and the conductive layer pattern on an inner surface of the contact hole exposing the gate electrode on which the ohmic layer is formed. The method may further include forming a barrier film for the conductive material constituting the same.

The gate electrode may be formed of a polyside film, a titanium silicide film, or a tungsten film. The plugs and the conductive layer patterns may be formed using tungsten.

Hereinafter, a method of forming a plurality of contact structures having different depths and a semiconductor device manufactured by the method will be described in detail with reference to the accompanying drawings. However, embodiments of the present invention may be modified in many different forms, and the scope of the present invention should not be construed as being limited to the embodiments described below. The following description with reference to the drawings is provided to more completely explain the present invention to those of ordinary skill in the art related to the present invention. In the drawings, the thicknesses of layers or regions are exaggerated for clarity. In the drawings like reference numerals refer to like elements. In addition, where a layer is described as being on top of another layer or substrate, the layer may be present directly on top of the other layer or substrate, with a third layer interposed therebetween.

Referring to FIG. 3, the active region 32, the gate electrode 34, the sidewall spacer 35, and the self-aligned bit line contact pads in which conductive impurities are introduced into a predetermined portion of the semiconductor substrate 10 may be used. (Hereinafter referred to as SAC PAD) 36, and an insulating film 37 is formed thereon to a predetermined thickness. The SAC PAD 36 may preferably be polysilicon or a conductive material. The insulating layer 37 may be silicon oxide, silicon nitride, or silicon oxy nitride. The active region 32 may be a source or a drain implanted with an n-type or p-type impurity. The three gate electrodes 34 may have a multilayer structure. Preferably, the first layer is a polysilicon film, and the second layer has a polyside structure made of a silicide film.

The insulating layer 37 is patterned using a predetermined photolithography technique to form the first contact hole 38 and the second contact hole 39.

A lower end of the first contact hole 38 exposes the SAC PAD 36, and a lower end of the second contact hole 39 exposes the active region 32 on the semiconductor substrate 10.

Referring to FIG. 4, an ohmic layer 42 is formed on the surface of the SAC PAD 36 and the surface of the active region 32 exposed by the first contact hole 38 and the second contact hole 39. A wiring material barrier film 44 is formed on the ohmic film 42. Subsequently, the wiring material 46, for example tungsten, is filled in the first contact hole 38 and the second contact hole 39. Before filling and filling the wiring material 46, the transition metal film (eg, titanium or cobalt) and the wiring material barrier film may be sequentially formed without sequentially forming the ohmic layer and the wiring material barrier film. The ohmic film is preferably formed of a silicide film, such as a titanium silicide film (hereinafter referred to as TiSix) or a cobalt silicide film (hereinafter referred to as CoSix).

The wiring material barrier film may be formed of a titanium nitride (TiN) single film or a double film of titanium (Ti) and TiN film.

Referring to FIG. 5, the wiring material plug 48 is formed in the first contact hole 38 and the second contact hole 39 by planarizing the surface by removing unnecessary wiring material on the upper surface 50 of the insulating film 37. Form. The planarization step can be preferably carried out through the method of CMP or etch back.

Referring to FIG. 6, a photolithography process is performed on the resultant product of FIG. 5 to form a third contact hole 52 exposing an upper portion of the gate electrode 34.

Referring to FIG. 7, an ohmic layer 42 is formed on an upper surface of the gate electrode 34 exposed by the third contact hole 52, and then a wiring material barrier layer 44 is formed.

The ohmic film is preferably formed of a silicide film, such as a TiSix or CoSix film.

The wiring material barrier layer may be formed of a single TiN layer or a double layer of a Ti layer and a TiN layer. Subsequently, a wiring material layer 54 filling the third contact hole 52 may be formed on the leading edge layer 37. To form.

Referring to Fig. 8, the wiring material film 54 is patterned to complete the bit line 56. The present invention can be applied to the case where the gate electrode is formed of TiSix or tungsten having low resistance.

According to the present invention, only the contact hole exposing the gate electrode among the plurality of contact holes is formed separately from the other contact holes. Therefore, the recesses in the upper portion of the gate electrode, which occurred when the plurality of contact holes are simultaneously patterned, are prevented. At this time, to simplify the process, the other contact holes are filled with plugs, and the final wiring forming process is performed in one process.

In addition, when forming the gate electrode 34 TiSix, in addition to minimizing the recess, the following effects are obtained.

In the method for forming a contact structure having a different depth according to the present invention, a first contact hole 38 and a second contact hole 39 are formed in the active region 32 and the SAC PAD 36 (see FIG. 3). Before the ohmic film 42 is formed, cleaning is performed to obtain a stable ohmic film. However, since the third contact hole 52 (see FIG. 6) exposing the upper portion of the gate electrode 34 is not yet formed during the cleaning, the gate electrode is consumed or undercut during the cleaning process. ) Can be prevented from occurring. In particular, when TiSix is a gate electrode, the process step of forming an ohmic film for stabilizing contact with tungsten can be omitted, thereby providing an advantage of reducing the number of processes.

In addition, when the present invention is applied when the gate electrode 34 is formed of tungsten, there are side effects as follows.

When the gate electrode 34 is formed of tungsten, a transition metal (eg, Ti) is deposited to form a stable ohmic layer, particularly a silicide layer (eg, TiSix) while the third contact hole 52 is open. In addition, when a process of removing the unreacted transition metal that does not change into the silicide film is performed after the silicide reaction, tungsten, which is a material constituting the gate electrode, is severely consumed. However, if the third contact hole is closed during the series of processes for forming the ohmic layer, the problem that the tungsten gate electrode is consumed will not occur.

Although the present invention has been described in detail through the above embodiments, the present invention is not limited thereto, and modifications and improvements of the present invention may be made with ordinary knowledge in the art within the technical idea of the present invention.

In the manufacture of a semiconductor device, especially a DRAM, if a contact structure having a different depth is formed, the contact resistance of the gate electrode and the conductive material can be stably secured, and the multilayer gate electrode, in particular, two layers It is possible to prevent the second layer material of the gate electrode from being severely recessed in the etching process of forming the contact hole.

Even when the gate electrode is formed of TiSix or tungsten, the present invention can minimize the recesses during the consumption, undercut and etching processes of the gate electrode material. In particular, when the gate electrode is formed of TiSix, the number of steps can be reduced.

Claims (3)

A method of forming a plurality of contact structures having different depths in predetermined regions of a semiconductor substrate and contacting the gate electrodes and the plurality of conductive regions, respectively, Simultaneously forming contact holes exposing the plurality of conductive regions except for the contact holes exposing the gate electrode; Forming a plurality of plugs respectively filling the contact holes; Forming a contact hole exposing the gate electrode; And simultaneously forming conductive layer patterns filling the contact holes exposing the gate electrode and conductive layer patterns connected to the plugs, respectively. The method of claim 1, wherein the plurality of conductive regions are active regions in which bit line contact pads and conductive impurities are introduced. Before forming the plurality of plugs, Forming ohmic films on the bottoms of the contact holes, respectively; And Forming a barrier film for the conductive material constituting the plugs on each inner surface of the contact holes in which the ohmic film is formed, After forming the contact hole exposing the gate electrode, Forming an ohmic layer on a bottom surface of the contact hole exposing the gate electrode; and And forming a barrier film for the conductive material constituting the conductive film pattern on an inner surface of the contact hole exposing the gate electrode on which the ohmic film is formed. Way. The method of claim 1, wherein the gate electrode is made of a polyside film, a titanium silicide film, or a tungsten film.