KR100487511B1 - A method of fabricating semiconductor device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device which can simplify the process step and reduce the chip size. The present invention relates to insulating films on both sidewalls of a bit line pattern formed by etching a first conductive layer using a bit line forming mask. Bit line spacers are formed. After the second insulating film is formed on the first insulating film including the bit line, the second insulating film and the first insulating film are sequentially etched using the contact hole forming mask to form the storage electrode pad forming contact hole, and the second insulating film The bit line contact holes are formed such that the etched sidewalls of the bit lines are exposed in the bit line contact holes by sequentially etching the bit lines and the first insulating layer. According to the method of manufacturing a semiconductor device, the gate electrode and the bit line are sequentially formed, and then the bit line contact and the storage electrode contact pad are simultaneously or sequentially formed, thereby reducing the planarization of the interlayer insulating film. In addition, when the storage electrode contact hole is formed, the thickness of the insulating layer is reduced to prevent unetch of the contact hole, corrosion of the upper opening area, and the like when using a budlessless concept. The tab area formed on the layout may be omitted for overlap with the chip, and thus the layout area may be reduced to reduce the chip size.

Description

A manufacturing method of a semiconductor device {A METHOD OF FABRICATING SEMICONDUCTOR DEVICE}

The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a bit line contact and a contact pad forming method of a semiconductor device.

As the DRAM semiconductor device becomes more integrated, the size of the contact hole opening is reduced when the contact hole is formed due to the reduction of the critical dimension and the layout area, and the thickness of the interlayer insulating film on which the contact is formed is rather increased. do.

Therefore, various problems are caused due to the high aspect ratio in forming the contact hole. For example, in a DRAM cell process having a capacitor over bitline (COB) structure, when forming a storage electrode contact hole after bit line formation and a metal contact for wiring after cell storage electrode formation, contact etching becomes difficult due to an increase in aspect ratio. do. This is not only a process realization itself, but also increases the thickness of the photoresist film serving as a mask as the etching depth increases, making patterning difficult.

In addition, problems such as a lack of overlap margin between the storage electrode polysilicon and the contact in the cell storage electrode contact and a lack of an overlap margin between the wiring metal film and the contact occur due to corrosion in the upper opening area of the contact. As a result, these problems result in an increase in layout area and chip size.

SUMMARY OF THE INVENTION The present invention has been proposed to solve the above-mentioned problems, and an object thereof is to provide a method of manufacturing a semiconductor device capable of simplifying the process and reducing chip size.

(Configuration)

According to the present invention for achieving the above object, a manufacturing method of a semiconductor device comprises the steps of: forming a first insulating film on a semiconductor substrate on which an element is formed; Forming a first conductive film for forming a bit line on the first insulating film; Etching the first conductive layer using a bit line forming mask to form a bit line pattern; Forming a bit line spacer with an insulating film on both sidewalls of the bit line pattern; Forming a second insulating film on the first insulating film including the bit line; The second insulating layer and the first insulating layer are sequentially etched using a contact hole forming mask to form a storage electrode pad forming contact hole, and the second insulating layer, the bit line, and the first insulating layer are sequentially etched to form a bit line contact. Forming a hole, wherein the etched sidewall of the bit line is exposed in a contact hole; Filling the bit line contact hole and the pad forming contact hole with a second conductive layer to form a bit line contact and a storage electrode contact pad; Forming a third insulating film on the second insulating film including the bit line contact hole and a pad; Forming a storage electrode contact hole by etching the third insulating layer until the surface of the pad is exposed using a contact hole forming mask.

(Action)

Referring to FIGS. 1, 3C, and 4C, a novel semiconductor device manufacturing method according to an embodiment of the present invention may include both sidewalls of a bit line pattern formed by etching a first conductive layer using a bit line forming mask. The bit line spacers are formed in the insulating film. After the second insulating film is formed on the first insulating film including the bit line, the second insulating film and the first insulating film are sequentially etched using the contact hole forming mask to form the storage electrode pad forming contact hole, and the second insulating film The bit line contact holes are formed such that the etched sidewalls of the bit lines are exposed in the bit line contact holes by sequentially etching the bit lines and the first insulating layer. According to the method of manufacturing a semiconductor device, the gate electrode and the bit line are sequentially formed, and then the bit line contact and the storage electrode contact pad are simultaneously or sequentially formed, thereby reducing the planarization of the interlayer insulating film. In addition, when the storage electrode contact hole is formed, the thickness of the insulating layer is reduced to prevent unetch of the contact hole, corrosion of the upper opening area, and the like when using a budlessless concept. The tab area formed on the layout may be omitted for overlap with the chip, and thus the layout area may be reduced to reduce the chip size.

(Example)

Hereinafter, embodiments of the present invention will be described in detail with reference to FIGS. 1, 2A to 2F, 3A to 3F, and 4A to 4F.

1 is a layout of a method of manufacturing a semiconductor device according to an embodiment of the present invention, and FIGS. 2A to 2F are flowcharts sequentially showing processes of the method of manufacturing a semiconductor device according to an embodiment of the present invention, respectively. A cross section taken along the AA 'line.

3A to 3F are sequential flowcharts illustrating processes of a method of manufacturing a semiconductor device according to an exemplary embodiment of the present invention, each of which is a cross-sectional view taken along the line BB ′ of FIG. 1, and FIGS. 4A to 4F. 1 is a flowchart sequentially illustrating processes of a method of manufacturing a semiconductor device, according to an embodiment of the present invention, respectively, taken along line CC ′ of FIG. 1.

Referring to FIG. 1, in the layout of the semiconductor device of the present invention, a plurality of bar-shaped active patterns 102 are formed. Bit lines BL1-BL3 are formed to be parallel to the active pattern 102. Word lines WL1-WL4 are formed to vertically intersect the active pattern 102 and the bit lines BL1-BL3.

A contact hole 112 for forming a storage electrode pad is formed in the active pattern 102 between the word lines WL1-WL4 and the word lines WL1-WL4, and the storage electrode pad forming contact is formed. In the active pattern 102 between the holes 112, bit line contact holes 111 partially overlapping the bit lines BL1 to BL3 are formed.

2A and 3A and FIG. 4A, in the method of manufacturing a semiconductor device of the present invention, an element isolation film 101 is formed on a semiconductor substrate 100 to define an active region and an inactive region.

A conductive film 103a is formed on the semiconductor substrate 100 with a gate oxide film (not shown) interposed therebetween. The conductive film 103a has a structure in which a gate polysilicon film and a silicide film are stacked. A nitride film 103b is formed on the conductive film 103a. The conductive film 103a and the nitride film 103b are sequentially etched using a gate electrode forming mask to form the gate electrode layer 103, that is, the word lines WL1-WL4.

Next, a nitride film 104 for insulation is formed on the semiconductor substrate 100 including the gate electrode layer 103. By etching the nitride film 104 by an etch back process, gate electrode spacers 104 are formed on both sidewalls of the gate electrode 103 (not shown in FIGS. 3A and 4A).

2B and 3B and 4B, for example, USG, TEOS, BPTEOS, BPSG, and PSG as the first insulating film 106 on the semiconductor substrate 100 including the gate electrode layer 103. One is formed.

Then, a conductive film 108a for forming a bit line is formed on the first insulating film 106. The conductive film 108a has a structure in which a polysilicon film and a silicide film are stacked. A nitride film 108b is formed on the conductive film 108a. The bit line pattern 108 is formed by sequentially etching the nitride film 108b and the conductive film 108a using a bit line forming mask.

The nitride film 109 is formed on the first insulating layer 106 including the bit line pattern 108. By etching the nitride film 109 by an etch back process, bit line spacers 109 are formed on both sidewalls of the bit line pattern 108 (not shown in FIG. 2B).

Next, for example, any one of USG, TEOS, BPTEOS, BPSG, and PSG is formed on the first insulating layer 106 including the bit line 108.

Referring to FIG. 2C, the second insulating layer 110 and the first insulating layer 106 are sequentially etched until the surface of the semiconductor substrate 100 is exposed using a contact hole forming mask to form a storage electrode pad. The contact hole 112 is formed, and the bit line is sequentially etched through the second insulating layer 110, the bit line 108, and the first insulating layer 106 until the surface of the semiconductor substrate 100 is exposed. The contact hole 111 is formed.

The bit line contact hole 111 and the storage electrode pad forming contact hole 112 may be formed using any one of the same etching process and different etching processes. That is, the bit line contact hole 111 and the storage electrode pad forming contact hole 112 are formed simultaneously or sequentially.

The bit line contact hole 111 is formed such that an etched sidewall of the bit line is exposed in the bit line contact hole 111.

In other words, in forming the storage electrode pad forming contact hole 112, the second insulating film 110 and the first insulating film 106 may be nitride layers, which are mask layers of the gate electrode layer 103 and the bit line 108, respectively. By etching to have an etching selectivity with the 103b and 108b and the spacers 104 and 109, a self-aligned contact is formed as shown in FIG. 3C.

When the bit line contact hole 111 is formed, a portion of the nitride film 108b and the polysilicon film 108a overlapping the bit line 108 are etched together, as shown in FIG. 4C. The bit line contact hole 111 is formed such that the etched sidewall of 108 is exposed in the bit line contact hole 111. The gate electrode 103 and the gate electrode spacer 104 are etched in two steps to have an etch selectivity with the first insulating layer 106.

2D, 3D, and 4D, the bit line contact hole 111 and the pad forming contact hole 112 are simultaneously filled with a second conductive film, for example, a polysilicon film 114. The polysilicon film 114 is a material having excellent step coverage and is formed by a low pressure chemical vapor deposition (LPCVD) process.

Thereafter, the polysilicon film 114 is electrically connected to the semiconductor substrate 100 by a flat etching such that the polysilicon film 114 remains only in the contact holes 111 and 112 by a CMP or RIE etch back process. The bit line contacts 114a and the storage electrode contact pads 114b are formed.

The bit line contact 114a is electrically connected to a sidewall of the bit line 108 exposed in the bit line contact hole 111. The storage electrode contact pad 114b is electrically separated from the bit line 108 by the bit line spacer 109, and an upper portion of the pad 115 is positioned above the bit line 108. .

As described above, in the present invention, after the gate electrode 103 is formed in the DRAM cell manufacturing process having the COB structure, the first insulating layer 106 is formed immediately without forming the storage electrode pad and the bit line contact. The bit line 108 and the second insulating layer 110 are sequentially formed on the first etched insulating layer 106, and then the bit line contact 114a and the storage electrode contact pad 114b are formed. Is formed.

Here, since the second insulating film 110 does not perform a separate planarization process, the planarization process of the insulating film can be reduced once compared to the conventional art. In addition, by forming the storage electrode contact pads 114b after the formation of the bit lines 108, the process may be simplified to reduce costs and to shorten the process period. In addition, the thickness of the insulating layer to be etched when the storage electrode contact and the metal contact are formed is reduced.

Therefore, problems such as unetch of the contact, process change due to erosion of the contact upper opening area, and the like, lack of patterning margin due to the increase in the thickness of the mask photoresist film, and the like, can be overcome. The contact overlap margin of the conductive layer can be secured.

Next, referring to FIGS. 2E, 3E, and 4E, a third insulating layer 116 is formed on the second insulating layer 110 including the bit line contact 114a and the storage electrode contact pad 114b. do. The third insulating layer 116 is formed of any one of, for example, USG, TEOS, BPTEOS, BPSG, and PSG.

The storage electrode contact hole 117 is formed by etching the third insulating layer 116 until the surface of the storage electrode contact pad 114b is exposed using a contact hole forming mask.

Finally, a storage electrode contact plug 118 electrically connected to the storage electrode pad 114b is formed by filling the storage electrode contact hole 117 with a conductive material.

By forming the conductive layer pattern 120 on the third insulating layer 116 including the storage electrode contact plug 118, the storage electrode is formed as shown in FIGS. 2F, 3F, and 4F. Not shown in the figure) The conductive film pattern 120 is formed to the same thickness as in the prior art.

According to the present invention, the gate electrode and the bit line are sequentially formed, and then the bit line contact and the storage electrode contact pad are simultaneously or sequentially formed, thereby reducing the planarization process of the interlayer insulating film. In addition, when the storage electrode contact hole is formed, the thickness of the insulating layer is reduced to prevent unetch of the contact hole, corrosion of the upper opening area, and the like when using a budlessless concept. The tab area formed on the layout may be omitted for overlapping with each other, and thus the layout area may be reduced, thereby reducing the chip size.

1 is a layout of a semiconductor device according to an embodiment of the present invention;

2A through 2D are flowcharts sequentially illustrating processes of a method of manufacturing a semiconductor device, according to an embodiment of the present invention, taken along line AA ′ of FIG. 1;

3A to 3F are flowcharts sequentially illustrating processes of a method of manufacturing a semiconductor device according to an embodiment of the present invention, which are taken along line BB ′ of FIG. 1;

4A to 4F are flowcharts sequentially illustrating processes of a method of manufacturing a semiconductor device according to an embodiment of the present invention, and are taken along line CC ′ of FIG. 1.

* Explanation of symbols for the main parts of the drawings

100 semiconductor substrate 101 device isolation film

103: gate electrodes 104 and 109; Spacer

106, 110, 116: insulating film 108: bit line

111: bit line contact hole 112: contact hole for forming a storage electrode pad

114: bit line contact 115: storage electrode contact pad

117: storage electrode contact hole

Claims (7)

Forming a first insulating film (106) on the semiconductor substrate (100) on which the element is formed; Forming a first conductive film (108a, 108b) for forming a bit line on the first insulating film (106); Etching the first conductive films (108a, 108b) using a bit line forming mask to form a bit line pattern (108); Forming bit line spacers (109) with insulating films on both sidewalls of the bit line patterns (108); Forming a second insulating film (110) on the first insulating film (106) including the bit line (108); The bit line contact hole 111 is formed by sequentially etching the second insulating layer 110, the bit line 108, and the first insulating layer 106 using a contact hole forming mask, and forming the bit line 108. The etched sidewall of the bit line contact hole 111 is exposed, and the second insulating film 110 and the first insulating film 106 are sequentially etched to form the storage electrode pad forming contact hole 112. Steps; Filling the bit line contact hole 111 and the storage electrode pad forming contact hole with a second conductive layer 114 to form a bit line contact 114a and a storage electrode contact pad 114b; Forming a third insulating film (116) on the second insulating film (110) including the bit line contact (114a) and a storage electrode contact pad (114b); Forming a storage electrode contact hole 117 by etching the third insulating layer 116 until the surface of the storage electrode contact pad 114b is exposed using a contact hole forming mask. Manufacturing method. The method of claim 1, The bit line contact hole (111) and the storage electrode pad forming contact hole (112) are formed in any one of the same etching process and different etching process. The method of claim 1, The bit line contact hole (111) and the storage electrode pad forming contact hole (112) are simultaneously filled with the second conductive layer (114). The method of claim 1, The bit line contact (114a) is electrically connected to the sidewall of the bit line (108) exposed in the bit line contact hole (111). The method of claim 1, The storage electrode contact pad (114b) is electrically separated from the bit line (108), and the upper portion of the storage electrode contact pad (114b) is located above the bit line (108). The method of claim 1, The first conductive film (108a, 108b) and the second conductive film (114) is a polysilicon film manufacturing method. The method of claim 1, The second conductive film 114 is a method of manufacturing a semiconductor device is deposited by a low pressure chemical vapor deposition (LPCVD) process.