KR20000045374A - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor device Download PDFInfo
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- KR20000045374A KR20000045374A KR1019980061932A KR19980061932A KR20000045374A KR 20000045374 A KR20000045374 A KR 20000045374A KR 1019980061932 A KR1019980061932 A KR 1019980061932A KR 19980061932 A KR19980061932 A KR 19980061932A KR 20000045374 A KR20000045374 A KR 20000045374A
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- insulating layer
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- insulating film
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 55
- 238000000034 method Methods 0.000 title claims abstract description 37
- 238000004519 manufacturing process Methods 0.000 title claims description 13
- 239000000758 substrate Substances 0.000 claims abstract description 38
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 15
- 238000005530 etching Methods 0.000 claims abstract description 11
- 230000003647 oxidation Effects 0.000 claims abstract description 9
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 9
- 238000002955 isolation Methods 0.000 claims description 32
- 230000001590 oxidative effect Effects 0.000 claims description 6
- 238000001039 wet etching Methods 0.000 claims description 5
- 150000004767 nitrides Chemical class 0.000 claims description 3
- 238000001312 dry etching Methods 0.000 claims 1
- 230000007423 decrease Effects 0.000 description 3
- 230000005684 electric field Effects 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 238000013459 approach Methods 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000000593 degrading effect Effects 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
- H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Plasma & Fusion (AREA)
- Element Separation (AREA)
Abstract
Description
본 발명은 반도체소자의 제조방법에 관한 것으로, 특히 함몰된 트렌치의 양쪽 가장자리에서 노출되는 반도체기판을 소정 두께 산화시킴으로써 후속 공정으로 형성되는 게이트 절연막이 상기 트랜치의 양쪽 가장자리에서 얇아지는 현상을 방지하여 소자의 특성 및 신뢰성을 향상시키는 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and in particular, by oxidizing a semiconductor substrate exposed at both edges of a recessed trench by a predetermined thickness, a gate insulating film formed in a subsequent process is prevented from thinning at both edges of the trench. It relates to a method of improving the characteristics and reliability of the.
고집적화라는 관점에서 소자의 집적도를 높이기 위해서는 각각의 소자 디멘젼(dimension)을 축소하는 것과, 소자간에 존재하는 분리영역의 폭과 면적을 축소하는 것이 필요하며, 이 축소정도가 셀의 크기를 좌우한다는 점에서 소자분리 기술이 메모리 셀 사이즈(memory cell size)를 결정하는 기술이라고 할 수 있다.In order to increase the integration of devices from the viewpoint of high integration, it is necessary to reduce each device dimension and to reduce the width and area of the separation region existing between devices, and the degree of reduction depends on the size of the cell. In this regard, device isolation technology may be used to determine memory cell size.
일반적으로 소자분리 기술에서 디자인 룰이 감소함에 따라 작은 버즈빅 길이와 큰 체적비를 요구하고 있다.In general, as the design rule decreases in device isolation technology, a small buzz length and a large volume ratio are required.
그러나, 종래의 로코스(LOCOS : LOCal Oxidation of Silicon, 이하에서 LOCOS 라 함) 공정방법은 소자분리막이 얇아지는 문제와 버즈빅현상으로 기가(Giga DRAM)급 소자에서는 적용하는데 한계가 있다.However, the conventional LOCOS (LOCOS: LOCOS) process method has a limitation in that it is applied to a giga DRAM device due to a problem of thinning an isolation layer and a buzz big phenomenon.
또한, 트렌치 소자분리 공정도 공정의 복잡성뿐만 아니라 디자인 룰이 감소할수록 트렌치 영역을 매립하는 것이 어려워지므로 실제로 디자인 룰이 0.1 ㎛ 에 접근하면 트렌치 소자분리 공정도 적용하기가 어려워 질 것이다.In addition, the trench isolation process is difficult to bury the trench region as the design rule is reduced as well as the complexity of the process, it will be difficult to apply the trench isolation process when the design rule approaches 0.1 ㎛.
이하, 첨부된 도면을 참고로 하여 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described in detail.
도 1a 내지 도 1d 는 종래기술에 따른 반도체소자의 제조방법을 도시하는 단면도이다.1A to 1D are cross-sectional views showing a method of manufacturing a semiconductor device according to the prior art.
먼저, 반도체기판(11) 상부에 제1절연막(13) 및 제2절연막(15)을 순차적으로 형성하고, 그 상부에 소자분리 영역으로 예정된 부분을 노출시키는 감광막 패턴(17)을 형성한다. 상기 제1절연막(13)은 산화막으로 형성하고, 상기 제2절연막(15)은 질화막으로 형성한다.First, the first insulating film 13 and the second insulating film 15 are sequentially formed on the semiconductor substrate 11, and a photosensitive film pattern 17 is formed on the semiconductor substrate 11 to expose a predetermined portion as a device isolation region. The first insulating layer 13 is formed of an oxide film, and the second insulating layer 15 is formed of a nitride film.
다음, 상기 감광막 패턴(17)을 식각마스크로 사용하여 상기 제2절연막(15), 제1절연막(13) 및 소정 두께의 반도체기판(11)을 제거하여 트렌치(19)를 형성한다. (도 1a참조)Next, the trench 19 is formed by removing the second insulating layer 15, the first insulating layer 13, and the semiconductor substrate 11 having a predetermined thickness using the photoresist pattern 17 as an etching mask. (See FIG. 1A)
그 다음, 상기 감광막 패턴(17)을 제거하고, 상기 트렌치(19)의 표면을 열산화시켜 희생산화막인 제3절연막(도시안됨)을 성장시킨 후 습식식각을 통해 상기 제3절연막을 제거함으로써 상기 트렌치(19) 형성공정시 발생된 상기 트렌치(19) 표면의 결함을 제거한다. 여기서, 상기 제3절연막을 제거하는 동안에 반도체기판(11) 및 제1절연막(13)이 손실된다.Next, the photoresist pattern 17 is removed, the surface of the trench 19 is thermally oxidized to grow a third insulating film (not shown), which is a sacrificial oxide film, and then the third insulating film is removed by wet etching. The defects on the surface of the trench 19 generated during the trench 19 formation process are removed. Here, the semiconductor substrate 11 and the first insulating film 13 are lost while the third insulating film is removed.
그 후, 다시 열산화공정을 실시하여 상기 트렌치(19)의 표면에 제4절연막(도시안됨)을 형성한다.Thereafter, a thermal oxidation process is performed again to form a fourth insulating film (not shown) on the surface of the trench 19.
다음, 전체표면 상부에 상기 트렌치(19)를 매립하는 소자분리절연막(21)을 형성하되, 고밀도플라즈마화학기상증착(high density plasma chemical vapor deposition, 이하 HDP CVD 라 함) 산화막을 이용하여 형성한다.Next, a device isolation insulating film 21 for filling the trench 19 is formed on the entire surface, and is formed by using an oxide film of high density plasma chemical vapor deposition (hereinafter referred to as HDP CVD).
그리고, 후속 열처리공정을 실시하여 상기 소자분리 절연막(21)을 치밀화(densification)시킨다. (도 1b참조)Subsequently, a subsequent heat treatment process is performed to densify the device isolation insulating film 21. (See FIG. 1B)
다음, 상기 소자분리절연막(21)을 상기 제2절연막(15)을 식각방지막으로 사용하여 화학적기계적연마(chemical mechanical polishing, 이하 CMP 라함)공정을 실시하여 제거한다. 이때, 상기 CMP공정후 상기 소자분리절연막(21)과 제2절연막(15)의 식각선택비차이로 인하여 상기 소자분리절연막(21)의 손실이 발생한다.Next, the device isolation insulating film 21 is removed by performing a chemical mechanical polishing (CMP) process using the second insulating film 15 as an etch stop layer. In this case, after the CMP process, a loss of the device isolation insulating layer 21 occurs due to a difference in etching selectivity between the device isolation insulating layer 21 and the second insulating layer 15.
그 다음, 소자분리영역과 반도체기판(11)과의 단차를 줄이기 위하여 상기 소자분리절연막(21)을 습식식각방법으로 제거한다. 이때, 상기 반도체기판(11)이 소정 두께 손실된다.Then, the device isolation insulating film 21 is removed by a wet etching method to reduce the step difference between the device isolation region and the semiconductor substrate 11. At this time, the semiconductor substrate 11 loses a predetermined thickness.
다음, 상기 제2절연막(15)을 과도식각하여 제거한다. 이때, 상기 반도체기판(11)의 손실이 더 발생하여 트렌치(19)의 양쪽 가장자리부분이 ⓐ 부분과 같이 함몰된다. (도 1c참조)Next, the second insulating layer 15 is overetched and removed. At this time, the loss of the semiconductor substrate 11 further occurs, so that both edge portions of the trench 19 are recessed like the ⓐ portion. (See FIG. 1C)
그 다음, 게이트 절연막(23)을 형성한 후, 게이트 전극(25)을 형성한다. 이때, 상기 소자분리절연막(21)의 양쪽 가장자리부분에서 ⓑ 부분과 같이 상기 게이트 절연막(23)의 두께가 얇아지게 된다. (도 1d참조)Then, after the gate insulating film 23 is formed, the gate electrode 25 is formed. At this time, the thickness of the gate insulating film 23 becomes thinner, like the ⓑ, at both edges of the device isolation insulating film 21. (See FIG. 1D)
참고로, 도 1e 는 종래기술에 따른 반도체소자의 제조방법에 의한 트렌지스터의 폭방향으로 전기장의 크기를 도시한 특성곡선이며, 도 1f 및 도 1g 는 종래기술에서 트랜지스터 폭의 크기에 따른 핫캐리어 주입 테스트를 도시한 그래프도로서, 트랜지스터의 폭이 클수록 드레인전류의 감소율이 작고, 반도체기판의 전류 감소율이 작은 것을 나타낸다.For reference, FIG. 1E is a characteristic curve showing the size of an electric field in the width direction of a transistor according to the method of manufacturing a semiconductor device according to the prior art, and FIGS. 1F and 1G are hot carrier injection according to the size of the transistor width in the prior art. The graph showing the test shows that the larger the width of the transistor is, the smaller the decrease rate of the drain current is, and the smaller the current decrease rate of the semiconductor substrate is.
상기와 같이 종래기술에 따른 반도체소자의 제조방법은, 트렌치를 매립하는 소자분리절연막 상부의 양쪽 가장자리가 함몰되어 게이트 절연막 형성공정시 상기 함몰 부분에서는 게이트 절연막이 얇게 형성되어 게이트 전극형성후 전기장이 크게 걸려 제너레이션(generation)된 핫캐리어(hot carrier)량이 증가하여 트랜지스터의 라이프타임(lifetime)을 감소시켜 소자의 특성 및 신뢰성을 저하시키는 문제점이 있다.As described above, in the method of manufacturing a semiconductor device according to the related art, both edges of an upper portion of the device isolation insulating film filling the trench are recessed so that a thin gate insulating film is formed in the recessed portion during the gate insulating film forming process, thereby increasing the electric field after forming the gate electrode. There is a problem in that the amount of generated hot carriers is increased, thereby reducing the lifetime of the transistor, thereby degrading the characteristics and reliability of the device.
본 발명은 상기한 종래기술의 문제점을 해결하기 위하여, 트랜치를 매립하는 HDP-CVD 산화막과 반도체기판간에 산화율(oxidation rate)을 이용하여 함몰된 트랜치의 양쪽 가장자리의 반도체기판을 산화시킨 후 후속공정을 실시하여 상기 트렌치의 양쪽 가장자리에서 게이트 절연막이 얇아지는 현상을 방지하고 그에 따른 반도체소자의 특성 및 신뢰성을 향상시키는 반도체소자의 제조방법을 제공하는데 그 목적이 있다.In order to solve the above-described problems of the prior art, the following process is performed after oxidizing the semiconductor substrates at both edges of the recessed trenches by using an oxidation rate between the HDP-CVD oxide film filling the trench and the semiconductor substrate. The purpose of the present invention is to provide a method for manufacturing a semiconductor device, which prevents the gate insulating film from thinning at both edges of the trench and improves the characteristics and reliability of the semiconductor device.
도 1a 내지 도 1d 는 종래기술에 따른 반도체소자의 제조방법을 도시한 단면도.1A to 1D are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the prior art.
도 1e 는 종래기술에 따른 반도체소자의 제조방법에 의한 트렌지스터의 폭방향으로 전기장의 크기를 도시한 특성곡선.Figure 1e is a characteristic curve showing the magnitude of the electric field in the width direction of the transistor by a method of manufacturing a semiconductor device according to the prior art.
도 1f 및 도 1g 는 종래기술에서 트랜지스터 폭의 크기에 따른 핫캐리어 주입 테스트를 도시한 그래프도.1F and 1G are graphs illustrating a hot carrier injection test according to the size of transistor widths in the prior art.
도 2a 내지 도 2e 는 본 발명에 따른 반도체소자의 제조방법을 도시한 단면도.2A to 2E are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with the present invention.
<도면의 주요부분에 대한 부호의 설명><Description of the symbols for the main parts of the drawings>
11, 12 : 반도체기판 13, 14 : 제1절연막11, 12: semiconductor substrate 13, 14: first insulating film
15, 16 : 제2절연막 17, 18 : 감광막 패턴15, 16: second insulating film 17, 18: photosensitive film pattern
19, 20 : 트랜치 21, 22 : 소자분리절연막19, 20: trench 21, 22: device isolation insulating film
23, 24 : 게이트 절연막 25, 26 : 게이트 전극23, 24: gate insulating film 25, 26: gate electrode
이상의 목적을 달성하기 위한 본 발명에 따른 반도체소자의 제조방법은,Method for manufacturing a semiconductor device according to the present invention for achieving the above object,
반도체기판 상부에 제1절연막을 형성하고, 상기 제1절연막 상부에 소자분리 영역으로 예정되어 있는 부분을 노출시키는 감광막 패턴을 형성하는 공정과,Forming a photoresist pattern on the semiconductor substrate, and forming a photoresist pattern on the semiconductor substrate, the photoresist pattern exposing a portion intended as an isolation region;
상기 감광막 패턴을 식각마스크로 상기 제1절연막과 반도체기판을 식각하여 트렌치를 형성한 다음, 상기 감광막 패턴을 제거하는 공정과,Forming a trench by etching the first insulating layer and the semiconductor substrate using the photoresist pattern as an etch mask, and then removing the photoresist pattern;
상기 트렌치 표면에 희생산화막을 형성하는 공정과,Forming a sacrificial oxide film on the trench surface;
상기 희생산화막을 제거하고, 상기 트렌치의 표면에 제2절연막을 형성하는 공정과,Removing the sacrificial oxide film and forming a second insulating film on a surface of the trench;
상기 구조 상부에 상기 트렌치를 매립하는 제3절연막을 형성하는 공정과,Forming a third insulating film filling the trench on the structure;
상기 제3절연막을 CMP 공정으로 제거하되, 상기 제1절연막을 식각방지막으로 사용하여 제거하는 공정과,Removing the third insulating layer by a CMP process, but using the first insulating layer as an etch stop layer;
상기 제3절연막을 상기 제1절연막과의 식각선택비차이를 이용하여 소정 두께 제거하는 공정과,Removing the third insulating layer by a predetermined thickness using an etch selectivity difference from the first insulating layer;
상기 제3절연막과 반도체기판의 산화율 차이를 이용하여 상기 제3절연막과 제1절연막 사이에 노출된 반도체기판을 산화시키는 공정과,Oxidizing a semiconductor substrate exposed between the third insulating layer and the first insulating layer by using a difference in oxidation rate between the third insulating layer and the semiconductor substrate;
상기 제1절연막을 제거한 다음, 전체표면 상부에 게이트 절연막을 형성하는 공정과,Removing the first insulating film, and then forming a gate insulating film over the entire surface;
상기 게이트 절연막 상부에 게이트 전극을 형성하는 공정을 포함하는 것을 특징으로 한다.And forming a gate electrode on the gate insulating film.
이하, 첨부된 도면을 참고로 하여 본 발명을 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2e 는 본 발명에 따른 반도체소자의 제조방법을 도시한 단면도이다.2A through 2E are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the present invention.
먼저, 반도체기판(12) 상부에 제1절연막(14) 및 제2절연막(16)을 순차적으로 형성하고, 그 상부에 소자분리 영역으로 예정된 부분을 노출시키는 감광막 패턴(18)을 형성한다. 상기 제1절연막(14)은 산화막으로 형성하고, 상기 제2절연막(16)은 질화막으로 형성한다.First, the first insulating film 14 and the second insulating film 16 are sequentially formed on the semiconductor substrate 12, and a photosensitive film pattern 18 is formed on the semiconductor substrate 12 to expose a predetermined portion as a device isolation region. The first insulating layer 14 is formed of an oxide film, and the second insulating layer 16 is formed of a nitride film.
다음, 상기 감광막 패턴(18)을 식각마스크로 사용하여 상기 제2절연막(16), 제1절연막(14) 및 소정 두께의 반도체기판(12)을 제거하여 트렌치(19)를 형성한다. (도 2a참조)Next, the trench 19 is formed by removing the second insulating layer 16, the first insulating layer 14, and the semiconductor substrate 12 having a predetermined thickness using the photoresist pattern 18 as an etching mask. (See Figure 2A)
그 다음, 상기 감광막 패턴(18)을 제거하고, 상기 트렌치(20)의 표면을 열산화시켜 희생산화막인 제3절연막(도시안됨)을 성장시킨 후 습식식각을 통해 상기 제3절연막을 제거함으로써 상기 트렌치(20) 형성공정시 발생된 상기 트렌치(20) 표면의 결함을 제거한다. 여기서, 상기 제3절연막을 제거하는 동안에 반도체기판(12) 및 제1절연막(14)이 손실된다.Next, the photoresist layer pattern 18 is removed, the surface of the trench 20 is thermally oxidized to grow a third insulating layer (not shown), which is a sacrificial oxide layer, and then the third insulating layer is removed by wet etching. The defects on the surface of the trench 20 generated during the trench 20 formation process are removed. Here, the semiconductor substrate 12 and the first insulating film 14 are lost while the third insulating film is removed.
그 후, 다시 열산화공정을 실시하여 상기 트렌치(20)의 표면에 제4절연막(도시안됨)을 형성한다.Thereafter, a thermal oxidation process is performed again to form a fourth insulating film (not shown) on the surface of the trench 20.
다음, 전체표면 상부에 상기 트렌치(20)를 매립하는 소자분리절연막(22)을 형성하되, HDP CVD 산화막을 이용하여 형성한다.Next, a device isolation insulating film 22 filling the trench 20 is formed on the entire surface of the device, and is formed by using an HDP CVD oxide film.
그리고, 후속 열처리공정을 실시하여 상기 소자분리 절연막(22)을 치밀화(densification)시킨다. (도 2b참조)Subsequently, a subsequent heat treatment process is performed to densify the device isolation insulating layer 22. (See Figure 2b)
다음, 상기 소자분리절연막(22)을 상기 제2절연막(16)을 식각방지막으로 사용하여 CMP 공정을 실시하여 제거한다. 이때, 상기 CMP공정후 상기 소자분리절연막(22)과 제2절연막(16)의 식각선택비차이로 인하여 상기 소자분리절연막(22)의 손실이 발생한다.Next, the device isolation insulating layer 22 is removed by performing a CMP process using the second insulating layer 16 as an etch stop layer. In this case, after the CMP process, the device isolation insulating layer 22 may be lost due to the difference in etching selectivity between the device isolation insulating layer 22 and the second insulating layer 16.
그 다음, 소자분리영역과 반도체기판(12)과의 단차를 줄이기 위하여 상기 소자분리절연막(22)을 습식식각방법으로 제거한다. 이때, 상기 반도체기판(12)이 소정 두께 손실된다.Then, the device isolation insulating film 22 is removed by a wet etching method to reduce the step difference between the device isolation region and the semiconductor substrate 12. At this time, the semiconductor substrate 12 loses a predetermined thickness.
그 다음, 상기 소자분리절연막(22)과 반도체기판(12) 간의 산화율차이를 이용하여 상기 반도체기판(12)의 함몰된 부분에 ⓒ 부분과 같이 산화막을 50 ∼ 100Å 두께로 형성한다. 이때, 상기 소자분리절연막(22)은 거의 산화되지 않는다. (도 2c참조)Then, using the difference in oxidation rate between the device isolation insulating film 22 and the semiconductor substrate 12, an oxide film is formed in the recessed portion of the semiconductor substrate 12 to have a thickness of 50 to 100 kPa, like the? Portion. At this time, the device isolation insulating film 22 is hardly oxidized. (See FIG. 2C)
다음, 상기 제2절연막(16)을 과도식각하여 제거한다. 상기 제2절연막(16) 제거후에도 상기 소자분리절연막(22)의 양쪽 가장자리 부분은 함몰되지 않는다. (도 2d참조)Next, the second insulating layer 16 is removed by over etching. Even after the second insulating layer 16 is removed, both edges of the device isolation insulating layer 22 are not recessed. (See FIG. 2D)
그 다음, 게이트 절연막(24)을 형성한 후, 게이트 전극(26)을 형성한다. 상기 ⓒ영역에서 상기 게이트 절연막(24)이 얇아지는 현상이 발생하지 않는다. (도 2d참조)Then, after the gate insulating film 24 is formed, the gate electrode 26 is formed. The thinning of the gate insulating film 24 in the area ⓒ does not occur. (See FIG. 2D)
이상에서 설명한 바와같이 본 발명에 따른 반도체소자의 제조방법은, 반도체기판 상부에 소자분리 영역으로 예정되는 부분을 노출시키는 절연막 패턴을 식각마스크로 사용하여 상기 반도체기판을 식각하여 트렌치를 형성하고, 전체표면 상부에 상기 트렌치를 매립하는 소자분리절연막을 형성한 다음, CMP공정으로 평탄화시킨 후 상기 단차를 줄이기 위한 식각공정시 상기 트렌치의 양쪽 가장자리 부분이 함몰되어 노출된 반도체기판을 상기 소자분리절연막과의 산화율차이를 이용하여 산화시켜 소정 두께의 산화막을 형성시킴으로써 후속공정시 게이트 절연막이 상기 트렌치의 양쪽 가장자리에서 얇아지는 현상을 방지하고 그에 따른 반도체소자의 특성 및 신뢰성을 향상시키는 이점이 있다.As described above, in the method of manufacturing a semiconductor device according to the present invention, a trench is formed by etching the semiconductor substrate using an insulating film pattern exposing a portion, which is intended as an isolation region, on the semiconductor substrate as an etching mask. After forming a device isolation insulating film filling the trench on the upper surface, and then planarized by a CMP process, the semiconductor substrate exposed by recessing both edge portions of the trench with the device isolation insulating film during an etching process to reduce the step difference. By oxidizing using the difference in oxidation rate to form an oxide film having a predetermined thickness, there is an advantage of preventing the gate insulating film from thinning at both edges of the trench in a subsequent process and thereby improving the characteristics and reliability of the semiconductor device.
Claims (5)
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100700284B1 (en) * | 2005-12-28 | 2007-03-26 | 동부일렉트로닉스 주식회사 | Method of fabricating the trench isolation layer in semiconductor device |
| KR100770455B1 (en) * | 2001-06-22 | 2007-10-26 | 매그나칩 반도체 유한회사 | Manufacturing method for semiconductor device |
| KR100792709B1 (en) * | 2001-06-25 | 2008-01-08 | 매그나칩 반도체 유한회사 | Manufacturing method for semiconductor device |
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| KR100770455B1 (en) * | 2001-06-22 | 2007-10-26 | 매그나칩 반도체 유한회사 | Manufacturing method for semiconductor device |
| KR100792709B1 (en) * | 2001-06-25 | 2008-01-08 | 매그나칩 반도체 유한회사 | Manufacturing method for semiconductor device |
| KR100700284B1 (en) * | 2005-12-28 | 2007-03-26 | 동부일렉트로닉스 주식회사 | Method of fabricating the trench isolation layer in semiconductor device |
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