KR20000011226A - Memory control method, memory unit and controller - Google Patents

Abstract

PURPOSE: A memory control method is provided to perform a memory control by transmitting a command to a memory having an internal processing function acquiring a use power of a bus which is used by another processing unit. CONSTITUTION: The memory control method comprises the steps of: relieving, after transmitting a command to a memory(10) having an internal processing function, a bus using power when the memory having an internal processing function is at a use state; standing by that the memory(10) having an internal processing function is switched from a use state to a preparation state; and acquiring the bus using power, when detecting that the memory(10) having an internal processing function is switched from a use state to a preparation state, at the standby state, to then process the process continuously.

Description

Memory control method, memory device and controller {MEMORY CONTROL METHOD, MEMORY UNIT AND CONTROLLER}

The present invention is a memory having an internal processing function by subjecting a memory having a function of internal processing of memory control to a control object, acquiring a license of a bus that is also used by another processing unit, and sending a command to a memory having internal processing function. And a controller for acquiring a right to use a CPU and a memory having an internal processing function and a common bus, and sending a command to a memory having an internal processing function, the CPU and the internal processing on the common bus. The memory device to which the memory with the function and the controller are connected, the CPU and the memory with the internal processing function are connected via a common bus, and the command is acquired by sending a command to the memory having the internal processing function. The present invention relates to a controller for controlling a memory having a processing function. The present invention relates to a memory control method, a memory device, and a controller for realizing efficient operation.

A memory device, such as a memory card having a memory, having a configuration having a controller of a hardware configuration that controls the memory, apart from a CPU receiving instructions from the host, the controller responding to instructions sent by the CPU. There is a device configuration for controlling a memory by sending a command of a memory control to the.

In a memory device having such a device configuration, when mounting a memory having a function of internally processing memory control as a memory, it is necessary to realize an improvement in processing efficiency by constructing a configuration suitable for the characteristics of such a memory.

Apart from the CPU receiving instructions from the host, a configuration is provided having a controller of a hardware configuration that controls the memory, and the controller controls the memory by sending a command of memory control to the memory in response to a command sent by the CPU. There is a memory device.

In the conventional memory device having this configuration, as shown in Fig. 20, a bus connecting a CPU and a controller (described as a CPU bus in the drawing) and a bus connecting a controller and a memory (a memory bus in the drawing) Is described separately).

In addition, the bus selector shown in the figure operates to connect between the memory and the buffer by selecting the memory bus when the controller is in the operating state, and to connect between the CPU and the buffer by selecting the CPU bus when the controller is in the inactive state. do.

Therefore, in a memory device having this configuration, the controller does not allow the CPU to acquire a license for the memory bus by itself, and sends a command to the memory and subsequently obtains memory state information for the command from the memory. Since the processing is performed, even after the license of the memory bus is acquired and the instruction is transmitted to the memory, the memory bus is held without releasing the license of the memory bus. Processing is performed to obtain status information.

In recent years, the demand for miniaturization of a device incorporating the memory device having the above-described configuration has further increased the demand for miniaturization of this memory device.

Therefore, rather than having two buses, a CPU bus and a memory bus, the two buses need to be common.

On the other hand, flash memory has become popular recently. This flash memory is an EEPROM that has a function of erasing the contents of the memory collectively, and it is expected to be mounted on various electronic devices because of its high density and its small size.

In this flash memory, in order to realize high-speed processing, a configuration having a controller and a buffer therein is taken, and when a command of memory control is sent from an external controller, the internal controller erases data in the flash memory in response thereto, The process of writing data transmitted from the outside via the bus to the internal buffer, writing data to the flash memory from the internal buffer, or reading data from the flash memory and writing the data to the internal buffer, and then outputting the data to the outside via the bus. Do

In this process, while the internal controller is erasing data in the flash memory, while the internal controller is writing data from the internal buffer to the flash memory, and while the internal controller is reading data from the flash memory into the internal buffer. Cannot communicate with the outside, and the flash memory is busy.

Therefore, in the memory device having the above-described configuration, when the flash memory is mounted as a memory and the CPU bus and the memory bus are configured in common, the controller is provided with a bus according to the configuration including the CPU bus and the memory bus separately. If the controller is configured to not release the bus for the period until the license is obtained and the command is sent to the flash memory and the status information of the flash memory is acquired, the controller maintains the bus license unnecessarily. There was a problem that was done.

That is, when a command is sent to the flash memory, the flash memory is then in use by entering the internal processing using the internal controller, and according to the prior art, the controller needs to maintain the bus license during this time. There was a problem that the CPU could not use the bus by keeping the bus license even when it was not there.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and the internal processing is performed by acquiring a license to use a bus having an internal processing function and using a different processing unit to transmit a command to a memory having an internal processing function. In the case of controlling a memory having a function, providing a new memory control method for realizing the efficient use of the bus license, acquiring the license of a memory having a CPU and an internal processing function and a common bus, and having an internal processing function. Providing a new memory device having a controller for sending commands to the memory, and when a memory and a controller having a CPU and an internal processing function are connected to the common bus, thereby realizing efficient operation of the bus right, and providing the CPU and internal processing. The memory with the function is connected via a common bus, and the bus license is acquired. When controlling a memory having an internal processing function by sending a command to the memory having the internal processing function, an object of the provision of the new controller to realize the efficient operation of the bus use.

1 is a principle block diagram of the present invention.

2 is a circuit configuration diagram of the memory card of the present invention.

3 is an explanatory diagram of a flash memory;

4 is an explanatory diagram of a flash controller.

5 illustrates one embodiment of a processing flow executed by a CPU.

6 is an explanatory diagram of a process executed by a flash controller;

7 is an explanatory diagram of a process executed by a sequencer.

8 is an explanatory diagram of a process executed by a sequencer;

9 is an explanatory diagram of a process executed by a sequencer;

10 is an explanatory diagram of a process executed by a sequencer;

11 is an explanatory diagram of a process executed by a sequencer;

12 is an explanatory diagram of a process executed by a sequencer;

13 is a time chart of an erase process.

14 is a time chart of an erase process;

15 illustrates one embodiment of a processing flow executed by a CPU.

16 illustrates one embodiment of a processing flow executed by a CPU.

17 is an explanatory diagram of a memory card.

18 is a time chart of an inspection process;

19 is another embodiment of a processing flow executed by a CPU.

20 is an explanatory diagram of a prior art.

<Explanation of symbols for main parts of drawing>

1: memory device

10: memory with internal processing

11: CPU

12: controller

13: bus

14: first execution means

15: second execution means

16: third execution means

17: detection means

18: indicating means

24: acquisition means

25: setting means

1 shows a principle configuration of the present invention.

In the drawings, reference numeral 1 denotes a memory device having the present invention, which includes a memory 10 having a function of internally processing memory control using an internal buffer, and a CPU that receives an access request sent by the host device 2 ( 11), a controller 12 for controlling a memory 10 having an internal processing function by sending a memory control command in response to an instruction of the CPU 11, a memory 10 having an internal processing function, and A common bus 13 is provided for connecting between the CPU 11 and the controller 12, and reference numeral 2 denotes a memory device 1 having an internal processing function with respect to the memory device 1 as a host device. To transmit.

The controller 12 includes a first execution means 14 for performing a process of releasing a right of use of the common bus 13 during a process terminated by acquiring state information or the like, and a memory 10 having an internal processing function. The second execution means 15 which performs the process waiting to transition from a use state to a ready state, and the 3rd execution means 16 which acquire the usage right of the common bus 13 and continue a process are provided.

Reference numeral 17 denotes a detection means, which operates on the CPU 11 and monitors the operation state of the controller 12 to detect the passage of time when the memory 10 having the internal processing function does not shift to the ready state.

Reference numeral 18 denotes a control means of the memory 10 having an internal processing function for the controller 12 when the detection means 17 operates on the CPU 11 and detects the elapse of the prescribed time. Instructs to forcibly terminate.

In the memory device 1 of the present invention configured as described above, the first execution means 14 of the controller 12 when accessing the memory 10 having an internal processing function in response to a request from the host device 2. Is transmitted to the memory 10 having a function of internal processing, and then, when the memory 10 having an internal processing function shifts to a use state during a process of terminating by acquiring status information or the like, the common bus We release right of use of (13).

Accepting this execution process, the second execution means 15 of the controller 12 waits for the memory 10 having an internal processing function to transition from the use state to the ready state.

When in the standby state, the third execution means 16 of the controller 12 acquires the right to use the common bus 13 when it detects that the memory 10 having an internal function moves to the ready state, Processing is continued, and processing such as obtaining state information of the memory 10 having an internal processing function is performed.

At this time, the detection means 17 monitors the operation state of the controller 12, detects the elapsed time of the state in which the memory 10 having the internal processing function does not shift to the ready state, receives this, and indicates the indication means ( 18 instructs the controller 12 to forcibly terminate the control process of the memory 10 having the internal processing function when the detection means 17 detects the passage of the prescribed time.

Therefore, in the present invention, a memory 10 having an internal processing function having a function of internally processing memory control using an internal buffer is a control object, and the memory 10 and the CPU 11 having an internal processing function and When taking the configuration of connecting the controllers 12 to the common bus 13, paying attention to the characteristics of the memory 10 having an internal processing function having an internal processing function, the controller 12 responds to a command to be transmitted. When the memory 10 having the internal processing function enters the internal processing, the controller 12 processes the license 12 of the acquired common bus 13 to be temporarily released. Therefore, the usage right of the common bus 13 is unnecessarily used. It keeps going.

As a result, the CPU 11 can execute separate processing using the common bus 13, and the operating right of the common bus 13 can realize efficient operation, thereby improving processing efficiency.

Further, in the memory device 1 of the present invention configured as described above, the first execution means 14 of the controller 12 when accessing the memory 10 having an internal processing function in response to a request of the host device 2. ) Transmits a command to the memory 10 having an internal processing function to cause the memory 10 having an internal processing function to transition to the use state. Without confirming that, the right to use the common bus 13 is released.

By accepting this execution process, the second execution means 15 of the controller 12 responds to the transmission of a command causing a use state of the memory 10 having an internal processing function (10) with an internal processing function. After the internal processing moves to the use state by the internal processing, the internal processing is terminated and the memory 10 having the internal processing function is waited for to transition from the use state to the ready state.

When in this standby state, the third execution means 16 of the controller 12 acquires the right to use the common bus 13 when it detects that the memory 10 having the internal processing function shifts to the ready state. Then, processing such as acquiring state information of the memory 10 having the internal processing function is performed by continuing the processing.

At this time, the detection means 17 monitors the operation state of the controller 12, detects the elapsed time of the state where the memory 10 having the internal processing function does not shift to the ready state, accepts this, and indicates the indication means ( 18) instructs the controller 12 to forcibly terminate the control process of the memory 10 having the internal processing function when the detection means 17 detects the passage of the prescribed time.

In this way, in the present invention, a memory 10 having a function of internally processing memory control using an internal buffer is a control object, and the memory 10 having the internal processing function, the CPU 11, and the controller 12 are controlled. When taking a configuration in which the common bus 13 is connected to each other, paying attention to the characteristics of the memory 10 having an internal processing function, the memory 10 having an internal processing function internally processes an instruction that causes a use state. At the time of transmission, since the controller 12 processes to immediately release the right of use of the common bus 13 without confirming that the memory 10 having the internal processing function shifts to the use state, the common bus 13 is unnecessary. You do not have to maintain the license.

As a result, the CPU 11 can execute a separate process using the common bus 13, and the use right of the common bus 13 can realize efficient operation, thereby improving the processing efficiency.

Hereinafter, the present invention will be described in detail with reference to examples.

2 shows an example of a circuit configuration of a memory card 1a according to the present invention.

The memory card 1a is provided with a connector and is freely detachably connected to a slot provided in a host such as a personal computer or a digital camera. At this time, the power supply to the memory card 1a is performed through the connector from the host of the destination.

As shown in FIG. 2, the memory card 1a is equipped with a plurality of flash memories 20 (only one may be built in), and in response to an access request sent by the personal computer 2a, In order to realize this process by executing the access process to the flash memory 20, the CPU 21 having the ROM 22 in addition to the flash memory 20, the flash controller 23, the host controller 24, and the buffer ( 25), RAM 26, etc., and a CPU bus 27 for connecting them.

As shown in FIG. 3, the flash memory 20 includes a flash memory cell 200, an internal controller 201, and an internal buffer 202, which are configured to control memory from the flash controller 23. When a command (hereinafter, a command transmitted by the controller 23 is referred to as a flash command) is transmitted, in response thereto, data written to the flash memory cell 200 is erased, or data received from the CPU bus 27 is stored in an internal buffer ( After writing to 202, data is written from the internal buffer 202 to the flash memory cell 200, or data is read from the flash memory cell 200 and written to the internal buffer 202, and then from the internal buffer 202. Processing such as output to the CPU bus 27 is performed.

In this process, the internal controller 201 outputs a ready / use signal to the flash controller 23 indicating whether it is in the ready state or in the used state.

This ready / use signal is used while erasing data of the flash memory cell 200, while writing data from the internal buffer 202 to the flash memory cell 200, and from the flash memory cell 200. While the data is being read out at 202, the use state is displayed; otherwise, the ready state is displayed.

In the ROM 22, a program for realizing access to the flash memory 20 is recorded. When the personal computer 2a transmits an access request, the CPU 21 writes to the flash controller 23 in accordance with the program. A process of executing access to the flash memory 20 is performed by sending an access instruction.

In more detail, since the configuration information such as the number of flash memories 20 to be mounted is recorded in the head flash memory 20, the CPU 21 starts the ROM 22 when the memory card 1a is started. According to the program recorded on the memory device, the memory capacity in units of one chip recorded in the flash memory 20 and its configuration information are read out to specify the total memory capacity, and the personal computer 2a is notified to it or the personal computer is operated during normal operation. When the computer 2a designates an address and transmits an access request, the chip number of the flash memory 20 to be accessed is specified from the memory capacity in units of one chip according to the program recorded in the ROM 22. By sending an access instruction to the flash controller 23, processing such as executing access to the flash memory 20 is performed.

The flash controller 23 executes access to the flash memory 20 by sending a flash command to the flash memory 20 when an access instruction to the flash memory 20 is transmitted from the CPU 21. The buffer 25 records data written to the flash memory 20 and data read from the flash memory 20. The host controller 24 executes interface processing between the personal computer 2a. The RAM 26 is used for the work memory of the CPU 21 and the like.

In order to execute the access processing to the flash memory 20, the flash controller 23 includes an instruction register 230 that receives a command transmitted by the CPU 21, and an instruction register 230 as shown in FIG. A command decoder 231 for decoding a command held by the user, a sequencer 232 of a hardware configuration for sequencing memory control according to the decoding result of the command decoder 231, and a flash in response to an instruction of the sequence 232. A flash command transmission mechanism 233 having a hardware configuration for transmitting a flash command to the memory 20, and an end display register 234 for receiving a flag indicating completion or non-end of the sequence operation of the sequencer 232; do.

The flash command transmitted by the flash controller 23 includes a data input command, a write command, a read command, an erase command, a status command, and the like.

When the data input command is transmitted from the flash controller 23, the internal controller 201 of the flash memory 200 writes data to which the write request is written to the internal buffer 202. When a write command is transmitted, the process of writing data written to the internal buffer 202 to the flash memory cell 200 is performed. In addition, when a read command is transmitted, a process of reading the specified data from the flash memory cell 20, writing it to the internal buffer 202, and outputting it to the CPU bus 27 is performed. In addition, when an erase command is transmitted, a process of erasing data designated from the flash memory cell 20 is performed. When the status command is transmitted, the flash controller 23 performs a process of returning status information.

When the internal controller 201 performs this process, as described above, while erasing data of the flash memory cell 200, while writing data from the internal buffer 202 to the flash memory cell 200, and While reading data from the flash memory cell 200 to the internal buffer 202, a process of using the ready / use signal and processing the display to the flash controller 23 is performed.

FIG. 5 shows one embodiment of the processing flow executed by the CPU 21, and FIG. 6 shows the processing executed by the flash controller 23 composed of hardware in the form of a processing flow.

When the CPU 21 transmits an access instruction to the flash memory 20 from the personal computer 2a, as shown in the processing flow of Fig. 5, the CPU 21 first accesses the flash controller 23 in step 1 first. Send an instruction specifying the instruction.

In the next step 2, it is determined with reference to the end display register 234 of the flash controller 23 whether or not the processing for the transmitted command is terminated, and when it is determined that the processing for the transmitted command is finished, the processing is terminated.

On the other hand, if it is determined that the processing for the command sent in step 2 has not ended, the process proceeds to step 3, where the prescribed time elapses since the prescribed time has elapsed from the command transmission and the flash memory 20 does not shift to the ready state. If it is determined whether or not the prescribed time has elapsed, the process returns to step 2, and if it is determined that the prescribed time has elapsed, the process proceeds to step 4 to instruct the flash controller 23 to stop the processing. Send a stop command to end the process.

In addition, when the CPU 21 refers to the end display register 234 of the flash controller 23, it is necessary to acquire a right to use the CPU bus 27.

The CPU 21 accepts the command sent by the CPU 21, and the flash controller 23 first uses the instruction decoder 231 in the first step 1, as shown in the form of the processing flow of FIG. The command to be transmitted is interpreted, and the access process is executed to the flash memory 20 by transmitting the flash command for the interpreted command using the sequencer 232 in the next step 2.

In the next step 3, it is determined whether or not the access process is terminated by the sequencer 232, and when the end of the access process is determined, the end of the process is set in the end display register 234 to end the process.

On the other hand, if it is determined in step 3 that the access processing by the sequencer 232 has not ended, the process proceeds to step 4, it is determined whether or not the aforementioned stop command has been sent from the CPU 21, and the stop command is transmitted. If it is determined that there is no information, the process returns to step 3, and if it is determined that the stop command has been transmitted, the process proceeds to step 5, where the access process of the sequencer 232 is forcibly terminated.

In this way, when the access instruction is transmitted from the CPU 21 to the flash memory 20, the flash controller 23 transmits a flash command to the flash memory 20 to process the access to the flash memory 20. .

The CPU 21 determines that a failure has occurred in the flash memory 20 even when the flash controller 23 does not finish the processing of the transmitted flash command even after the prescribed time has elapsed. Processing is instructed to stop processing.

7 to 9 show the processing executed by the sequencer 232 included in the flash controller 23 in the form of a processing flow. Here, FIG. 7 shows a process to be executed when receiving an access instruction for writing data from the CPU 21, and FIG. 8 shows a process to be executed when receiving a read access instruction of data from the CPU 21. FIG. 9 shows a process to be executed when the data from the CPU 21 receives an erase instruction.

Next, Figs. 7 to 9 illustrate the processing executed by the sequencer 232. Figs.

When the sequencer 232 receives an access instruction for writing data from the CPU 21, the sequencer 232 enters the path processing of data recording, and as shown in the processing flow form of FIG. 27) to obtain a license. In a next step 2, a flash command of data input is sent to the flash memory 20, and in step 3, write data is sent to the flash memory 20. FIG.

Accepting the flash command of this data input, the internal controller 201 of the flash memory 20 in the command standby state writes the write data which is subsequently sent to the internal buffer 202.

When the sequencer 232 transmits write data to the flash memory 20 in step 3, the sequencer 232 transmits a flash command for writing data to the flash memory 20 in the next step 4.

The internal controller 201 of the flash memory 20, which accepts this data write flash command and is in the standby state of the command, enters a process in which data written to the internal buffer 202 is written to the flash memory cell 200, thereby entering a sequencer. It is notified about the state of the use of 232.

Next, when the sequencer 232 transmits a flash command for writing data in step 4, the sequencer 232 waits for the usage status to be notified from the flash memory 20 in the next step 5, and if the usage status is notified, returns to step 6. In progress, the right to use the CPU bus 27 is temporarily released.

During the release of the right to use the CPU bus 27, the internal controller 201 of the flash memory 20 writes data written in the internal buffer 202 to the flash memory cell 200. The sequencer 232 is notified that it is in a ready state.

Next, when the sequencer 232 releases the use of the CPU bus 27 in step 6, it waits for the ready status to be notified from the flash memory 20 in the next step 7, and if the ready status is notified, step 8 Proceeds to and acquires the right to use the CPU bus 27, and in step 9, the flash command for state acquisition is transmitted to the flash memory 20.

The internal controller 201 of the flash memory 20 which is in this state of acquiring the flash command for acquiring this state acquires the status of whether data writing is successful to the flash memory cell 200 with respect to the sequencer 232. Come to notice.

Next, when the sequencer 232 transmits the state acquisition flash command in step 9, the sequencer 232 acquires the state coming from the flash memory 20 in the next step 10, and releases the right to use the CPU bus 27 in the next step 11. In the final step 12, the processing end flag is set in the end display register 234 to end the process.

As described above, according to the present invention, as the sequencer 232 performs data write processing to the flash memory 20 which terminates with the acquisition of the state, the right of use of the CPU bus 27 is acquired until the acquisition of the state is completed. It does not take the structure to hold | maintain continuously, when the flash memory 20 internally processes and becomes a use state, it temporarily releases the license of the CPU bus 27, and the internal process is complete | finished, and the flash memory 20 terminates. When it is ready, the structure which acquires a license by using the CPU bus 27 again is taken.

Accordingly, when the flash memory 20 is in the use state, the usage right of the CPU bus 27 reaches the CPU 21, and the CPU 21 then performs a separate process of using the CPU bus 27 during this time. You can run it.

In addition, when the sequencer 232 receives an access instruction for reading data from the CPU 21, first, in step 1, as shown in the processing flow diagram of FIG. Obtain the right to use (27). In the next step 2, a flash command for reading data is sent to the flash memory 20. FIG.

A process of receiving a flash command for reading this data, and the internal controller 201 of the flash memory 20 in the standby state of the command reads the specified data from the flash memory cell 200 and receives it into the internal buffer 202. And notifies the sequencer 232 that it is in use.

Next, when the sequencer 232 transmits the flash command for reading the data in step 2, it waits for the usage status to be notified from the flash memory 20 in the next step 3, and proceeds to step 4 if the usage status is notified. The license for the CPU bus 27 is temporarily released.

During the release of the right to use this CPU bus 27, the internal controller 201 of the flash memory 20 reads data from the flash memory cell 200 to the internal buffer 202, but when this reading is finished, the sequencer 232 is notified that the device is in the ready state, and the internal buffer 202 is notified of the transmission of the read data.

Next, when the sequencer 232 releases the license of the CPU bus 27 in step 4, it waits for the ready state to be notified from the flash memory 20 in the next step 5, and proceeds to step 6 if the ready state is notified. Then, the usage right of the CPU bus 27 is acquired again.

In step 7, data transmitted from the flash memory 20 is received, and in step 8, the right to use the CPU bus 27 is released. Then, in the final step 9, the end of processing register is set in the end display register 234 to end the processing.

As described above, in accordance with the present invention, the sequencer 232 corresponds to the data read processing from the flash memory 20 which terminates the data read, and thus the right of use of the CPU bus 27 for the period until the data read is completed. When the flash memory 20 enters an internal process and enters an internal state instead of being held continuously, when the flash memory 20 enters an internal state, the license of the CPU bus 27 is temporarily released, and when the internal process ends, it becomes a ready state. Then, a configuration in which the right to use the CPU bus 27 is acquired to receive data is obtained.

Accordingly, when the flash memory 20 is in the use state, the right of use of the CPU bus 27 reaches the CPU 21, and the CPU 21 then performs a separate process of using the CPU bus 27 during this time. You can run it.

In addition, when the sequencer 232 receives an access instruction for erasing data from the CPU 21, the sequencer 232 enters a data erasing path process, and as shown in the processing flow form of FIG. 9, first, in the first step 1, the CPU bus. Obtain the right to use (27). In the next step 2, the flash command for erasing data is transmitted to the flash memory 20.

Receiving the flash command for erasing this data, the internal controller 201 of the flash memory 20 in the standby state of the command performs a process of erasing the specified data recorded in the flash memory cell 200 and performing the sequencer ( 232) is notified that it is in use.

Next, when the sequencer 232 transmits the flash command for erasing data in step 2, the sequencer 232 waits for the usage status to be notified from the flash memory 20 in the next stage 3, and proceeds to step 4 if the usage status is notified. In this way, the right to use the CPU bus 27 is temporarily released.

During the release of the right to use the CPU bus 27, the internal controller 201 of the flash memory 20 erases the designated data recorded in the flash memory cell 200, but when the erasing is completed, the sequencer 232 is terminated. You are notified that you are in the ready state.

Next, when the sequencer 232 releases the use of the CPU bus 27 in step 4, it waits for the ready status to be notified from the flash memory 20 in the next step 5, and if the ready status is notified, the process proceeds to step 6. It proceeds and acquires the usage right of the CPU bus 27 again, and transmits the flash command of a state acquisition to the flash memory 20 in next step 7.

Receiving the flash command of this state acquisition, the internal controller 201 of the flash memory 20 which is in the standby state of the command determines whether the erasure of data recorded in the flash memory cell 200 with respect to the sequencer 232 was successful. Notifies the status of

Next, in step 7, when the flash command for state acquisition is sent, the state coming from the flash memory 20 is acquired in the next step 8, and the right to use the CPU bus 27 is released in the next step 9. Then, in the last step 10, the end of the processing is terminated by setting a flag for processing termination in the end display register 234.

As described above, according to the present invention, the sequencer 232 corresponds to the data erasing process of the flash memory 20 terminated by the acquisition of the state, and the right to use the CPU bus 27 until the acquisition of the state is completed. It does not take a configuration to keep the &lt; Desc / Clms Page number 5 &gt; When is in the ready state, the usage right of the CPU bus 27 is acquired again and the state is acquired.

Accordingly, when the flash memory 20 is in the use state, the usage right of the CPU bus 27 reaches the CPU 21, and then the CPU 21 executes separate processing using the CPU bus 27 during that time. It becomes possible.

In the processing flow format of FIG. 7, the CPU in step 6 when the write state is sent in step 4, then waits for the use state to be notified from flash memory 20 in step 5, and the use state is notified. Although the configuration of releasing the right to use the bus 27 is taken, when the flash command for writing is sent, it is understood that the flash memory 20 enters the internal state by entering the internal processing, and thus the processing of step 5 is omitted. As shown in the processing flow form of FIG. 10, after sending the write flash command in step 4, it is possible to immediately proceed to step 6 to take the configuration of releasing the right to use the CPU bus 27. FIG.

In addition, in the processing flow form of FIG. 8, after transmitting the flash command of reading in step 2, waiting for the use state to be notified from the flash memory 20 in the next step 3, and when the use state is notified, step 4 In the above example, the CPU bus 27 is freed from use. However, when the flash command for reading is sent, the flash memory 20 enters the internal processing, thereby transitioning to the use state. It is possible to omit and to proceed to step 4 immediately after transmitting the write flash command in step 2, as shown in the processing flow form of FIG. 11, to take the configuration of releasing the right to use the CPU bus 27.

In the processing flow form of Fig. 9, after the flash command for erasing is sent in step 2, the next step 3 waits for the usage state to be notified from the flash memory 20, and when the usage state is notified, step 4 Has been configured to release the right to use the CPU bus 27, but since the flash memory 20 enters the internal processing when the flash command for erasing is transmitted, it is understood that the state of the CPU bus 27 is transferred to the use state. As shown in the processing flow form in FIG. 12, the processing is omitted, and after the erase flash command is transmitted in step 2, the flow proceeds to step 4 immediately, whereby the configuration of releasing the license of the CPU bus 27 can be taken. Do.

By adopting the configuration according to the processing flow format of FIGS. 10 to 12, the flash controller 23 can immediately release the unnecessary usage rights of the CPU bus 27, so that efficient operation of the usage rights of the CPU bus 27 is realized. do.

FIG. 13 shows a time chart in the case of following the processing flow format of FIG. 9, and FIG. 14 shows a time chart in the case following the processing flow format of FIG.

In the figure, XBREQ represents a license request of the CPU bus 27 transmitted by the flash controller 23, XBACK represents a permission signal of the CPU 21 to the license request of the CPU bus 27, and XFCE is enabled. Represents the chip number of the flash memory 20 to be converted, XFWP represents the release signal of the write protect of the flash memory 20, FCLE represents an instruction latch enable signal which becomes a synchronization signal of the flash command, and FALE represents an erase address. Indicates an address latch enable signal that is a synchronization signal of XFRE, XFRE indicates a read enable signal of flash memory 20, XFWE indicates a write enable signal of flash memory 20, and XFBSY indicates a flash enable signal of flash memory 20. A ready / use signal is shown, CD represents a flash command transmitted to the flash memory 20, and COMPL represents a processing end signal.

In addition, ① denotes an erase flash command (first code), ② denotes an address before erasing (first code), ③ denotes an address before erasing (second code), and ④ denotes an erase flash instruction (first code). 2 code) and flash command for status acquisition, and (5) indicates status.

As can be seen from the time charts of Figs. 13 and 14, when the processing flow format of Fig. 9 is followed, the flash memory 20 enters the internal processing in response to the transmission of the flash command for erasing, thereby transitioning to the use state. If it is detected, the processing to release the right of use of the CPU bus 27 is taken. However, in the case of following the processing flow form of FIG. A configuration for processing to release the right of use (27) is taken.

As described above, the internal controller 201 of the flash memory 20 erases data of the flash memory cell 200 in response to a command transmitted by the flash controller 23, and the internal buffer 202. Processing of notifying the flash controller 23 of the usage status while data is being written from the flash memory cell 200 to the internal buffer 202 while data is being written from the flash memory cell 200. do.

By using the characteristics of the flash memory 20, it is possible to easily check whether the flash memory 20 is actually mounted and whether the mounted flash memory 20 is broken.

15 and 16 show one embodiment of the processing flow executed by the CPU 21 to realize this inspection processing.

When the memory card 1a is activated, the CPU 21 enters into execution of the inspection program developed in the ROM 22, and as shown in the processing flows of Figs. Configuration information for recording information such as the number of flash memories 20 recorded in the memory 20 is read. As described above, since the configuration information such as the number of flash memories 20 to be mounted is recorded in the head flash memory 20, first, the configuration information is read first.

In the next step 2, it is judged whether or not the configuration information has been read from the head flash memory 20 in accordance with the process of step 1, and when it is determined that it is not read, the head flash memory 20 is abnormal (not loaded). Or failure), the process proceeds to step 8 to record the system abnormality to terminate the processing.

Although not described in FIG. 2, as shown in FIG. 17, the host controller 24 is accessible by the personal computer 2a to notify the personal computer 2a of the state of the memory card 1a. The status register 24 is prepared. Next, when the CPU 21 determines that the head flash memory 20 has an error in step 2, the system 21 records a system error in the system status register 24 to notify the personal computer 2a of the error. The process ends.

On the other hand, when it is determined in step 2 that the configuration information can be read out from the head flash memory 20, the process proceeds to step 3, where the head next flash memory 20 is assigned to the variable i representing the chip number of the flash memory 20. Is set to "1" indicating the chip number.

In the next step 4, a read command is transmitted to the flash memory 20 of the chip number indicated by the variable i.

Although not described in FIG. 2, as shown in FIG. 17, the sequencer 232 of the flash controller 23 includes a flash state register 2320 (the end shown in FIG. 4) which holds state information of each flash memory 20. Display register 234 is also included therein). After the sequencer 232 transmits a read command to the flash memory 20 in response to an instruction from the CPU 21, the flash memory 20 When is shifted to the use state, it detects it and writes to the flash state register 2320 the effect.

Next, when the read command is transmitted to the flash memory 20 of the chip number indicated by the variable i in step 4, the flash memory 20 is referred to in step 5 by referring to the flash status register 2320 provided by the sequencer 232. Check the status of).

Next, in accordance with the check processing in step 6 to step 5, it is determined whether the flash memory 20 of the number indicated by the variable i has shifted to the use state, and when it is determined that it has not shifted to the use state, the process proceeds to step 7 It is determined whether the prescribed time has elapsed from the transmission of the read command.

When it is determined that the prescribed time has not elapsed from the transmission of the read command in accordance with the process of step 7, the process returns to step 5, and the check process of whether the flash memory 20 has shifted to the use state is continued, and the specified time is passed. When it is determined that the elapsed time has passed, the process proceeds to step 8, where the system error is recorded in the system status register 24 included in the host controller 24, and the processing ends.

In this way, even if the prescribed time elapses from the transmission of the read command, when detecting that the flash memory 20 of the chip number indicated by the variable i has not moved to the use state, the flash memory 20 is abnormal (not mounted). Failure), the process proceeds to step 8 to record the system abnormality to terminate the processing.

On the other hand, when it is determined in step 6 that the flash memory 20 has moved to the use state in response to the transmission of the read command, the process proceeds to step 9 (process flow in FIG. 16), in which the value of the variable i is incremented by one, In the next step 10, it is determined whether or not the value of the incremented variable i has exceeded the number of chips specified by the configuration information acquired in step 1, and when it is determined that the value is not exceeded, the process returns to step 4 and reads to the next flash memory 20. When it is judged that the command has been sent and has passed, the process proceeds to step 11, where the system normal is recorded in the system status register 24 provided in the host controller 24, and the process ends.

That is, when the memory card 1a is activated, the CPU 21 flashes the inspection target flash memory 20 with the chip enable signal XFCE via the flash controller 23 as shown in the time chart of FIG. 18. ), First, in synchronization with the latch enable signal FCLE and the write enable signal XFWE, the read command “00H” is transmitted to the flash memory 20 to be inspected, and then the address is continued. In synchronization with the latch signal FALE and the write enable signal XFWE, the read address signals "A0-7, A8-16, A17-23" are transmitted to the flash memory 20 to be inspected, and these transmissions are transmitted. In response, when the flash memory 20 to be inspected enters the internal processing (the process of reading the read data from the flash memory cell 200 into the internal buffer 202), the flash memory 20 enters into the use state. Is to determine that the operation is possible.

Although not described in FIG. 2, as shown in FIG. 17, the flash controller 23 includes a register group 235 (shown in FIG. 4) that holds an address, an instruction, a chip number, or the like transmitted by the CPU 21. The command register 230 is also included therein), and in the internal controller 201 of the flash memory 20, a register group 2010 for holding an address, a command, and the like transmitted by the flash controller 23 is prepared. The read command &quot; 00H &quot; sent by the CPU 21 is recorded in the register group 235 of the flash controller 23, and then according to the instruction of the flash controller 23, the register group 2010 of the flash memory 20. Will be written to

In this way, when the memory card 1a is activated, the CPU 21 transmits a read command to the flash memory 20 by executing the processing flows of FIGS. 15 and 16, and flashes in response to the transmission of the read command. Checks whether the memory 20 transitions to the use state, and when there is a flash memory 20 that does not enter the use state, writes the system error to the system status register 24 of the host controller 24, and all flashes. When the memory 20 transitions to the use state, the system state is recorded in the system status register 24 of the host controller 24 to determine whether the mounted flash memory 20 can be operated on the personal computer 2a. It is processing to notify. Here, in the execution of this inspection process, the configuration in which the read command is transmitted is adopted because, when the write command is transmitted, data irrespective of the original process is recorded in the flash memory 20, and This is because the data is erased from the flash memory 20 when the erase command is transmitted. However, when an error does not occur even when such an occurrence occurs, it is also possible to take a configuration in which the write command and the erase command are transmitted instead of the read command.

In the processing flows of Figs. 15 and 16, when the flash memory 20 detects the transition to the use state in response to the transmission of the read command, the configuration is immediately determined that the flash memory 20 at the destination of the read command is normal. It is also possible to take a configuration in which the flash memory 20 is judged to be normal after confirming that the flash memory 20 moves to the ready state again.

In taking this configuration, the CPU 21 executes the processing flow of FIG. 19 instead of the processing flow of FIG. 16.

That is, when it is determined in step 6 of the processing flow of FIG. 15 that the flash memory 20 has transitioned to the use state in response to the transmission of the read command, the sequencer 232 in step 9 as shown in the processing flow of FIG. 19. The state of the flash memory 20 is checked by referring to the flash state register 2320 included in.

Next, in step 10, in accordance with the check processing in step 9, it is determined whether the flash memory 20 of the chip number indicated by the variable i has shifted to the ready state, and if it is determined that it has not shifted to the ready state, step 11 It proceeds to and determines whether the prescribed time has elapsed since the transition to the use state.

According to the process of step 11, when it is determined that the prescribed time has not elapsed since the transition to the use state, the process returns to step 9, and the check processing of whether the flash memory 20 has shifted to the ready state is continued and prescribed. When it is determined that the time has elapsed, the process proceeds to step 12, where the system error is recorded in the system status register 24 included in the host controller 24, and the processing ends.

On the other hand, if it is determined in step 10 that the flash memory 20 has moved to the ready state, the process proceeds to step 13, in which the value of the variable i is incremented by one, and in step 14, the value of the incremented variable i is shown in FIG. If it is determined whether the number of chips specified by the configuration information acquired in step 1 of the processing flow is exceeded or not, the flow returns to step 4 of the processing flow of FIG. 15 to read the next flash memory 20. If it is determined that the data has been exceeded, the process proceeds to step 15, where the system normal is recorded in the system status register 24 provided in the host controller 24, and the processing ends.

In this way, in the processing flow of Figs. 15 and 16, if the flash memory 20 detects the transition to the use state in response to the transmission of the read command, it is immediately configured to determine that the flash memory 20 at the destination of the read command is normal. However, the CPU 21 executes the processing flow of FIG. 19 instead of the processing flow of FIG. 16 to confirm that the flash memory 20 transitions to the ready state again, and judges that it is normal.

Further, in the processing flows of Figs. 15 and 16, when it is determined that one flash memory 20 is abnormal, a configuration of stopping the check processing of whether the remaining flash memory 20 is normal is employed, but the remaining flash memory ( It is also possible to adopt a configuration in which the check processing of 20) is continued, and the configuration in which the number of flash memories 20 is abnormal is written into the system status register 24.

In addition, although the processing flow of FIG. 15 and FIG. 16 took the structure which enters an inspection process when the memory card 1a is started, in addition, when the memory card 1a rises or an abnormality arises in the memory card 1a, In some cases, the inspection process may be performed at a different timing as when the user returns from the user.

Although the present invention has been described in accordance with the illustrated embodiments, the present invention is not limited thereto. For example, in the embodiment, the present invention has been described by taking the mounting of the flash memory 20 as a specific example, but the present invention is not limited to the application of the flash memory 20, but is used by entering into the internal processing of the memory control. Any memory having an internal processing function that takes a configuration of outputting a signal can be applied as it is.

In the embodiment, the present invention has been described with reference to the application to the memory card 1a as a specific example. However, the present invention is not limited to the memory card 1a, but can be widely applied to a general memory device.

As described above, in the present invention, when the memory having the function of processing the internal memory is subjected to the control, the internal processing function is adopted when the memory having the internal processing function and the CPU and the controller are connected by a common bus. The controller acquires when the memory having the internal processing function enters the internal processing in response to a command to be sent by the controller, paying attention to the characteristic that the memory having the memory is in use state when it enters the internal processing of the memory control. Since the right to use the common bus is temporarily released, the use of the common bus is unnecessarily maintained.

As a result, the CPU can execute separate processing using the common bus, thereby realizing the efficient operation of the usage right of the common bus, thereby improving the processing efficiency.

In addition, the present invention has a configuration in which a memory having an internal processing function having a function of internal processing of memory control is controlled, and a memory is connected to a CPU having an internal processing function, and a controller is connected to a common bus. At this time, paying attention to the characteristic that a memory having an internal processing function enters a used state when it enters the internal processing of memory control, when the memory having an internal processing function transmits a command causing a use state, the controller executes the internal processing function. The processing is performed to immediately release the common bus without confirming that the provided memory is shifted to the use state, thereby eliminating the need to use the common bus unnecessarily.

As a result, the CPU can execute separate processing using the common bus, thereby realizing the efficient operation of the usage right of the common bus, thereby improving the processing efficiency.

In the present invention, the internal processing that is to be mounted using the characteristic that a memory having an internal processing function having a function of internally processing memory receives a command and enters an internal state by entering the internal processing of the memory control, is used. Sends a command to a memory having a function, and in response, checks whether the memory having an internal processing function shifts to a used state (and also checks whether or not the state shifts to a ready state). Since the memory having the internal processing function is actually mounted and whether the memory having the internal processing function is mounted is checked to determine whether or not the equipped memory is actually mounted, Extremely simple to check whether the memory with internal processing function It can be so.

On the other hand, conventionally, a configuration is provided in which predetermined data is written to the memory, followed by reading of the data, and a check is made to determine whether the memory is normal by checking whether the read data is consistent with the recorded data. Although the search is performed, even if such a complicated order is not followed, it is possible to check whether or not the memory having the internal processing function is actually mounted and whether the memory having the internal processing function is broken.

Claims (18)

The internal processing function by acquiring a license for a bus that uses a memory having a function of internally processing memory control using an internal buffer, and using the other processing unit to send a command to a memory having the internal processing function. A memory control method for controlling a memory having: After sending the command to the memory having the internal processing function, releasing the right to use the bus when the memory with the internal processing function is in use during processing; Waiting for the memory with the internal processing function to transition from a use state to a ready state, And when the memory having the internal processing function detects the transition to the ready state when the standby state is reached, processing to acquire a right to use a bus and continue the processing. The internal processing function by acquiring a license for a bus that uses a memory having a function of internally processing memory control using an internal buffer, and using the other processing unit to send a command to a memory having the internal processing function. A memory control method for controlling a memory having: When a command for generating a usage state of the memory having the internal processing function is sent to the memory having the internal processing function, the right to use the bus without confirming that the memory having the internal processing function is shifted to the usage state. Liberated, Waiting for the memory with the internal processing function to be in use state in response to the sending of the command to transition to a ready state, And when the memory having the internal processing function detects the transition to the ready state when in the standby state, the process of acquiring the right to use the bus and continuing the processing. The internal processing according to claim 1 or 2, wherein when the memory having the internal processing function detects the elapsed time of a state in which the memory does not move to a ready state, and detects the elapse of the prescribed time by the detection processing, the internal processing is performed. And processing to forcibly terminate the control process of the memory having a function. The method according to any one of claims 1 to 3, wherein the command is transmitted to a memory having an internal processing function at the time of startup of the memory having the internal processing function, And checking whether or not the memory having the internal processing function is shifted to the use state to determine whether the memory having the internal processing function is connected or not. The method according to any one of claims 1 to 3, wherein at the time of startup of the memory having an internal processing function, a command is sent to the memory having the internal processing function, And checking whether or not the memory having the internal processing function is connected to the ready state by checking whether the memory having the internal processing function is in the ready state after the transition to the use state. A CPU having a CPU, a memory having a function of internally processing memory control using an internal buffer, and a controller for acquiring a right to use a common bus and sending a command to a memory having the internal processing function; And a memory having an internal processing function and a memory device to which the controller is connected, The controller, First execution means for releasing the right to use the bus when the command is sent to a memory with the internal processing function and then the memory with the internal processing function shifts to a use state during processing; Second execution means for waiting for the memory with the internal processing function to transition from a use state to a ready state by the execution processing of the first execution means; When waiting for the memory with the internal processing function to transition to the ready state by the execution processing of the second execution means, if it is detected that the memory with the internal processing function is shifting to the ready state, And third execution means for acquiring a usage right and continuing the processing. A CPU having a CPU, a memory having a function of internally processing memory control using an internal buffer, and a controller for acquiring a right to use a common bus and sending a command to a memory having the internal processing function; And a memory having the internal processing function and the controller connected thereto. The controller, When a command for generating a usage state of the memory with the internal processing function is sent to the memory with the internal processing function, the bus with the internal processing function is not confirmed to move to the use state, First execution means for releasing a license, Second execution means for waiting for the memory with the internal processing function to be in a use state in response to the transmission of the command to transition to a ready state by the execution processing of the first execution means; When the memory having the internal processing function is shifted to the ready state by the execution processing of the second execution means, if the memory having the internal processing function is shifted to the ready state, the right to use the bus And third execution means for acquiring the data and continuing the processing. 8. The apparatus according to claim 6 or 7, further comprising: detecting means for operating on said CPU and monitoring the operating state of said controller to detect the passage of time in a state in which the memory with said internal processing function does not transition to a ready state; And instructing means for instructing the controller to forcibly terminate the control process of the memory having the internal processing function when the detection means detects the elapse of a prescribed time. Memory device. 9. The apparatus according to any one of claims 6 to 8, wherein the command is transmitted to a memory having said internal processing function via said controller when operating on said CPU and starting up said memory having said internal processing function. A transmission means, In response to a command sent by the transmitting means, it is checked whether or not the memory with the internal processing function is shifted to a use state in response to a command transmitted by the transmitting means to determine whether the memory with the internal processing function is connected or not; And a judging means for judging. The transmission means according to any one of claims 6 to 8, which operates on the CPU and transmits a command to a memory having the internal processing function via a controller when the memory having the internal processing function is activated. and, In response to a command transmitted by the transmitting means, checking whether the memory with the internal processing function is shifted to the ready state after the transition to the use state and checking the memory of the memory with the internal processing function. And determining means for determining whether or not the device is connected. A memory control method for controlling a memory having a function of internally processing memory control by using an internal buffer, At the start of the memory with the internal processing function, a command is sent to the memory with the internal processing function, And determining whether the memory having the internal processing function is connected or not by checking whether the memory having the internal processing function is shifted to a use state. A memory control method for controlling a memory having a function of internally processing memory control by using an internal buffer, At the start of the memory with the internal processing function, a command is sent to the memory with the internal processing function, And checking whether or not the memory having the internal processing function is connected to the ready state by checking whether the memory having the internal processing function is in the ready state after the transition to the use state. The memory control method according to claim 11 or 12, wherein at the time of startup of the memory having the internal processing function, a read command is sent to the memory having the internal processing function. Controlling a memory having an internal processing function by sending a command to a CPU, a memory having a function of internally processing memory control using an internal buffer, and a memory having the internal processing function in response to a CPU instruction; A memory device having a controller, Transmitting means for operating on the CPU and transmitting a command to the memory having an internal processing function through the controller when the memory having the internal processing function is activated; In response to a command sent by the transmitting means, it is checked whether or not the memory with the internal processing function transitions to the ready state, and whether or not the memory with the internal processing function is connected and whether or not it has failed; And a judging means for judging. Control a CPU, a memory having a function of internally processing memory control using an internal buffer, and a memory having the internal processing function by sending a command to a memory having the internal processing function in response to an instruction of the CPU A memory device having a controller for Transmitting means for operating on the CPU and transmitting a command to the memory having the internal processing function via the controller when the memory having the internal processing function is activated; A memory having the internal processing function, which is operated on the CPU and in response to a command sent by the transmitting means, checks whether or not the memory having the internal processing function shifts to a ready state after transitioning to a use state; And determining means for determining whether a device is connected to the device and whether there is a failure. 16. The memory device according to claim 14 or 15, wherein the transmitting means processes the read command to be transmitted to a memory having the internal processing function. The internal processing function is connected through a memory and a common bus having a function of internally processing memory control using a CPU and an internal buffer, obtaining a license of the bus, and sending a command to a memory having the internal processing function. As a controller to control the equipped memory, First execution means for releasing the right to use the bus when the command is sent to a memory having an internal processing function and then the memory having the internal processing function shifts to a use state during processing; Second execution means for waiting for the memory with the internal processing function to transition from a use state to a ready state by execution processing of the first execution means; When waiting for the memory with the internal processing function to transition to the ready state by the execution processing of the second execution means, if it is detected that the memory with the internal processing function is shifting to the ready state, And third execution means for acquiring the usage right and continuing the processing. The internal processing function is connected through a memory and a common bus having a function of internally processing memory control using a CPU and an internal buffer, obtaining a license of the bus, and sending a command to a memory having the internal processing function. As a controller to control the equipped memory, When a command for generating a usage state of the memory having the internal processing function is sent to the memory having the internal processing function, the right to use the bus without confirming that the memory having the internal processing function is shifted to the use state. First execution means for releasing, Second execution means for waiting for a memory having an internal processing function to be in a use state in response to transmission of an instruction by the execution processing of said first execution means to transition to a ready state; When waiting for the memory with the internal processing function to transition to the ready state by the execution processing of the second execution means, if it is detected that the memory with the internal processing function is shifting to the ready state, And third execution means for acquiring the usage right and continuing the processing.