JP2000105734A - Method for controlling memory, memory device, and controller - Google Patents

Abstract

PROBLEM TO BE SOLVED: To efficiently operate the usage of a bus concerning a memory control method by which memory control is executed by acquiring the usage of the bus to be also used for the other processing unit and issuing a command to a memory with internal processing function. SOLUTION: While considering that the memory 10 with internal processing function is shifted to be in a busy state when the memory 10 starts internal processing, after the command is issued, when the memory 10 with internal processing function shifting to be in the busy state in the middle of processing, the usage of a bus 13 is released or when issuing a command for calling the busy state, the usage of the bus 13 is released without confirming the shift of the memory 10 with internal processing function to busy state and continuously, the shift of the memory 10 with internal processing function from busy state to ready state is waited. In such a waiting state, when the shift of the memory 10 with internal processing function to the ready state is detected, the usage of the bus 13 is acquired so that processing can be continued.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory having an internal processing function having a function of performing an internal processing of a memory control. A memory control method for controlling a memory with an internal processing function by issuing a command; and a controller for acquiring a right to use a CPU, a memory with an internal processing function, and a common bus and issuing a command to the memory with an internal processing function. And a memory device in which the CPU, the memory with the internal processing function, and the controller are connected to the common bus, and the CPU and the memory with the internal processing function are connected via the common bus, and the right to use the bus is acquired. A controller that controls the memory with the internal processing function by issuing a command to the memory with the internal processing function. , The memory control method for realizing the efficient operation of the use right of the bus, a memory device and a controller.

2. Description of the Related Art A memory device such as a memory card having a memory is provided with a hardware-structured controller for controlling the memory separately from a CPU for receiving an instruction from a host.
There is an apparatus configuration in which a memory is controlled by issuing a memory control command to the memory in response to a command issued by U.

When a memory having a function of performing internal processing of memory control is mounted as a memory in a memory device having such a device configuration, processing efficiency is improved by constructing a configuration adapted to the characteristics of such a memory. Needs to be improved.

[0004]

2. Description of the Related Art In addition to a CPU for receiving an instruction from a host, a configuration having a hardware-structured controller for controlling a memory is adopted.
There is a memory device that controls a memory by issuing a memory control command to the memory in response to a command issued by the memory device.

In a conventional memory device having this configuration, as shown in FIG. 20, a bus (described as a CPU bus in the figure) connecting between a CPU and a controller and a bus between the controller and the memory are used. Is connected to a separate bus (denoted as a memory bus in the figure).

The bus selector shown in the figure selects a memory bus when the controller is in operation, thereby connecting the memory and the buffer, and selects a CPU bus when the controller is inoperative. By doing so, it operates to connect between the CPU and the buffer.

From now on, in the memory device adopting this configuration, the controller does not voluntarily acquire the right to use the memory bus, and after issuing a command to the memory, From memory,
Since the process of acquiring memory status information for the command is performed, even after acquiring the right to use the memory bus and issuing the command to the memory, the right to use the memory bus is maintained without being released. In the meantime, a command for acquiring the status information of the memory is issued, so that the status information of the memory for the command is acquired.

[0008]

Recently, the demand for miniaturization of a memory device having the above-mentioned structure has been increasing, and the demand for miniaturization of the memory device has been increasing. .

From now on, instead of having the above-mentioned two buses, the CPU bus and the memory bus, these two buses will be used.
There is a need to share one bus. On the other hand, recently, flash memories have been spreading. This flash memory is an EEPROM that has the function of erasing the contents of the memory all at once. It is expected that it will be installed in various electronic devices because it has the feature that it can achieve a compact size due to its high degree of integration. Is done.

This flash memory employs a configuration in which a controller and a buffer are provided in order to realize high-speed processing. When a memory control command is issued from an external controller, the internal controller responds to the command. After erasing the data in the flash memory or storing external data sent via the bus in the internal buffer, writing data to the flash memory from the internal buffer or reading data from the flash memory After storing the data in the internal buffer, the data is output to the outside via the bus.

In this process, while the internal controller is erasing data in the flash memory, while the internal controller is writing data from the internal buffer to the flash memory, or when the internal controller is writing data from the flash memory to the internal buffer. While reading data, the flash memory is in a busy state because it cannot communicate with the outside.

In the memory device having the above configuration, a flash memory is mounted as a memory, and a configuration in which a CPU bus and a memory bus are used in common is adopted. In accordance with the extension of the configuration, the controller does not release the bus usage right after acquiring the bus usage right and issuing a command to the flash memory until obtaining the flash memory status information. With such a configuration, there is a problem that the controller wastefully holds the right to use the bus.

That is, when a command is issued to the flash memory, the flash memory is then busy by entering internal processing using the internal controller.
During this time, the controller holds the right to use the bus without having to hold the right to use the bus.
There was a problem that U could not use that bus.

The present invention has been made in view of the above circumstances, and a memory having an internal processing function is to be controlled.
Efficient operation of the bus usage right when controlling the memory with the internal processing function by acquiring the right to use the bus also used by other processing units and issuing commands to the memory with the internal processing function And a controller that obtains the right to use the CPU, the memory with the internal processing function, and the common bus, and issues a command to the memory with the internal processing function. When the memory with the processing function and the controller are connected, the provision of a new memory device for realizing the efficient operation of the right to use the bus, and the communication between the CPU and the memory with the internal processing function via a common bus Connected and obtains the right to use the bus and issues a command to the memory with internal processing function to control the memory with internal processing function. Te, for the purpose of and provide for a new controller to achieve the efficient operation of the right to use the bus.

[0015]

FIG. 1 shows the principle configuration of the present invention. In FIG. 1, reference numeral 1 denotes a memory device having the present invention, which is a memory 10 having an internal processing function having a function of performing internal processing of memory control using an internal buffer, and a CPU 11 receiving an access request issued by the host device 2.
A controller 12 that controls the memory 10 with an internal processing function by issuing a memory control command in response to an instruction from the CPU 11, and a common bus that connects the memory 10 with an internal processing function, the CPU 11, and the controller 12. Reference numeral 13 denotes a host device, which issues a request to the memory device 1 to access the memory 10 with an internal processing function.

The controller 12 receives the status information from the common bus 13
First executing means 14 for performing processing for releasing the right to use
A second execution unit for performing a process of waiting for the memory with an internal processing function to transition from a busy state to a ready state;
And a third execution unit 16 that obtains the right to use the common bus 13 and performs processing to continue processing.

Reference numeral 17 denotes a detecting means, which operates on the CPU 11 and monitors the operating state of the controller 12, thereby detecting the lapse of time when the memory with internal processing function 10 does not shift to the ready state.

Indicating means 18 operates on the CPU 11 and forcibly instructs the controller 12 to control the memory 10 with the internal processing function when the detecting means 17 detects the elapse of a specified time. To end.

In the memory device 1 of the present invention configured as described above, when the memory with internal processing function 10 is accessed in response to a request from the host device 2, the first execution means 14 of the controller 12 After the command is issued to the memory 10 with the internal processing function, and the memory 10 with the internal processing function shifts to the busy state during the processing that ends with the acquisition of status information or the like, the common bus 13
Release the right to use

In response to this execution processing, the controller 12
The second executing means 15 of the memory 10 with the internal processing function
Waits for a transition from the busy state to the ready state. When the third execution means 16 of the controller 12 detects that the memory with internal processing function 10 shifts to the ready state while in this waiting state, the third execution means 16 acquires the right to use the common bus 13 and continues the processing. By doing so, processing such as acquiring status information of the memory 10 with an internal processing function is performed.

At this time, the detecting means 17 monitors the operating state of the controller 12 to detect the lapse of time in which the memory 10 with the internal processing function does not shift to the ready state. Instructs the controller 12 to forcibly end the control process of the memory with internal processing function 10 when the detecting means 17 detects the elapse of the specified time.

As described above, in the present invention, the memory 10 with the internal processing function having the function of performing the internal processing of the memory control using the internal buffer is to be controlled, and the memory 10 with the internal processing function, the CPU 11 and the controller 12 Is connected by a common bus 13, and pays attention to the characteristics of the memory 10 having an internal processing function having an internal processing function, and responds to a command issued by the controller 12. When the memory 10 enters the internal processing, the controller 12 performs processing to temporarily release the acquired right to use the common bus 13, so that the controller 12 may uselessly hold the right to use the common bus 13. Disappears.

As a result, the CPU 11
Can be executed, and the efficient use of the right to use the common bus 13 can be realized, so that the processing efficiency can be improved.

Further, in the memory device 1 of the present invention configured as described above, when the memory 10 with the internal processing function is accessed in response to the request from the host device 2, the first execution means of the controller 12 is used. 14 issues a command that causes the internal processing function memory 10 to be in a busy state to the internal processing function memory 10 without confirming that the internal processing function memory 10 shifts to the busy state. Release the right to use

In response to this execution processing, the controller 12
The second executing means 15 of the memory 10 with the internal processing function
After the memory 10 with the internal processing function enters the internal processing in response to the issuance of the command causing the busy state, the memory 10 shifts to the busy state, and when the internal processing ends, the memory 10 with the internal processing function is changed from the busy state. Wait for transition to ready state.

In this waiting state, when the third execution means 16 of the controller 12 detects that the memory with internal processing function 10 shifts to the ready state, it acquires the right to use the common bus 13 and By continuing the processing, processing such as acquiring status information of the memory 10 with the internal processing function is performed.

At this time, the detecting means 17 monitors the operating state of the controller 12 to detect the lapse of time in which the memory 10 with the internal processing function does not shift to the ready state. Instructs the controller 12 to forcibly end the control process of the memory with internal processing function 10 when the detecting means 17 detects the elapse of the specified time.

As described above, according to the present invention, the memory 10 with the internal processing function having the function of performing the internal processing of the memory control using the internal buffer is to be controlled, and the memory 10 with the internal processing function, the CPU 11 and the controller 12 Is connected by the common bus 13, and the memory 10 with the internal processing function enters the internal processing by paying attention to the characteristics of the memory 10 with the internal processing function having the internal processing function. When issuing a command to cause a state, the controller 12 immediately releases the right to use the common bus 13 without confirming that the memory 10 with the internal processing function shifts to the busy state. The right to use the common bus 13 is not retained.

As a result, the CPU 11
Can be executed, and the efficient use of the right to use the common bus 13 can be realized, so that the processing efficiency can be improved.

[0030]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail according to embodiments. FIG. 2 shows an example of a circuit configuration of a memory card 1a having the present invention.

The memory card 1a has a connector and is used by being detachably connected to a slot provided in a host such as a personal computer or a digital camera. At this time, power is supplied to the memory card 1a from the host at the connection destination via the connector.

The memory card 1a, as shown in FIG.
A plurality of flash memories 20 (only one may be mounted) are mounted, and access processing to the flash memories 20 is executed in response to an access request issued by the personal computer 2a. In addition to the flash memory 20, R
CPU 21 with OM22, flash controller 2
3, host controller 24, buffer 25, RAM2
6 and the like, and a CPU bus 27 for connecting them.

As shown in FIG. 3, the flash memory 20 includes a flash memory cell 200 and an internal controller 2.
01 and an internal buffer 202. When the flash controller 23 issues a memory control command (hereinafter, a command issued by the flash controller 23 is referred to as a flash command), the internal controller 201 responds thereto. To erase data stored in the flash memory cell 200,
The data sent from the bus 27 is stored in the internal buffer 202.
Then, data is written from the internal buffer 202 to the flash memory cell 200, or data is read from the flash memory cell 200 to store the data in the internal buffer 20.
After storing in the CPU bus 2
7 and the like.

At the time of performing this processing, the internal controller 201 outputs a ready / busy signal indicating whether the flash controller 23 is in a ready state or a busy state to the flash controller 23.

The ready / busy signal is output while the data in the flash memory cell 200 is being erased, while data is being written from the internal buffer 202 to the flash memory cell 200, or when the flash memory cell 200 is being written to the internal buffer 202. While the data is being read, the busy state is displayed, and otherwise, the ready state is displayed.

The ROM 22 stores a program for realizing access to the flash memory 20.
When the personal computer 2a issues an access request, the PU 21 issues an access instruction to the flash controller 23 according to the program, thereby performing processing for executing access to the flash memory 20.

More specifically, the head flash memory 20 has a flash memory 20 mounted therein.
Since configuration information such as the number of
1 specifies the total memory capacity by reading the memory capacity per chip recorded in the flash memory 20 and its configuration information in accordance with a program stored in the ROM 22 when the memory card 1a is started, and specifying the total memory capacity. When the personal computer 2a notifies the personal computer 2a or issues an access request by designating an address during normal operation, the flash memory to be accessed is determined from the memory capacity per chip according to a program stored in the ROM 22. By specifying the chip number of the memory 20 and issuing an access instruction to the flash controller 23, the flash memory 2
Processing such as execution of access to 0 is performed.

The flash controller 23 has a CPU 2
By issuing a flash command to the flash memory 20 when an instruction to access the flash memory 20 is issued from 1, access to the flash memory 20 is executed. The buffer 25 stores the flash memory 20
And the data read from the flash memory 20. The host controller 24 performs an interface process with the personal computer 2a. The RAM 26 is used as a working memory of the CPU 21 and the like.

The flash controller 23 executes a process for accessing the flash memory 20 as shown in FIG.
As shown in the figure, a command register 230 for receiving a command issued by the CPU 21 and a command register 230
Command decoder 2 for decoding the command held by
31, a sequencer 232 having a hardware configuration for performing a memory control sequence operation according to the decoding result of the command decoder 231, and a hardware configuration for issuing a flash command to the flash memory 20 in response to an instruction from the sequencer 232. The flash memory includes a flash command issuing mechanism 233 and an end display register 234 that stores a flag indicating whether the sequence operation of the sequencer 232 has been completed or not.

The flash commands issued by the flash controller 23 include a data input command, a write command, a read command, an erase command, and a status command.

When this data input command is issued from the flash controller 23, the internal controller 201 of the flash memory 200 performs a process of writing data requested to be written to the internal buffer 202. Also,
When a write command is issued, a process of writing data written in the internal buffer 202 to the flash memory cell 200 is performed. When a read command is issued, the designated data is read from the flash memory cell 20 and written to the internal buffer 202, and is written to the CP 202.
A process for outputting to the U bus 27 is performed. When an erase command is issued, a process of erasing data specified from the flash memory cell 20 is performed. When a status command is issued, a process for returning status information to the flash controller 23 is performed.

When performing this processing, the internal controller 201 executes the flash memory cell 20 as described above.
While the data of 0 is being erased, the data is being written from the internal buffer 202 to the flash memory cell 200, or the data is being read from the flash memory cell 200 to the internal buffer 202, the ready / busy signal is output. This is used to display a busy state to the flash controller 23.

FIG. 5 shows an embodiment of the processing flow executed by the CPU 21, and FIG. 6 shows the processing executed by the flash controller 23 composed of hardware in the form of a processing flow.

The CPU 21 is a personal computer 2
When an access instruction to the flash memory 20 is issued from a, as shown in the processing flow of FIG. 5, first, in step 1, a command specifying the access instruction is issued to the flash controller 23.

Subsequently, in step 2, by referring to the end display register 234 of the flash controller 23, it is determined whether or not the processing for the issued command has been completed, and it is determined that the processing for the issued command has been completed. If it is determined, the process ends.

On the other hand, when it is determined in step 2 that the processing for the issued command has not been completed,
Proceeding to step 3, when the specified time has elapsed since the command was issued, it is determined whether or not the time during which the flash memory 20 does not shift to the ready state has elapsed, and it is determined that the specified time has not elapsed If it is determined that the specified time has elapsed, the process proceeds to step 4 where the flash controller 2
Then, a stop command for instructing stop of the process is issued to No. 3, and the process ends.

When the CPU 21 refers to the end display register 234 of the flash controller 23,
It is necessary to acquire the right to use the CPU bus 27 in advance. Upon receiving the command issued by the CPU 21, the flash controller 23 firstly executes the command decoder 2 in step 1 as shown in the processing flow format of FIG.
31, the command issued by the CPU 21 is interpreted, and then, in step 2, a flash command corresponding to the interpreted command is issued using the sequencer 232 to execute access processing to the flash memory 20. .

Subsequently, in step 3, the sequencer 232
It is determined whether or not the access processing has been completed, and when it is determined that the access processing has been completed, a processing end flag is set in the end display register 234, and the processing ends.

On the other hand, if it is determined in step 3 that the access processing by the sequencer 232 has not been completed, the process proceeds to step 4 where it is determined whether the above-described stop command has been issued from the CPU 21 and the stop is performed. When it is determined that the command has not been issued, the process returns to step 3, and when it is determined that the stop command has been issued, the process proceeds to step 5, where the access process of the sequencer 232 is forcibly terminated.

As described above, when the CPU 21 issues an access instruction to the flash memory 20, the flash controller 23 issues a flash command to the flash memory 20 so that the flash memory 2
Processing will be performed to execute access to 0.

When the CPU 21 does not end the processing for the issued flash command even after the specified time has elapsed, the CPU 21 determines that a failure has occurred in the flash memory 20 and sends the processing to the flash controller 23. Will be processed so as to instruct to stop.

FIGS. 7 to 9 show the processing executed by the sequencer 232 of the flash controller 23 in the form of a processing flow. Here, FIG.
8 shows a process executed when receiving a data write access instruction from the CPU 21. FIG. 8 shows a process executed when receiving a data read access instruction from the CPU 21, and FIG. It shows a process executed when receiving an instruction.

Next, the processing executed by the sequencer 232 will be described with reference to FIGS. When the sequencer 232 receives the data write access instruction from the CPU 21, the sequencer 232 enters a data write routine process, and first, as shown in the processing flow form of FIG. Acquire rights. Subsequently, in step 2, a data input flash command is issued to the flash memory 20, and in subsequent step 3, write data is sent to the flash memory 20.

In response to this data input flash command, the flash memory 20 in a command waiting state
The internal controller 201 stores the write data transmitted subsequently to the internal buffer 202.

The sequencer 232 sends the write data to the flash memory 20 in step 3, and then issues a data write flash command to the flash memory 20 in step 4.

In response to the flash command for writing the data, the internal controller 201 of the flash memory 20 which is in a command waiting state sends the internal buffer 20.
By starting the process of writing the data stored in the flash memory cell 200 into the flash memory cell 200, the sequencer 232 is notified that the flash memory cell 200 is busy.

When the sequencer 232 issues a data write flash command in step 4, the sequencer 232 waits for the busy state to be notified from the flash memory 20 in step 5, and then notifies the busy state. Then, the process proceeds to step 6, where the right to use the CPU bus 27 is temporarily released.

During the release of the right to use the CPU bus 27,
The internal controller 201 of the flash memory 20 writes the data stored in the internal buffer 202 to the flash memory cell 200. When this writing is completed, the internal controller 201 notifies the sequencer 232 of the ready state.

When the sequencer 232 releases the right to use the CPU bus 27 in step 6, the sequencer 232
In step 7, the system waits for the ready state to be notified from the flash memory 20. When the ready state is notified, the process proceeds to step 8 to acquire the right to use the CPU bus 27 again. Issue a status acquisition flash command to the flash memory 20.

In response to the status acquisition flash command, the internal controller 201 of the flash memory 20 which is in a command waiting state determines whether or not data writing to the flash memory cell 200 has succeeded to the sequencer 232. You will be notified of the status.

When the sequencer 232 issues a status acquisition flash command in step 9, the sequencer 232 acquires the status sent from the flash memory 20 in step 10.
Then, the right to use the CPU bus 27 is released. Finally, in step 12, a processing end flag is set in the end display register 234, and the processing ends. in this way,
According to the present invention, the sequencer 232 employs a configuration in which the right to use the CPU bus 27 is maintained until the status acquisition is completed in the process of writing data to the flash memory 20 ending with the status acquisition. Instead, when the flash memory 20 is in a busy state by entering internal processing, the CPU bus 2
7 is temporarily released, and when the internal processing is completed and the flash memory 20 becomes ready, the usage right of the CPU bus 27 is acquired again and the status is acquired. take.

Thus, when the flash memory 20 is in a busy state, the right to use the CPU bus 27 is
U21, and from this time, the CPU 21
Another process using the U bus 27 can be executed.

When the sequencer 232 receives the data read access instruction from the CPU 21, the sequencer 232 enters a data read routine, and first, as shown in the processing flow form of FIG. CP
The right to use the U bus 27 is acquired. Then, step 2
Then, a flash command for reading data is issued to the flash memory 20.

In response to the data read flash command, the internal controller 201 of the flash memory 20 in a command waiting state reads the specified data from the flash memory cell 200 and enters a process of storing the specified data in the internal buffer 202. And the sequencer 232
Is notified that the device is busy.

When the sequencer 232 issues a flash command for reading data in step 2, the sequencer 232 waits for a notification of the busy state from the flash memory 20 in step 3, and then notifies the busy state. Then, the process proceeds to step 4, where the right to use the CPU bus 27 is temporarily released.

During the release of the right to use the CPU bus 27,
The internal controller 201 of the flash memory 20 reads data from the flash memory cell 200 to the internal buffer 202. When the reading is completed, the internal controller 201 notifies the sequencer 232 of the ready state, and The buffer 202 is notified of the transmission of the read data.

When the sequencer 232 releases the right to use the CPU bus 27 in step 4, the sequencer 232
In step 5, the system waits for the ready state to be notified from the flash memory 20, and when the ready state is notified, proceeds to step 6 to acquire the right to use the CPU bus 27 again.

Subsequently, in step 7, the data sent from the flash memory 20 is received, and in step 8, the right to use the CPU bus 27 is released. And
Finally, in step 9, a processing end flag is set in the end display register 234, and the processing ends.

As described above, in accordance with the present invention, the sequencer 232 holds the right to use the CPU bus 27 until the data reading is completed in the data reading process from the flash memory 20 that ends with the data reading. When the flash memory 20 is in a busy state by entering internal processing instead of continuing, the right to use the CPU bus 27 is temporarily released, and the ready state is established when the internal processing ends. , The right to use the CPU bus 27 is acquired again to receive data.

When the flash memory 20 is in a busy state, the right to use the CPU bus 27 is
U21, and from this time, the CPU 21
Another process using the U bus 27 can be executed.

When the sequencer 232 receives a data erasure access instruction from the CPU 21, the sequencer 232 enters a data erasure routine, and first, as shown in the processing flow format of FIG. CPU bus 2
Acquire the right to use 7. Subsequently, in step 2, a flash command for erasing data is issued to the flash memory 20.

In response to the flash command for erasing the data, the flash memory 2 in a command waiting state
The internal controller 201 of “0” notifies the sequencer 232 that it is busy by starting the process of erasing specified data stored in the flash memory cell 200.

When the sequencer 232 issues a flash command for erasing data in step 2, the sequencer 232 waits for a notification of a busy state from the flash memory 20 in step 3, and then notifies the busy state. Then, the process proceeds to step 4 where the CPU bus 2
7 is temporarily released.

During the release of the right to use the CPU bus 27,
The internal controller 201 of the flash memory 20 erases the specified data stored in the flash memory cell 200. When the erasing is completed, the internal controller 201 notifies the sequencer 232 that the flash memory cell 200 is in the ready state. .

When the sequencer 232 releases the right to use the CPU bus 27 in step 4, the sequencer 232
In step 5, the system waits for the ready state to be notified from the flash memory 20. When the ready state is notified, the process proceeds to step 6 to acquire the right to use the CPU bus 27 again. Issue a status acquisition flash command to the flash memory 20.

In response to the status acquisition flash command, the internal controller 201 of the flash memory 20 in a command waiting state asks the sequencer 232 whether the data stored in the flash memory cell 200 has been successfully erased. You will be notified of the status.

When the sequencer 232 issues a status acquisition flash command in step 7, the sequencer 232 acquires the status sent from the flash memory 20 in step 8.
The right to use the CPU bus 27 is released. Then, finally, at step 10, a process end flag is set in the end display register 234, and the process ends.

As described above, according to the present invention, the sequencer 232 holds the right to use the CPU bus 27 until the status acquisition is completed in the process of erasing the data in the flash memory 20 which ends with the status acquisition. Rather than adopting a configuration of continuing, when the flash memory 20 enters a busy state by entering internal processing, the right to use the CPU bus 27 is temporarily released, and the flash memory 20 is terminated by ending the internal processing. When the device becomes ready, the right to use the CPU bus 27 is acquired again and the status is acquired.

When the flash memory 20 is in a busy state, the right to use the CPU bus 27 is
U21, and from this time, the CPU 21
Another process using the U bus 27 can be executed.

In the processing flow of FIG.
Then, after issuing a write flash command, in a succeeding step 5, it waits for a busy state to be notified from the flash memory 20, and when a busy state is notified, in a step 6, the CPU bus 27 Although the use right is released, it is known that when the write flash command is issued, the flash memory 20 enters the internal processing and shifts to the busy state, so that the processing in step 5 is omitted. As shown in the processing flow format of FIG. 10, it is possible to adopt a configuration in which, after issuing a write flash command in step 4, immediately proceed to step 6 and release the right to use the CPU bus 27. It is.

In the processing flow format of FIG. 8, after issuing a read flash command in step 2,
In the subsequent step 3, the system waits for the notification of the busy state from the flash memory 20, and when the busy state is notified, releases the right to use the CPU bus 27 in step 4. It is known that when the read flash command is issued, the flash memory 20 enters the internal processing and shifts to the busy state. Therefore, the processing in step 3 is omitted and the processing is performed as shown in the processing flow format of FIG. Alternatively, it is possible to adopt a configuration in which, after issuing a write flash command in step 2, immediately proceed to step 4 to release the right to use the CPU bus 27.

Further, in the processing flow format of FIG. 9, after issuing a flash command for erasing in step 2 and then in step 3 waiting for a notification of the busy state from the flash memory 20, the busy state is changed. When notified, in step 4, the right to use the CPU bus 27 is released. However, when a flash command for erasing is issued, the flash memory 20 enters an internal process and shifts to a busy state. Therefore, the process of step 3 is omitted, and as shown in the process flow form of FIG. 12, after issuing the erase flash command in step 2, immediately proceed to step 4, and It is possible to adopt a configuration in which the right to use the bus 27 is released.

If the configuration according to the processing flow format shown in FIGS. 10 to 12 is adopted, the flash controller 23
Since the unnecessary right to use the CPU bus 27 can be immediately released, efficient operation of the right to use the CPU bus 27 can be realized.

FIG. 13 is a time chart in the case of following the processing flow format of FIG. 9, and FIG. 14 is a time chart in the case of following the processing flow format of FIG. In the figure, XB
REQ is the CPU issued by the flash controller 23
XBACK indicates a request for the right to use the bus, XBACK indicates a permission signal of the CPU 21 for the request for the right to use the CPU bus 27, and XFCE indicates the flash memory 20 to be enabled.
XFWP indicates the flash memory 20
FCLE indicates a command latch enable signal serving as a flash command synchronization signal, FALE indicates an address latch enable signal serving as an erase address synchronization signal, and XFRE indicates a read enable signal for the flash memory 20. Indicates that
XFWE indicates a write enable signal of the flash memory 20, XFBSY indicates a ready / busy signal of the flash memory 20, CD indicates a flash command issued to the flash memory 20, and COMPL.
Indicates a processing end signal.

The flash command for erasing (1
st code), indicates an erase destination address (1st code), indicates an erase destination address (2nd code), indicates an erase flash command (2nd code), indicates a status acquisition flash command,
Indicates a status.

As can be seen from the time charts of FIGS. 13 and 14, when the processing flow of FIG. 9 is followed, the flash memory 20 enters the internal processing in response to the issuance of the erasing flash command, thereby causing a busy state. Is detected, the processing to release the right to use the CPU bus 27 is adopted. On the other hand, according to the processing flow of FIG. 10, when the erase flash command is issued, A configuration is adopted in which the right to use the CPU bus 27 is immediately released in synchronization with the issuance.

As described above, the internal controller 201 of the flash memory 20
3 while the data in the flash memory cell 200 is being erased or the internal buffer 2
During writing data from the flash memory cell 200 to the flash memory cell 200 or reading data from the flash memory cell 200 to the internal buffer 202, the flash controller 23 is notified of a busy state.

The characteristics of the flash memory 20 can be used to easily check whether the flash memory 20 is actually mounted and whether the mounted flash memory 20 is out of order. Become.

FIGS. 15 and 16 show an embodiment of a processing flow executed by the CPU 21 to realize this inspection processing. When the memory card 1a is started, the CPU 21 starts execution of the inspection program expanded in the ROM 22, and first, as shown in the processing flow of FIGS. The configuration information for recording information such as the number of flash memories 20 stored in the flash memory 20 is read. As mentioned above,
Since the first flash memory 20 stores configuration information such as the number of flash memories 20 to be mounted, the configuration information is read out first.

Subsequently, in step 2, it is determined whether or not the configuration information has been read from the first flash memory 20 in accordance with the processing in step 1, and if it is determined that the configuration information cannot be read, the first flash memory 20 is read. If it is determined that there is an abnormality (not mounted or malfunctioning), the process proceeds to step 8, where a system abnormality is recorded and the process is terminated.

Although not described in FIG. 2, as shown in FIG. 17, the host controller 24
In order to notify the personal computer 2a of the state of “a”,
A system status register 24 accessible from the personal computer 2a is provided. When the CPU 21 determines in step 2 that there is an abnormality in the first flash memory 20, the CPU 21 records the system abnormality in the system status register 24 to notify the personal computer 2a of the abnormality, and terminates the processing. I do.

On the other hand, when it is determined in step 2 that the configuration information has been read from the first flash memory 20, the process proceeds to step 3, and the variable i indicating the chip number of the flash memory 20 is stored in the variable i indicating the next flash memory. “1” indicating the chip number of the memory 20 is set.

Subsequently, in step 4, a read command is issued to the flash memory 20 of the chip number indicated by the variable i. Although not described in FIG. 2, as shown in FIG. 17, the sequencer 2 of the flash controller 23
32, a flash status register 2320 (including the end display register 234 shown in FIG. 4) for holding status information of each flash memory 20 is prepared. The sequencer 232 responds to an instruction from the CPU 21. After the read command is issued to the flash memory 20 and the flash memory 20 shifts to a busy state, the flash memory 20 detects this and performs a process of recording the fact in the flash status register 2320.

From now on, when a read command is issued to the flash memory 20 of the chip number indicated by the variable i in step 4, subsequently, in step 5, the sequencer 2
The status of the flash memory 20 is checked by referring to the flash status register 2320 included in the flash memory 32.

Subsequently, in step 6, according to the check processing in step 5, it is determined whether or not the flash memory 20 of the chip number indicated by the variable i has shifted to the busy state, and it is determined that the flash memory 20 does not shift to the busy state. If so, the process proceeds to step 7, where it is determined whether a specified time has elapsed since the issuance of the read command.

When it is determined that the specified time has not elapsed since the issuance of the read command in accordance with the processing in step 7, the flow returns to step 5 to check whether or not the flash memory 20 shifts to the busy state. To continue and determine that the specified time has elapsed,
Proceeding to step 8, the system abnormality is recorded in the system status register 24 provided in the host controller 24, and the processing is terminated.

As described above, when it is detected that the flash memory 20 of the chip number indicated by the variable i does not shift to the busy state even after the specified time has elapsed since the issuance of the read command, the flash memory 20 has an abnormality ( It is determined that there is any (not mounted or out of order), and the process proceeds to step 8, where a system abnormality is recorded and the process is terminated.

On the other hand, when it is determined in step 6 that the flash memory 20 has shifted to the busy state in response to the issuance of the read command, the process proceeds to step 9 (the processing flow in FIG. 16), and the value of the variable i is changed. When the value of the incremented variable i is increased by one in the subsequent step 10 and it is determined whether or not the number of chips specified by the configuration information obtained in step 1 is exceeded, and it is determined that the value is not exceeded, Returning to step 4, a read command is issued to the next flash memory 20. When it is determined that the read command has been exceeded, the process proceeds to step 11, where the system status register 24 provided in the host controller 24 indicates that the system is normal. The recording is completed, and the process ends.

That is, the CPU 21 sets the memory card 1
When a is activated, as shown in the time chart of FIG. 18, the flash memory 20 to be inspected is enabled by the chip enable signal (XFCE) via the flash controller 23, and then the command latch enable is first activated. In synchronization with the signal (FCLE) and the write enable signal (XFWE), a read command “00H” is sent to the flash memory 20 to be inspected.
In synchronization with the address latch signal (FALE) and the write enable signal (XFWE), the read destination address signal “A0-7, A8-16, A
17-23 ", and in response to these transmissions, the flash memory 20 to be inspected enters an internal process (a process of reading read data from the flash memory cell 200 to the internal buffer 202) to shift to a busy state. Then, it is determined that the flash memory 20 is operable.

Although not described in FIG. 2, FIG.
As shown in FIG.
A register group 235 (including the command register 230 shown in FIG. 4) holding an address, a command, a chip number, and the like issued by the U 21 is prepared, and the internal controller 201 of the flash memory 20 A register group 2010 for holding addresses and commands to be issued is prepared.
The read command “00H” issued by U21 is written to the register group 235 of the flash controller 23, and then written to the register group 2010 of the flash memory 20 according to the instruction of the flash controller 23.

As described above, when the memory card 1a is activated, the CPU 21 issues a read command to the flash memory 20 by executing the processing flow of FIGS. It is checked whether or not the flash memory 20 shifts to the busy state in response to the issuance. If there is a flash memory 20 that does not shift to the busy state, a system error is recorded in the system status register 24 of the host controller 24, When all the flash memories 20 shift to the busy state, the system status register 24 of the host controller 24 records whether the mounted flash memory 20 is operable with respect to the personal computer 2a. To notify It is to sense.

Here, in executing this inspection processing, a configuration in which a read command is issued is adopted. When a write command is issued, data irrelevant to the original processing is written to the flash memory 20. This is because if the erase command is issued, the data will be erased from the flash memory 20. However, if such a problem does not cause any inconvenience, the read command Alternatively, a configuration for issuing a write command or an erase command can be adopted.

In the processing flow of FIG. 15 and FIG. 16, upon detecting that the flash memory 20 shifts to the busy state in response to the issuance of the read command, it is immediately determined that the flash memory 20 to which the read command is issued is normal. Although it is configured to make a determination, after confirming that the flash memory 20 shifts to the ready state again,
It is also possible to adopt a configuration of determining that it is normal.

When employing this configuration, the CPU 21
The processing flow of FIG. 19 is executed instead of the processing flow of FIG. That is, in step 6 of the processing flow of FIG.
In response to the issuance of the read command, the flash memory 20
When it is determined that the device has shifted to the busy state, FIG.
As shown in the processing flow of FIG. 9, in step 9, the flash status register 232 of the sequencer 232 is provided.
The status of the flash memory 20 is checked by referring to “0”.

Subsequently, in step 10, according to the check processing in step 9, it is determined whether or not the flash memory 20 of the chip number indicated by the variable i has shifted to the ready state, and it is determined not to shift to the ready state. If so, the process proceeds to step 11, where it is determined whether or not a specified time has elapsed since the shift to the busy state.

When it is determined that the specified time has not elapsed from the transition to the busy state according to the processing in step 11, the flow returns to step 9 to check whether or not the flash memory 20 transitions to the ready state. When the process is continued and it is determined that the specified time has elapsed, the process proceeds to step 12, where a system error is recorded in the system status register 24 provided in the host controller 24, and the process ends.

On the other hand, when it is determined in step 10 that the flash memory 20 has shifted to the ready state,
Proceeding to step 13, the value of the variable i is incremented by one. In the following step 14, the value of the incremented variable i exceeds the number of chips specified by the configuration information obtained in step 1 of the processing flow of FIG. If it is determined that the time has not exceeded the time limit, the process returns to step 4 of the processing flow in FIG. 15 and a read command is issued to the next flash memory 20 to determine that the time has exceeded the value. When the determination is made, the process proceeds to step 15, where the normal status of the system is recorded in the system status register 24 provided in the host controller 24, and the process ends.

As described above, in the processing flow of FIGS. 15 and 16, upon detecting that the flash memory 20 shifts to the busy state in response to the issuance of the read command, the flash memory 20 to which the read command is issued is immediately sent. Is determined to be normal, but C
The PU 21 executes the processing flow of FIG. 19 instead of the processing flow of FIG. 16 so as to confirm that the flash memory 20 shifts to the ready state again and determine that the flash memory 20 is normal. Become.

In the processing flows of FIGS. 15 and 16, when it is determined that one flash memory 20 is abnormal, the check processing for checking whether or not the remaining flash memories 20 are normal is interrupted. Was taken,
It is also possible to adopt a configuration in which the check processing of the remaining flash memory 20 is continued and a configuration in which the number of the flash memory 20 is abnormal is recorded in the system status register 24.

In the processing flows of FIGS. 15 and 16, the inspection process is started when the memory card 1a is activated. In addition to this, when the memory card 1a is started, The inspection process may be started at another timing such as when returned from the user due to an abnormality in 1a.

The present invention has been described with reference to the illustrated embodiments.
The present invention is not limited to this. For example, in the embodiments, the present invention has been described with a specific example in which the flash memory 20 is mounted. However, the present invention is not limited to the application to the flash memory 20 and can be implemented by entering internal processing of memory control. Any memory with an internal processing function that adopts a configuration that outputs a busy signal can be applied as it is.

Further, in the embodiment, the present invention has been described by taking the application to the memory card 1a as a specific example. However, the present invention is not limited to the application to the memory card 1a, and is applicable to a wide range of general memory devices. Applicable.

[0113]

As described above, according to the present invention, the memory with the internal processing function having the function of performing the internal processing of the memory control is controlled, and the memory with the internal processing function, the CPU, and the controller are shared. Focusing on the characteristic that the memory with internal processing function becomes busy when the memory with internal processing function enters the internal processing of memory control when adopting the configuration connected by bus, with internal processing function in response to the command issued by the controller When the memory enters internal processing, the controller performs processing to temporarily release the acquired right to use the common bus, so that the controller does not needlessly hold the right to use the common bus.

As a result, the CPU can execute other processing using the common bus, and can efficiently operate the right to use the common bus, thereby improving the processing efficiency.

Further, according to the present invention, a memory having an internal processing function having a function of performing internal processing of memory control is to be controlled, and the memory having the internal processing function, the CPU, and the controller are connected by a common bus. Attention is paid to the characteristic that the memory with the internal processing function enters a busy state when the memory with the internal processing function enters the internal processing of the memory control. Since the process for immediately releasing the right to use the common bus without confirming that the memory with the internal processing function shifts to the busy state is performed, the right to use the common bus is not needlessly held.

As a result, the CPU can execute another process using the common bus, and can efficiently operate the right to use the common bus, thereby improving the processing efficiency.

In the present invention, when a memory with an internal processing function having a function of performing internal processing of a memory control receives a command, it takes advantage of the characteristic that the memory enters a busy state by entering an internal processing of the memory control. Command to the memory with internal processing function that will be
In response to this, it is checked whether or not the memory with the internal processing function shifts to a busy state (further, it may be checked whether or not the memory shifts to a ready state).
A configuration is used to check whether the memory with the internal processing function is actually installed and whether the memory with the internal processing function is malfunctioning. It becomes very easy to check whether the memory is mounted and whether the memory with the internal processing function is malfunctioning.

On the other hand, in the related art, a configuration is adopted in which prescribed data is written to a memory and the data is subsequently read, and it is checked whether or not the read data matches the written data. , It was configured to judge whether the memory is normal or not, but without following such a complicated procedure, whether the memory with internal processing function is actually installed, It is possible to check whether or not a memory with an internal processing function that has not failed.

[Brief description of the drawings]

FIG. 1 is a principle configuration diagram of the present invention.

FIG. 2 is a circuit configuration example of a memory card of the present invention.

FIG. 3 is an explanatory diagram of a flash memory.

FIG. 4 is an explanatory diagram of a flash controller.

FIG. 5 is an example of a processing flow executed by a CPU.

FIG. 6 is an explanatory diagram of a process executed by a flash controller.

FIG. 7 is an explanatory diagram of a process executed by a sequencer.

FIG. 8 is an explanatory diagram of a process executed by a sequencer.

FIG. 9 is an explanatory diagram of a process executed by the sequencer.

FIG. 10 is an explanatory diagram of a process executed by a sequencer.

FIG. 11 is an explanatory diagram of a process executed by a sequencer.

FIG. 12 is an explanatory diagram of a process executed by a sequencer.

FIG. 13 is a time chart of an erasing process.

FIG. 14 is a time chart of an erasing process.

FIG. 15 is an example of a processing flow executed by a CPU.

FIG. 16 is an example of a processing flow executed by a CPU.

FIG. 17 is an explanatory diagram of a memory card.

FIG. 18 is a time chart of an inspection process.

FIG. 19 is another embodiment of the processing flow executed by the CPU.

FIG. 20 is an explanatory diagram of a conventional technique.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Memory device 10 Memory with internal processing function 11 CPU 12 Controller 13 Bus 14 First execution means 15 Second execution means 16 Third execution means 17 Detection means 18 Instruction means

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Tomohiro Hayashi 2--15-16 Shin-Yokohama, Kohoku-ku, Yokohama-shi, Kanagawa Prefecture Within Fujitsu Computer Technology Co., Ltd. 16 Fujitsu Computer Technology Co., Ltd. (72) Inventor Ken Nagase 2--15-15 Shin-Yokohama, Kohoku-ku, Yokohama, Kanagawa Prefecture Fujitsu Computer Technology Co., Ltd. (72) Inventor 4-1-1 1-1 Fujitsu Limited F term (reference) 5B060 MB04 MM18 5B061 BA01 BB14 QQ04 RR03 RR06

Claims (18)

[Claims] 1. A memory having an internal processing function having a function of performing internal processing of memory control using an internal buffer is to be controlled, and a right to use a bus used by another processing unit is acquired, and the memory with the internal processing function is acquired. A memory control method for controlling the memory with an internal processing function by issuing a command, the method comprising: issuing a command to the memory with an internal processing function; , Release the right to use the bus, and then wait for the memory with internal processing to transition from the busy state to the ready state, and in this waiting state, the memory with the internal processing function transitions to the ready state A memory control method for acquiring a right to use the bus and performing processing so as to continue the processing. 2. A memory having an internal processing function having a function of performing internal processing of memory control using an internal buffer is to be controlled, and a right to use a bus used by another processing unit is acquired, and the memory having the internal processing function is acquired. A memory control method for controlling a memory having an internal processing function by issuing a command, wherein the command causing a busy state of the memory having an internal processing function is issued to the memory having an internal processing function. Releases the right to use the bus without confirming that it will enter the busy state, and then waits for the internal processing memory that becomes busy in response to the command to enter the ready state. If it is detected that the memory with the internal processing function shifts to the ready state while in this wait state, the right to use the bus is acquired. A memory control method characterized by performing processing so that the processing is continued. 3. The memory control method according to claim 1 or 2, wherein a time elapsed in a state where the memory with the internal processing function does not shift to the ready state is detected, and when the specified time is detected by the detection processing,
A memory control method characterized by processing for forcibly terminating control processing of a memory with an internal processing function. 4. The memory control method according to claim 1, wherein a command is issued to the memory with the internal processing function when the memory with the internal processing function is activated. By checking whether the memory shifts to the busy state, it is processed to determine whether the memory with the internal processing function is not connected and whether the memory with the internal processing function has failed A memory control method. 5. The memory control method according to claim 1, wherein a command is issued to the memory with the internal processing function when the memory with the internal processing function is activated. Checking whether the memory shifts to the ready state after shifting to the busy state indicates whether the memory with the internal processing function is not connected or whether the memory with the internal processing function has failed. A memory control method characterized by performing processing to judge. 6. A CPU, a memory with an internal processing function having a function of internally processing memory control using an internal buffer, and a controller for acquiring a right to use a common bus and issuing a command to the memory with the internal processing function. A memory device in which the CPU, the memory with the internal processing function, and the controller are connected to the common bus, wherein the controller issues a command to the memory with the internal processing function, First execution means for releasing the right to use the bus when the memory with the internal processing function shifts to a busy state on the way; and following the execution processing of the first execution means, the memory with the internal processing function is busy. A second execution unit that waits for a transition from a state to a ready state, and a memory with an internal processing function transitions to a ready state by execution processing of the second execution unit. When waiting for, the internal processing function memory is detected that the shift to the ready state, further comprising a third execution means for continuing the acquisition and processing use right of the bus, the memory device comprising. 7. A CPU, a memory with an internal processing function having a function of internally processing memory control using an internal buffer, and a controller for acquiring a right to use a common bus and issuing a command to the memory with the internal processing function A memory device in which the CPU, the memory with the internal processing function, and the controller are connected to the common bus, wherein the controller internally issues a command that causes a busy state of the memory with the internal processing function. First execution means for releasing the right to use the bus without confirming that the memory with internal processing function shifts to a busy state when issuing to the memory with processing function; and execution of the first execution means. A second execution unit that waits for the memory with the internal processing function, which is in a busy state in response to the command issuance, to transition to a ready state following the processing; When waiting for the memory with the internal processing function to shift to the ready state by the execution processing of the second execution means, detecting that the memory with the internal processing function shifts to the ready state acquires the right to use the bus. And a third execution unit that continues processing. 8. The memory device according to claim 6, wherein the operation with the CPU monitors the operation state of the controller to detect a lapse of time when the memory with the internal processing function does not shift to the ready state. Operating on the CPU and instructing the controller to forcibly end the control processing of the memory with the internal processing function when the detecting means detects the elapse of the specified time. And a memory device. 9. The memory device according to claim 6, which operates on a CPU and, when the memory with an internal processing function is activated, sends a command to the memory with an internal processing function via a controller. Issuing means for issuing; and operating on the CPU to check whether the memory with the internal processing function shifts to a busy state in response to the command issued by the issuing means. A memory device comprising: a determination unit configured to determine whether the memory is not connected, and whether the memory with the internal processing function has failed. 10. The memory device according to claim 6, which operates on a CPU and, when the memory with the internal processing function is activated, sends a command to the memory with the internal processing function via the controller. Issuing means for issuing, and operating on the CPU, in response to the command issued by the issuing means, checking whether the memory with the internal processing function shifts to the ready state after shifting to the busy state. A memory device having a function of determining whether the memory with the internal processing function is not connected and whether or not the memory with the internal processing function has failed. 11. A memory control method for controlling a memory with an internal processing function having a function of performing internal processing of a memory control using an internal buffer. It is issued to the memory with internal processing function, and subsequently, whether the memory with internal processing function is connected is checked by checking whether the memory with internal processing function shifts to the busy state. A memory control method characterized by performing processing so as to determine whether or not a device has failed. 12. A memory control method for controlling a memory with an internal processing function having a function of performing an internal processing of a memory control using an internal buffer, the method comprising: By issuing a message to the memory with internal processing function and then checking whether the memory with internal processing function shifts to the ready state after shifting to the busy state, it can be determined whether the memory with internal processing function is connected or not. A memory control method for determining whether a memory with an internal processing function has failed. 13. The memory control method according to claim 11, wherein when the memory with the internal processing function is activated, processing is performed so as to issue a read command to the memory with the internal processing function. . 14. A CPU, a memory with an internal processing function having a function of internally processing memory control using an internal buffer, and a command issued to the memory with an internal processing function in response to an instruction from the CPU. A memory device comprising: a controller that controls a memory with an internal processing function. The memory device operates on a CPU and issues a command to the memory with an internal processing function via the controller when the memory with the internal processing function is activated. Means for operating on the CPU and checking whether the memory with internal processing function shifts to a busy state in response to the command issued by the issuing means, thereby connecting the memory with internal processing function. It is provided with a judgment means for judging whether the memory with internal processing function has failed or not. Characteristic memory device. 15. A CPU, a memory with an internal processing function having a function of internally processing memory control using an internal buffer, and a command issued to the memory with an internal processing function in response to an instruction from the CPU. A memory device comprising: a controller that controls a memory with an internal processing function. The memory device operates on a CPU and issues a command to the memory with an internal processing function via the controller when the memory with the internal processing function is activated. Means operating on the CPU to check whether or not the memory with the internal processing function shifts to the ready state after shifting to the busy state in response to the command issued by the issuing means. A judgment is made to determine whether the memory with function is not connected and whether the memory with internal processing function has failed. Further comprising a means, a memory device according to claim. 16. The memory device according to claim 14, wherein the issuing means performs processing so as to issue the read command to the memory with the internal processing function. 17. A CPU and a memory having an internal processing function having a function of internally processing memory control using an internal buffer via a common bus, and acquiring a right to use the bus to perform the internal processing. A controller that controls a memory with an internal processing function by issuing a command to the memory with a function, issues a command to the memory with an internal processing function, and then shifts the memory with the internal processing function to a busy state during processing. A first execution unit for releasing the right to use the bus; and a second execution unit that waits for the memory with the internal processing function to transition from the busy state to the ready state following the execution processing of the first execution unit. An execution unit, when the memory with the internal processing function shifts to the ready state by the execution process of the second execution unit, the memory with the internal processing function becomes ready. And a third execution means for acquiring a right to use the bus and continuing the processing when detecting the transition to the state. 18. A CPU and a memory having an internal processing function having a function of performing internal processing of memory control using an internal buffer via a common bus, and acquiring a right to use the bus to perform the internal processing. A controller for controlling a memory with an internal processing function by issuing a command to the memory with an internal processing function, wherein the controller causes the internal processing function to issue a command that causes a busy state of the memory with the internal processing function. First execution means for releasing the right to use the bus without confirming that the attached memory shifts to a busy state; and following the execution processing of the first execution means, a busy state is issued in response to a command issuance. A second execution unit that waits for the memory with the internal processing function to be in a state to transition to a ready state; and an internal process by the execution process of the second execution unit. When waiting for the function-equipped memory to transition to the ready state, when detecting that the memory with the internal processing function transits to the ready state, a third execution means for acquiring the right to use the bus and continuing the processing is provided. A controller comprising: