KR102305385B1 - 칩 간격 유지 방법 - Google Patents
칩 간격 유지 방법 Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L21/6836—Wafer tapes, e.g. grinding or dicing support tapes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67132—Apparatus for placing on an insulating substrate, e.g. tape
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
- H01L2221/68336—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding involving stretching of the auxiliary support post dicing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/6834—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to protect an active side of a device or wafer
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- Microelectronics & Electronic Packaging (AREA)
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- Condensed Matter Physics & Semiconductors (AREA)
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- Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
Abstract
시트(T2)를 확장시켜 칩 사이에 간격을 형성하는 칩 간격 형성 단계와, 칩 간격 형성 단계를 실시한 후, 칩 사이의 간격을 유지한 상태로 프레임(F)과 피가공물(W) 사이의 시트(T2)를 가열하여 피가공물 외주측에서 늘어난 시트(T2)를 수축시키는 시트 수축 단계를 구비하고, 시트 수축 단계의 실시 전에, 프레임(F)과 피가공물(W) 사이의 시트(T2)에 복수의 열수축 테이프(T3)를 접착하는 단계를 구비하며, 시트 수축 단계에서는 프레임(F)과 피가공물(W) 사이의 시트(T2)를 테이프(T3)와 함께 가열하여 테이프(T3)가 접착된 영역의 시트(T2)를 수축시킨다.
Description
도 2는 레이저 가공 장치에 의해 피가공물의 내부에 개질층을 형성하는 상태를 도시한 단면도이다.
도 3은 피가공물의 이면을 연삭 장치에 의해 피가공물을 연삭하여 소정의 두께로 박화하고, 연삭 압력에 의해 피가공물을 칩으로 분할하는 상태를 도시한 사시도이다.
도 4는 피가공물이 익스팬드 시트에 접착되어 환형 프레임에 의해 지지되고, 또한 피가공물로부터 보호 테이프가 박리된 상태를 도시한 사시도이다.
도 5는 환형 프레임의 내주 가장자리와 피가공물의 외주 가장자리 사이의 익스팬드 시트에 복수의 열수축 테이프를 접착한 상태의 일례를 도시한 평면도이다.
도 6은 칩 간격 확장 장치에, 익스팬드 시트에 접착되어 환형 프레임에 의해 지지된 분할 후의 피가공물을 세팅한 상태를 도시한 단면도이다.
도 7은 칩 간격 확장 장치에 의해 익스팬드 시트를 확장시킴으로써, 각 칩 사이에 소정의 간격을 형성하는 상태를 도시한 단면도이다.
도 8은 환형 프레임의 내주 가장자리와 피가공물의 외주 가장자리 사이의 익스팬드 시트를 열수축 테이프와 함께 가열함으로써 열수축 테이프가 접착된 영역의 익스팬드 시트를 수축시키는 상태를 도시한 단면도이다.
Wb: 피가공물의 이면 S: 분할 예정 라인
D: 디바이스 M: 개질층
C: 칩 T1: 보호 테이프
T1a: 보호 테이프의 점착면 T2: 익스팬드 시트
T2a: 익스팬드 시트의 점착면 T2b: 익스팬드 시트의 기재면
T3: 열수축 테이프 1: 레이저 가공 장치
10: 척 테이블 10a: 척 테이블의 유지면
11: 레이저광 조사 수단 111: 집광기
112: 집광 렌즈 12: 가공 이송 수단
14: 얼라인먼트 수단 140: 적외선 카메라
2: 연삭 장치 20: 유지 테이블
20a: 유지 테이블의 유지면 23: Y축 방향 이송 수단
21: 연삭 수단 210: 회전축
212: 모터 213: 마운트
214: 연삭 휠 214a: 휠 베이스
214b: 연삭 지석 5: 칩 간격 확장 장치
50: 환형 테이블 50a: 환형 테이블의 유지면
50c: 환형 테이블의 개구 52: 고정 클램프
53: 확장 드럼 55: 환형 테이블 승강 수단
550: 실린더 튜브 551: 피스톤 로드
6: 흡인 유지 테이블 60: 흡착부
600: 흡착면 61: 프레임
610: 상면 62: 흡인원
7: 가열 장치
Claims (1)
- 익스팬드 시트에 접착된 상태로 상기 익스팬드 시트를 통해 환형 프레임에 의해 지지되는 피가공물을 구성하는 복수의 칩의 간격을 확장된 상태로 유지하는 칩 간격 유지 방법으로서,
환형 테이블의 유지면 상에 상기 익스팬드 시트를 고정하고, 상기 환형 테이블의 내주측에 배치된 흡인 유지 테이블의 흡착면으로 상기 익스팬드 시트를 흡인 유지하지 않는 상태로 지지하며, 상기 유지면과 상기 흡착면을 상하 방향으로 상대적으로 이동시켜 상기 익스팬드 시트를 확장시켜 상기 칩 사이에 간격을 형성하는 칩 간격 형성 단계와,
상기 칩 간격 형성 단계를 실시한 후, 상기 익스팬드 시트의 상기 칩에 대응하는 영역을 상기 흡인 유지 테이블의 상기 흡착면으로 흡인 유지하여 상기 칩 사이의 간격을 유지한 상태로, 환형 프레임의 내주 가장자리와 피가공물의 외주 가장자리 사이의 익스팬드 시트를 가열하여 피가공물의 외주측에서 늘어난 상기 익스팬드 시트를 수축시키는 익스팬드 시트 수축 단계를 구비하고,
적어도 상기 익스팬드 시트 수축 단계를 실시하기 전에, 환형 프레임의 내주 가장자리와 피가공물의 외주 가장자리 사이의 익스팬드 시트에 복수의 직사각형 형상의 열수축 테이프를 접착하는 열수축 테이프 접착 단계를 더 구비하며,
상기 익스팬드 시트 수축 단계에서는 환형 프레임의 내주 가장자리와 피가공물의 외주 가장자리 사이의 익스팬드 시트를 상기 열수축 테이프와 함께 가열함으로써 상기 열수축 테이프가 접착된 영역의 상기 익스팬드 시트를 수축시키는 것인, 칩 간격 유지 방법.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
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JP2016176352A JP6741529B2 (ja) | 2016-09-09 | 2016-09-09 | チップ間隔維持方法 |
JPJP-P-2016-176352 | 2016-09-09 |
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KR20180028932A KR20180028932A (ko) | 2018-03-19 |
KR102305385B1 true KR102305385B1 (ko) | 2021-09-24 |
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KR (1) | KR102305385B1 (ko) |
CN (1) | CN107808847B (ko) |
TW (1) | TWI718326B (ko) |
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JP7154809B2 (ja) * | 2018-04-20 | 2022-10-18 | 株式会社ディスコ | ウエーハの加工方法 |
JP2020102569A (ja) * | 2018-12-25 | 2020-07-02 | 東レエンジニアリング株式会社 | 保持テーブル |
JP2022167030A (ja) | 2021-04-22 | 2022-11-04 | 株式会社ディスコ | チップ間隔形成方法 |
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JP2015204362A (ja) * | 2014-04-14 | 2015-11-16 | 株式会社ディスコ | チップ間隔維持方法 |
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- 2017-08-03 TW TW106126221A patent/TWI718326B/zh active
- 2017-08-31 CN CN201710769571.5A patent/CN107808847B/zh active Active
- 2017-09-04 KR KR1020170112608A patent/KR102305385B1/ko active IP Right Grant
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KR100466533B1 (ko) | 1997-02-10 | 2005-06-20 | 린텍 가부시키가이샤 | 칩의제조방법및칩제조를위한점착시트 |
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JP2006203133A (ja) | 2005-01-24 | 2006-08-03 | Lintec Corp | チップ体の製造方法、デバイスの製造方法およびチップ体固着用粘接着シート |
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JP5536555B2 (ja) | 2010-06-22 | 2014-07-02 | 株式会社ディスコ | 拡張テープ収縮装置 |
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JP2015133370A (ja) | 2014-01-10 | 2015-07-23 | 株式会社ディスコ | 分割装置及び被加工物の分割方法 |
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TW201812882A (zh) | 2018-04-01 |
KR20180028932A (ko) | 2018-03-19 |
TWI718326B (zh) | 2021-02-11 |
JP6741529B2 (ja) | 2020-08-19 |
CN107808847A (zh) | 2018-03-16 |
JP2018041894A (ja) | 2018-03-15 |
CN107808847B (zh) | 2023-04-11 |
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