KR101948215B1 - Mother substrate for liquid crystal display device and method of manufacturing the same - Google Patents

Abstract

The present invention relates to a mother substrate for a liquid crystal display and a method of manufacturing the same, and includes a plurality of thin film transistor substrates on which cells having thin film transistors are formed; A guard ring formed to surround the plurality of thin film transistor substrates to form a closed loop and to prevent static electricity; A first wiring and a second wiring connected to the guard ring at an outer portion of the mask shot at the time of exposure to form an equal potential; A first connection pattern connecting the cell to the guard ring; And a second connection pattern connecting the cell with the first wiring or the second wiring, wherein the guard ring, the first and second wiring, and the first and second connection patterns are formed in the same layer with the same material .

Description

TECHNICAL FIELD [0001] The present invention relates to a mother board for a liquid crystal display and a method of manufacturing the mother board.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a mother board for a liquid crystal display and a manufacturing method thereof, and more particularly, to a mother board for a liquid crystal display device and a manufacturing method thereof for preventing defects due to the generation of static electricity .

2. Description of the Related Art [0002] With the development of information society in recent years, demands for the display field have been increasing in various forms. In response to this demand, various flat panel display devices having characteristics such as thinning, light weight and low power consumption have been developed, A liquid crystal display device, a plasma display panel device, and an organic light emitting diode display device have been studied.

Among these, the liquid crystal display device is one of the most widely used flat panel display devices, and includes a liquid crystal panel for displaying an image and a driving part for driving the liquid crystal panel.

The liquid crystal panel includes a thin film transistor substrate having a plurality of thin film transistors, a color filter substrate facing the thin film transistor substrate and having a plurality of color filters corresponding to the thin film transistors, and a liquid crystal layer interposed between the two substrates .

In order to increase production efficiency, a thin film transistor substrate or a color filter substrate of such a liquid crystal panel is formed by forming a plurality of thin film transistor substrates or color filter substrates on a large substrate called a mother substrate, Can be produced.

However, when a plurality of thin film transistor substrates or color filter substrates are fabricated on the mother substrate, there is a problem that the production efficiency is increased during the fabrication process, but the process defects are frequently generated.

For example, during the thin film process of each substrate, static electricity may be generated which causes fatal damage to the thin film transistor due to external or internal factors during sputtering, CVD equipment, or substrate transfer.

Such static electricity causes gate wirings and data wirings to open to cause unevenness when the panel is driven.

Therefore, the conventional thin film transistor substrate is manufactured by applying a structure for preventing static electricity. Hereinafter, an antistatic structure of a conventional thin film transistor substrate will be described with reference to the drawings.

1 is a view showing an antistatic structure of a conventional multi-faced thin film transistor substrate.

As shown in Fig. 1, on the mother substrate 1, a plurality of thin film transistor substrates 10 are formed.

Cells (Cell1 to Cell12) having thin film transistors and the like may be formed on a plurality of thin film transistor substrates 10, respectively.

On the other hand, a guard ring 20 for preventing static electricity is formed on the edge of the mother substrate 1 as a closed loop.

At this time, the plurality of cells (Cell1 to Cell12) may be connected to the guard ring (20) through the connection pattern (30) to achieve an equal potential to prevent static electricity.

In this structure, the fifth and eighth cells (Cell5 and Cell8) formed at the center of the mother substrate 1 among the plurality of cells Cell1 to Cell12 are not connected to the guard ring 20, .

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems and it is an object of the present invention to provide a mother board for a liquid crystal display device and a manufacturing method thereof for preventing a defect caused by the generation of static electricity, .

According to an aspect of the present invention, there is provided a mother substrate for a liquid crystal display, including: a plurality of thin film transistor substrates on which cells having thin film transistors are formed; A guard ring formed to surround the plurality of thin film transistor substrates to form a closed loop and to prevent static electricity; A first wiring and a second wiring connected to the guard ring at an outer portion of the mask shot at the time of exposure to form an equal potential; A first connection pattern connecting the cell to the guard ring; And a second connection pattern connecting the cell with the first wiring or the second wiring, wherein the guard ring, the first and second wiring, and the first and second connection patterns are formed in the same layer with the same material .

Here, the guard ring, the first and second wirings, and the first and second connection patterns may be made equal in potential by any one of a gate signal, a common voltage, and a ground voltage.

The mother substrate for a liquid crystal display includes: a third wiring formed between neighboring cells in the mask shot; And a third connection pattern connecting the cell with the third wiring.

At this time, in the third wiring and the third connection pattern, the guard ring, the first and second wiring, and the first and second connection patterns may be formed in the same layer with the same material.

According to another aspect of the present invention, there is provided a method of manufacturing a mother substrate for a liquid crystal display, comprising: forming a plurality of thin film transistor substrates on which cells having thin film transistors are formed for each mast shot; Forming a guard ring surrounding the plurality of thin film transistor substrates and forming a closed loop for preventing static electricity; Forming a first wiring and a second wiring on the outer surface of the mask shot to be connected to the guard ring so as to form an equal potential; Forming a first connection pattern connecting the cell with the guard ring and a second connection pattern connecting the cell with the first wiring or the second wiring, And the second wiring and the first and second connection patterns are formed on the same layer with the same material.

Here, the guard ring, the first and second wirings, and the first and second connection patterns may be made equal in potential by any one of a gate signal, a common voltage, and a ground voltage.

According to another aspect of the present invention, there is provided a method of manufacturing a mother substrate for a liquid crystal display, comprising: forming a third wiring pattern between neighboring cells within a mask shot, and a third connection pattern connecting the cell with the third wiring; The method comprising the steps of:

At this time, in the third wiring and the third connection pattern, the guard ring, the first and second wiring, and the first and second connection patterns may be formed in the same layer with the same material.

INDUSTRIAL APPLICABILITY As described above, in the mother substrate for a liquid crystal display and the method of manufacturing the same according to the present invention, defects due to static electricity generated in a thin film transistor substrate manufacturing process can be reduced and the yield of the thin film transistor substrate can be improved.

1 is a view showing a conventional multi-faced thin film transistor substrate.
2 is a view schematically showing a thin film transistor substrate according to an embodiment of the present invention.
3 is a flowchart illustrating a manufacturing process of a thin film transistor substrate according to an embodiment of the present invention.
4 is a view illustrating an anti-static structure of a multi-faced thin film transistor substrate according to a first embodiment of the present invention.
FIGS. 5 and 6 are views illustrating an anti-static structure of a multi-faced thin film transistor substrate according to the second and third embodiments of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 2 is a schematic view illustrating a thin film transistor substrate according to an embodiment of the present invention. FIG. 3 is a flowchart illustrating a manufacturing process of a thin film transistor substrate according to an embodiment of the present invention. 1 is a view showing an anti-static structure of a multi-faced pull-off thin film transistor substrate according to an embodiment.

The liquid crystal display device according to the embodiment of the present invention includes a liquid crystal panel (not shown), a source driver (not shown), a gate driver (not shown), and a timing controller (not shown)

The liquid crystal panel includes a thin film transistor substrate having a plurality of thin film transistors, a color filter substrate facing the thin film transistor substrate and having a plurality of color filters corresponding to the thin film transistors, and a liquid crystal layer interposed between the two substrates .

The source driver generates a data signal using the converted image data and the plurality of data control signals transmitted from the timing controller, and supplies the generated data signal to the display area.

At this time, the data signals are transferred to the plurality of source IC pad portions 120 formed on the TFT substrate, and the data signals are supplied to the display region 110 through the plurality of data lines DL.

The gate driver may be formed on a side surface of the thin film transistor substrate using a GIP (Gate In Panel) method. The gate driver generates a gate signal using a plurality of gate control signals transmitted through a timing control unit and a level shift, And supplied to the display region through a plurality of gate lines GL.

Here, the gate control signal may include a gate start pulse (Gate Start Pulse), a gate shift clock (Gate Shift Clock), and the like.

The timing control unit receives a plurality of video signals, a vertical synchronizing signal (Vsync), a horizontal synchronizing signal (Hsync), and a data enable signal (DE) from a system such as a graphic card through an LVDS (Low Voltage Differential Signal) A plurality of control signals can be received.

The timing control unit may generate a data control signal for controlling the source driver and a gate control signal for controlling the gate driver by using a plurality of control signals.

Although not shown, a power supply unit (not shown) may be further provided for generating and supplying a driving voltage for driving the components of the liquid crystal display device using a power supply voltage received from the outside.

2, the thin film transistor substrate 100 according to an embodiment of the present invention may include a display region 110, a source driver pad portion 120, and the like.

In the display region 110, a plurality of gate lines GL and a plurality of data lines DL, which define a plurality of pixels P, may be formed.

A thin film transistor (not shown) connected to a plurality of gate lines GL and a plurality of data lines DL and a pixel electrode (not shown) contacting the drain electrode of the thin film transistor are formed in each pixel P .

When a gate signal is supplied through a gate line GL to turn on a thin film transistor, a data signal supplied through the data line DL is applied to the thin film transistor And storage capacitors.

The liquid crystal display device displays different gradations by applying data signals of various sizes to each pixel, and as a result, various images can be displayed.

The storage capacitor holds the data signal for one frame to maintain the gray level displayed by the liquid crystal display device constant.

Hereinafter, a manufacturing process of a TFT substrate according to an embodiment of the present invention will be described with reference to FIG.

3, a gate metal material such as aluminum (Al), an aluminum alloy (AlNd), copper (Cu), or a copper alloy having low resistance characteristics is first deposited, A gate wiring or the like can be formed by patterning through a process (S100).

Then, silicon oxide (SiO ₂₎ or silicon nitride (SiNx) by depositing an inorganic insulating material such as to form a gate insulating film (not shown) over the entire surface of the substrate, depositing a gate insulating film over the pure amorphous silicon layer or the impurity amorphous silicon layer , And patterned through a mask process to form an active layer (S110).

Next, a pixel electrode may be formed by depositing a transparent conductive material such as indium-tin-oxide (ITO) or indium-zinc-oxide (IZO) (S120).

Then, a metal material layer such as aluminum (Al), an aluminum alloy (AlNd), copper (Cu), or a copper alloy is deposited and patterned through a mask process to form a data line and a source electrode and a drain electrode (S / D) (S130).

Next, an inorganic insulating material such as silicon oxide (SiO ₂ ) or an organic insulating material such as benzocyclobutene (BCB) or photo acryl is applied to the entire surface of the substrate to form a passivation (S 140) .

Then, a transparent conductive material such as indium-tin-oxide (ITO) is deposited on the protective layer and patterned through a mask process to form a common electrode Vcom (S150).

As shown in FIG. 4, a plurality of thin film transistor substrates 100 having the above-described structure may be formed on the mother substrate 1.

A guard ring 200 for preventing static electricity may be formed on the mother substrate 1 to surround a plurality of thin film transistor substrates 100 and form a closed loop.

At this time, the guard ring 200 may be formed on the same layer where the gate line GL is formed of the same material as the gate line GL.

When a material layer (a gate wiring, a gate insulating film, a semiconductor layer, a protective layer, or the like) is deposited on the mother substrate 1 by using sputtering or CVD equipment, sputtering or CVD equipment Is generated mainly at the edge of the mother board 1. [0043]

Therefore, the guard ring 200 may be formed at the edge of the mother substrate 1 to prevent the static electricity from penetrating into the thin film transistor substrate 100.

On the other hand, when the size of the mother substrate is increased or the size of the thin film transistor substrate is reduced, an exposure process is performed for each mask shot (A) as shown in FIG. 4, 100) can be formed.

A first wiring 220 extending in a first direction (vertical direction) and a second wiring 240 extending in a second direction (a horizontal direction) may be formed between the mask shots A, 1 wiring 220 and the second wiring 240 may be connected to the guard ring 200 at equal potential.

Here, the number of the thin film transistor substrates 100 formed for each mask shot A is described as 12. However, the number of the thin film transistor substrates 100 may be variously formed depending on the size of the mother substrate, the size of the thin film transistor substrate, and the like.

A plurality of cells (Cell1 to Cell12) including thin film transistors and the like may be formed on each thin film transistor substrate 100. [

At this time, a plurality of cells (Cell1 to Cell12) may be connected to the guard ring 200 through the first connection pattern 300 to prevent static electricity, but they may be formed at the center of the mask shot A The fifth and eighth cells Cell5 and Cell8 are not connected to the guard ring 200, and thus there is a problem that they are vulnerable to static electricity.

That is, the inside of the guard ring 200 of the mother substrate 1, particularly, the inside of each mask shot A is vulnerable to static electricity.

The cells between the mask shots A may be connected to each other through the first connection pattern 300 to achieve an equal potential.

Therefore, in the fifth and eighth cells (Cell5 and Cell8) formed at the center of the mask shot (A) of the mother substrate 1 having the above-described structure, defects such as thin film transistors or the like in the cells are destroyed by static electricity Can occur.

As the number of substrates of the thin film transistor formed on one mother substrate increases due to the increase of the size of the mother substrate or the size of the thin film transistor substrate, the substrate is formed at the center of the mask shot A and connected to the guard ring 200 The number of the fifth and eighth cells (Cell 5, Cell 8) which are not in contact with each other increases. As a result, the occurrence frequency of defects in the cells due to static electricity increases, and the yield can be further reduced.

Hereinafter, an anti-static structure of the multi-faced thin film transistor substrate according to the second embodiment of the present invention will be described with reference to FIG. 5 as a method for improving the defect caused by the generation of static electricity in the center of the mask shot (A) .

FIGS. 5 and 6 are views illustrating an anti-static structure of a multi-faced thin film transistor substrate according to the second and third embodiments of the present invention.

As shown in FIG. 5, a plurality of thin film transistor substrates 100 having the above-described structure can be formed on the mother substrate 1 by using the mask shots A, respectively.

A guard ring 200 for preventing static electricity may be formed on the mother substrate 1 to surround a plurality of thin film transistor substrates 100 and form a closed loop.

The first wiring 220 extending in the first direction (vertical direction) and the second wiring 240 extending in the second direction (the horizontal direction) may be formed between the mask shots A, 1 wiring 220 and the second wiring 240 may be connected to the guard ring 200 at equal potential.

The cells formed on the rim of the mask shot A are connected to the guard ring 200 or the first wiring 220 and the second wiring 240 through the first connection pattern 300 and the second connection pattern 320, To be connected at equal potential.

At this time, the guard ring 200, the first wirings 220 and the second wirings 240, and the first connection pattern 300 and the second connection pattern 320 may be formed of the same material in the same layer.

For example, the guard ring 200, the first wiring 220 and the second wiring 240, and the first connection pattern 300 and the second connection pattern 320 are formed in the same May be formed in the same layer where the gate wiring GL is formed of a material.

The first through third cells Cell1 through Cell3 may be connected to each other through the third connection pattern 340 to have the same potential.

The third connection pattern 340 may be formed of the same material as the first connection pattern 300 and the second connection pattern 320 in the same layer.

For example, the third connection pattern 340 may be formed on the same layer in which the gate wiring GL is formed of the same material as the gate wiring GL.

6, in the mother substrate of the multi-layered thin film transistor substrate according to the third embodiment of the present invention, the third wiring 260 may be further formed between the cells within the mask shot (A) have.

For example, the third wiring 260 may be formed between the first and second cells Cell1 and Cell2 or between the second and third cells Cell2 and Cell3.

The third wiring 260 may be formed on the same layer on which the gate wiring GL is formed of the same material as the gate wiring GL and may be connected to the guard ring 200 in the same potential.

The first through third cells Cell1 through Cell3 may be connected to the third wiring 260 through the third connection pattern 340 to have the same potential.

The third connection pattern 340 may be formed of the same material as the first connection pattern 300 and the second connection pattern 320 in the same layer.

For example, the third connection pattern 340 may be formed on the same layer in which the gate wiring GL is formed of the same material as the gate wiring GL.

Meanwhile, the guard ring 200, the first wiring 220 and the second wiring 240, and the first connection pattern to the third connection pattern 300 to 340 may form an equal potential using another signal wiring .

In other words, the anti-static structure of the multi-layered thin film transistor according to the present invention forms wirings not only on the edge of the mother substrate and the outline of each mask shot (A) but also inside the mask shot (A) .

At this time, the wiring and the connection pattern for connecting each cell are formed so as to be connected to various wirings such as a gate wiring or a common wiring so as to form an equal potential through various signals such as a gate signal, a common voltage, .

As a result, the present invention can improve the degree of freedom of design and increase the productivity by improving the yield.

The embodiments of the present invention as described above are merely illustrative, and those skilled in the art can make modifications without departing from the gist of the present invention. Accordingly, the protection scope of the present invention includes modifications of the present invention within the scope of the appended claims and equivalents thereof.

100: liquid crystal panel 110: display area
120: source driver pad unit 200: guard ring
300: first connection pattern 320: second connection pattern
340: Third connection pattern

Claims (10)

A guard ring formed to form a closed loop at the edge of the mother substrate on which a plurality of unit areas corresponding to each of the plurality of mask shots are defined;
A plurality of thin film transistor substrates each having cells each having a thin film transistor formed in each of the plurality of unit regions;
A first wiring connected to the guard ring between the unit areas neighboring in the second direction and extending in a first direction perpendicular to the second direction and having an equal potential;
A second wiring connected to the guard ring between the unit areas adjacent to each other in the first direction and forming an equal potential and extending along the second direction;
A first connection pattern connecting the cell adjacent to the guard ring to the guard ring;
And a second connection pattern connecting the cell arranged adjacent to the first wiring or the second wiring to the first wiring or the second wiring,
Wherein the guard ring, the first and second wirings, and the first and second connection patterns are formed of the same material in the same layer.
The method according to claim 1,
Wherein the guard ring, the first and second wirings, and the first and second connection patterns form an equal potential by one of a gate signal, a common voltage, and a ground voltage.
The method according to claim 1,
A third wiring formed between neighboring cells in the unit region;
And a third connection pattern connecting the cell to the third wiring. ≪ Desc / Clms Page number 19 >
The method of claim 3,
The third wiring, and the third connection pattern,
Wherein the guard ring, the first and second wirings, and the first and second connection patterns are formed of the same material in the same layer.
Forming a guard ring on the edge of the mother substrate on which a plurality of unit areas corresponding to each of the plurality of mask shots are defined to form a closed loop for preventing static electricity;
Forming a plurality of thin film transistor substrates in each unit region in which cells having thin film transistors are formed for each of the mask shots;
Forming first wirings extending in a first direction perpendicular to the second direction, the first wirings being connected to the guard ring between the unit regions adjacent to each other in the second direction and forming an equal potential;
Forming a second wiring that is connected to the guard ring between the unit areas neighboring in the first direction to form an equal potential and extends along the second direction;
A first connection pattern connecting the cell arranged adjacent to the guard ring to the guard ring and a second connection pattern connecting the cell arranged adjacent to the first wiring or the second wiring to the first wiring or the second wiring And forming a second connection pattern,
Wherein the guard ring, the first and second wirings, and the first and second connection patterns are formed of the same material in the same layer.
6. The method of claim 5,
Wherein the guard ring, the first and second wirings, and the first and second connection patterns form an equipotential by any one of a gate signal, a common voltage, and a ground voltage. Way.
6. The method of claim 5,
And forming a third connection pattern between neighboring cells in the unit region, the third connection pattern connecting the third wiring and the cell to the third wiring. ≪ Desc / Clms Page number 20 >
8. The method of claim 7,
The third wiring, and the third connection pattern,
Wherein the guard ring, the first and second wirings, and the first and second connection patterns are formed of the same material in the same layer.
The method of claim 3,
Wherein the third wiring extends between the neighboring cells within the unit area in the first direction and is connected to the guard ring
Mosquito board for liquid crystal displays.
8. The method of claim 7,
Wherein the third wiring extends between the neighboring cells within the unit area in the first direction and is connected to the guard ring
A method for manufacturing a mother substrate for a liquid crystal display device.

Images