KR101747885B1 - 시프트 회로 - Google Patents
시프트 회로 Download PDFInfo
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- KR101747885B1 KR101747885B1 KR1020100083869A KR20100083869A KR101747885B1 KR 101747885 B1 KR101747885 B1 KR 101747885B1 KR 1020100083869 A KR1020100083869 A KR 1020100083869A KR 20100083869 A KR20100083869 A KR 20100083869A KR 101747885 B1 KR101747885 B1 KR 101747885B1
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- 238000000034 method Methods 0.000 claims description 6
- 230000003213 activating effect Effects 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 8
- 230000001360 synchronised effect Effects 0.000 description 6
- 230000015654 memory Effects 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 description 2
- 230000004044 response Effects 0.000 description 2
- 230000000630 rising effect Effects 0.000 description 2
- 239000000654 additive Substances 0.000 description 1
- 230000000996 additive effect Effects 0.000 description 1
- 230000001934 delay Effects 0.000 description 1
- 230000003111 delayed effect Effects 0.000 description 1
- 230000000415 inactivating effect Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1072—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/4074—Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/4076—Timing circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/408—Address circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4093—Input/output [I/O] data interface arrangements, e.g. data buffers
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/12015—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details comprising clock generation or timing circuitry
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
- G11C7/109—Control signal input circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
- G11C2207/22—Control and timing of internal memory operations
- G11C2207/2272—Latency related aspects
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- Computer Hardware Design (AREA)
- Databases & Information Systems (AREA)
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Abstract
Description
도 2는 시프트부(101, 102, 110)의 구성도,
도 3은 본 발명의 일실시예에 따른 시프트 회로의 구성도,
도 4는 본 발명의 일실시예에 따른 다수의 클럭제어부(311, 312, 319)의 구성도.
Claims (6)
- 입력신호를 클럭에 동기하여 순차적으로 시프트하는 다수의 시프트부; 및
상기 다수의 시프트부 중 적어도 하나 이상의 시프트부에 구비되는 다수의 클럭 제어부를 포함하고,
상기 다수의 클럭 제어부는 자신에게 대응되는 시프트부의 입력이 활성화되기 이전에 자신에게 대응되는 시프트부에 클럭의 공급을 시작하고, 자신에게 대응되는 시프트부의 출력신호가 활성화되면 자신에게 대응되는 시프트부에 클럭의 공급을 중단하는 시프트 회로.
- [청구항 2은(는) 설정등록료 납부시 포기되었습니다.]제 1항에 있어서,
상기 다수의 클럭 제어부는,
자신에게 대응되는 시프트부 이전의 시프트부의 입력이 활성화되면 자신에게 대응되는 시프트부에 클럭의 공급을 시작하고, 자신에게 대응되는 시프트부의 출력신호가 활성화되면 자신에게 대응되는 시프트부에 클럭의 공급을 중단하는 것을 특징으로 하는 시프트 회로.
- [청구항 3은(는) 설정등록료 납부시 포기되었습니다.]제 1항에 있어서,
상기 입력신호는,
일정한 펄스 폭을 가진 펄스 신호인 것을 특징으로 하는 시프트 회로.
- [청구항 4은(는) 설정등록료 납부시 포기되었습니다.]제 1항에 있어서,
상기 다수의 시프트부는,
디플립플롭으로 구성되는 것을 특징으로 하는 시프트 회로.
- [청구항 5은(는) 설정등록료 납부시 포기되었습니다.]제 1항에 있어서,
상기 다수의 클럭제어부는,
자신에게 대응되는 시프트부 이전의 시프트부의 입력이 활성화되면 인에이블신호를 활성화하고, 자신에게 대응되는 시프트부의 출력이 활성화되면 상기 인에이블 신호를 비활성화하는 인에이블 신호 생성부; 및
상기 인에이블 신호가 활성화되면 상기 클럭을 통과시키고, 상기 인에이블 신호가 비활성화되면 상기 클럭을 통과시키지 않는 클럭 인에이블부
를 포함하는 것을 특징으로 하는 시프트 회로.
- [청구항 6은(는) 설정등록료 납부시 포기되었습니다.]제 5항에 있어서,
상기 인에이블 신호 생성부는,
RS 래치로 구성되는 것을 특징으로 하는 시프트 회로.
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020100083869A KR101747885B1 (ko) | 2010-08-30 | 2010-08-30 | 시프트 회로 |
US13/220,983 US8644106B2 (en) | 2010-08-30 | 2011-08-30 | Shift circuit of a semiconductor device |
CN201110252226.7A CN102403996B (zh) | 2010-08-30 | 2011-08-30 | 半导体器件的移位电路 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
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KR1020100083869A KR101747885B1 (ko) | 2010-08-30 | 2010-08-30 | 시프트 회로 |
Publications (2)
Publication Number | Publication Date |
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KR20120020319A KR20120020319A (ko) | 2012-03-08 |
KR101747885B1 true KR101747885B1 (ko) | 2017-06-27 |
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KR1020100083869A KR101747885B1 (ko) | 2010-08-30 | 2010-08-30 | 시프트 회로 |
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US (1) | US8644106B2 (ko) |
KR (1) | KR101747885B1 (ko) |
CN (1) | CN102403996B (ko) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10366742B1 (en) * | 2018-02-07 | 2019-07-30 | Micron Technology, Inc. | Memory device parallelizer |
KR102638793B1 (ko) * | 2018-10-01 | 2024-02-21 | 에스케이하이닉스 주식회사 | 반도체장치 |
US10902904B1 (en) * | 2019-09-11 | 2021-01-26 | Micron Technology, Inc. | Apparatuses and methods for providing multiphase clocks |
US11468958B1 (en) * | 2021-06-11 | 2022-10-11 | Winbond Electronics Corp. | Shift register circuit and a method for controlling a shift register circuit |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6061418A (en) | 1998-06-22 | 2000-05-09 | Xilinx, Inc. | Variable clock divider with selectable duty cycle |
US7742359B2 (en) | 2004-12-30 | 2010-06-22 | Hynix Semiconductor Inc. | Calibration circuit of a semiconductor memory device and method of operating the same |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH11134893A (ja) * | 1997-10-30 | 1999-05-21 | Sony Corp | シフトレジスタおよびこれを用いたマトリクス型液晶表示装置の駆動回路 |
JP3473745B2 (ja) * | 1999-05-28 | 2003-12-08 | シャープ株式会社 | シフトレジスタ、および、それを用いた画像表示装置 |
KR100600331B1 (ko) * | 2005-05-30 | 2006-07-18 | 주식회사 하이닉스반도체 | 연속적인 버스트 모드로 동작 가능한 슈도 sram |
US7750715B2 (en) * | 2008-11-28 | 2010-07-06 | Au Optronics Corporation | Charge-sharing method and device for clock signal generation |
-
2010
- 2010-08-30 KR KR1020100083869A patent/KR101747885B1/ko active IP Right Grant
-
2011
- 2011-08-30 US US13/220,983 patent/US8644106B2/en active Active
- 2011-08-30 CN CN201110252226.7A patent/CN102403996B/zh active Active
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6061418A (en) | 1998-06-22 | 2000-05-09 | Xilinx, Inc. | Variable clock divider with selectable duty cycle |
US7742359B2 (en) | 2004-12-30 | 2010-06-22 | Hynix Semiconductor Inc. | Calibration circuit of a semiconductor memory device and method of operating the same |
Also Published As
Publication number | Publication date |
---|---|
US20120051172A1 (en) | 2012-03-01 |
CN102403996A (zh) | 2012-04-04 |
CN102403996B (zh) | 2016-08-03 |
KR20120020319A (ko) | 2012-03-08 |
US8644106B2 (en) | 2014-02-04 |
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